Traffic Light Intersection

Version 9.50.11

Jenniffer Estrada
EE365: Advanced Digital Design
Prof. Khondker
December 4, 2008

Executive Summary
A traffic intersection is simulated on the DE1 board, using a button press,
KEY0, for a pedestrian wanting to cross, a switch, SW0, to simulate a car waiting at
the low priority street. Unless there is a pedestrian or a car in the low priority street,
the green light will be set for the high priority street. Key1 is used to return the
system to the initial default state, and 3 red and 3 green LEDs as well as three 7
segment displays are used to display the output of the system.

Problem Description
The traffic light control system will be implemented in a two street
intersection that allows pedestrians to cross on request. A cross-walk button, KEY 0,
can be used to halt all traffic to allow pedestrians to cross. Each traffic signal uses
at two LEDs (green and red) per traffic light or the pedestrian crossing point, one of
the two streets has a priority over the other. For the high priority street, the traffic
signal will always remain green until the low priority street car sensor has been
tripped or a pedestrian has pressed a crosswalk button. The occurrence of such an
event gives the high priority street 5 seconds before the light changes to red.
Switch, SW0, to simulate a car sensor at the low priority street and a button KEY0 to
simulate the crosswalk request button for pedestrian use. Multiple button presses
would be treated as a single press until the pedestrian gets a WALK (green) signal.
The duration of the green light for the low priority street and the pedestrian crossing
is 9 and 4 seconds, respectively. The system utilizes a second button, KEY1, to reset
the circuit, at which the seven segment displays are set to their default values (5, 9,
and 4) and the highest priority street becomes a green light. At no time should there
ever be more than one green light in the system. Each traffic or pedestrian crossing
light of this system will use seven segment displays that will display the number of
seconds left that the light will remain green. When any of these seven segment
displays reach zero they should reset to the default value (5, 9 and 4) and await the
next countdown.

Design Problem Statement

The Traffic Light system defaults to having the high priority street having the
green light unless the low priority street or the pedestrian are triggered. When this
happens, the high priority street HEX2 will count down to zero, and the pedestrian
or the low priority street will count down from 4 and 9 seconds, respectively.

Problem Decomposition
TrafficControl:ControlIntersect

HiDone
Clock

CLOCK_50

Clock

Enable

7' h7F --

LEDR[2..0]

PED

DecodeHex:LowPriority

PedDone

reset

HiCount[3..0]

Edge_Detect:PedCross

LowCount[3..0]

BitInput[3..0]

PedCount[3..0]

Clock
Enable

Enable

HEX2[6..0]
HEX3[6..0]

HexOutput[6..0]

LowDone

lowpriortraffic

ClockCounter:OneMilliSec

BitInput[3..0]

LOWP

EffClock
crosswalktraffic

Clock

DecodeHex:HighPriority
HIP

ClockCounter:OneSec

HEX1[6..0]

HexOutput[6..0]

LEDG[2..0]

Output

Input

DecodeHex:Pedestrian
Edge_Detect:Rst

BitInput[3..0]

HEX0[6..0]

HexOutput[6..0]

Clock
Enable

KEY[1..0]

Output

Input

SW[0..0]

Figure.1. Main Entity TrafficLightIntersection RTL view

countdown9[2..1]
PRE
D

register9

Selector8_OUT

trip9~0

ENA

trip5
SEL[5..0]
OUT
SEL

0
1

countdown5[2]

1' h0 - -

PRE
Q

1' h1 - -

CLR

5' h1D - -

countdown5[1]

SEL

DATAA
4' h5 - -

count4Down~0

A [4.. 0]
B [4.. 0]

PRE

countdown4[3..0]

SEL
DATAA
4' h4 --

DATAB

lowpriortr affic
reset

OUT0

ENA

ENA
CLR

countdown9~[3..0]

Add1
1' h1 - 5' h1D - -

A[4 ..0]
B[4 ..0]

DATAB

PRE
OUT0

LowCount[3..0]
ENA

MUX21

CLR

CLR

SELECTOR

0
1

Selector10

COUNT5_Low
countdown5[3..0]

countdown9[3]

SEL
DATAA
4' h9 - -

ADDER
ENA

DATA[1..0]

LowPrior
Pedestrian
COUNT5_Ped

CLR

ADDER

1' h1 --

Hig hPrior

count9Down~0

NextS~2

L2Ped

Go2Ped~1

MUX21

3' h7 - OUT0

countdown9[3..0]

CLR

SEL[5..0]

5' h00 --

Selector13

LowDone
PedDone

trip9

MUX21

B[4 ..0]

SELECTOR

OUT

1' h1 --

1' h1 --

HiCount[3..0]

ENA
CLR

CurrentS_Pedes trian
CurrentS_COUNT5_Ped
CurrentS_COUNT5_Low

DATA[5..0]

EQUAL

PRE
D

EffClock
WideOr5_OUT0

NextS~2_OUT0

Go2Ped~1_OUT0
CurrentS_LowPrior

ENA

DATA[5..0]

Equal0

CLR

ADDER

PRE
Q

1' h1 -5' h1D - -

ENA
CLR

DATAB

A[4 ..0]

OUT0

DATAB

CLR

countdown4~[3..0]

Add2

OUT

PRE

ENA

A[4 ..0]
B[4 ..0]

2' h3 - -

countdown5~[3..0]

Add0

ENA

Count5Down~0

DATAA

countdown5[3]

PRE
D

regis ter[5..4]

PRE

trip5~[1..0]

NextS~6

trip9~1

cross walktraffic
0

countdown4[3]

PRE

0
1

countdown4[2]

SEL[1..0]

Go2Ped

Selector6

ENA
CLR

res et

PRE

crosswalktraffic

PRE
D

Selector9

CurrentS
clk

Go2Ped

MUX21

ENA
CLR

countdown5[0]

Works ~0
trip9~3

Works ~0_OUT0

1' h1 --

PED
CurrentS_HighPrior

DATA[5..0]

ENA
CLR

LOWP
CurrentS_L2Ped

OUT

PRE
D

SELECTOR

SEL[5..0]

3' h7 --

Works ~2
trip4~2

SELECTOR

1' h0 - -

countdown4[1..0]

Equal2

PRE
D

Works ~3

A [4.. 0]

Q
5' h00 --

B [4.. 0]

PedCount[3..0]

ENA
EQUAL

CLR

Works ~1

1' h0 - -

countdown9[0]

Equal1

PRE
D

A [4.. 0]

Q
5' h00 --

B [4.. 0]

ENA
EQUAL

CLR

trip9~5

Selector11
trip4

SEL[1..0]

PRE
OUT

trip4~0_OUT0
1' h1 --

Selector12

DATA[1..0]

ENA
CLR

SELECTOR

SEL[5..0]

OUT
2' h3 - -

trip9~4

DATA[5..0]

trip9~6
SELECTOR

lowpriortraffic
Clock

Figure.1. Traffic Control RTL view

count~[15..0]

Add0
A [1 5..0]

16' h0001 --

B [1 5..0]

count[15..0]

SEL
DATAA
16' h0000 --

DATAB

ADDER

PRE
OUT0

Equal0

Q
16' hC34E --

B [15 ..0 ]

ENA
MUX21

CLR

Enable~reg0

A [15 ..0 ]

EQUAL

PRE
D

Enable

ENA
CLR

Clock

Figure.2. Clock Counter RTL view

Instead of using a clock divider, a counter is used to count up to an arbitrary value,
UpperBound, to create an enable signal. Since the Altera DE1 board has an internal

50 MHz clock, the counter will count up to 49999999 and 49999, to create a 1
second and 1 millisecond enable signal, respectively.

Q[2..0]
PRE
D

Input
Clock
Enable

OutSig~0

OutSig
PRE
D

Output

ENA

ENA
CLR

CLR

Figure.3. Edge Detect RTL

Edge Detect is used to prevent metastability within the circuit that may
cause glitches. Both D Flip Flops are seeing the same clock and same enable
signal.

Mux0
BitInput[3..0]

SEL[3..0]
16' h1083 --

DATA[15..0]

OUT

MUX

Mux1

SEL[3..0]
16' h208E --

DATA[15..0]

OUT

MUX

Mux2

SEL[3..0]
16' h02BA --

DATA[15..0]

OUT

MUX

Mux3

SEL[3..0]
16' h8692 --

DATA[15..0]

OUT

HexOutput[6..0]

MUX

Mux4

SEL[3..0]
16' hD004 --

DATA[15..0]

OUT

MUX

Mux5

SEL[3..0]
16' hD860 --

DATA[15..0]

OUT

MUX

Mux6

SEL[3..0]
16' h2812 --

DATA[15..0]

OUT

MUX

Figure.4. Seven Segment Display Decoder RTL view

Seven Multiplexers are used to determine the correct output to the seven
segment displays given by BitInput.

Significant Details of Design Process

The design is written to be modular for future use of components. The Top
Level Entity, TrafficLightIntersection, has four components, ClockCounter,
Edge_Detect, TrafficControl and DecodeHex.
One instantiation of ClockCounter.vhd uses the 50Mhz clock from the DE1 board to
count 50000000 pulses to synchronously enable TrafficControl at 1 second intervals
and the other to count 50000 pulses to enable Edge_Detect at 1 millisecond
intervals
Edge_Detect.vhd takes in an input from a key press and sends an enable signal to
TrafficControl confirming that the button has been pressed and released.
Edge_Detect runs at 1 millisecond to ensure that TrafficControl has the correct input
in time.
TrafficControl.vhd controls all three states of the intersection. When initialized, the
system is set to the default settings, with the green light on the high priority light,
and the displays reading the default values, 5, 9, 4. When KEY0 is pressed or SW is
toggled, the system will begin counting down the high priority light and give the
green light to the pedestrian or the low priority light, respectively. The 7 segment
displays will count down until the counter hits zero and will return to the default
state and await another input. KEY1 is used to asynchronously reset the entire
system to the default values.
DecodeHex.vhd takes the four bit binary vector and acts as a 4 to 7 Multiplexer,
displaying the corresponding decimal number on the 7 segment display.
The top level entity, TrafficLightIntersection, uses structural architecture and
instantiates the component DecodeHex three times and ClockCounter twice.

Alternative Designs
An alternate design for this project is the extent of modularity for the
component, TrafficControl, could be explored further. Another change would be to
make the states on the case statement into numbers, instead of words. Instead of
having one giant file that does all the needed functions to control the intersection,
many small counters and signals could be implemented to help aide with the extent
of the projects modularity.

Design Documentation

HighPriority

COUNTDOWN5Ped

COUNTDOWN5Low

LowPriority

reset

Figure.5. State Machine

Pedestrian

L2Ped

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
ENTITY TrafficLightIntersection IS
PORT (CLOCK_50: IN
std_logic;
KEY :
IN
std_logic_vector(1 downto 0);
SW :
IN
std_logic_vector(0 downto 0);
HEX0 :
OUT std_logic_vector(6 DOWNTO 0);
HEX1 :
OUT std_logic_vector(6 DOWNTO 0);
HEX2 :
OUT std_logic_vector(6 DOWNTO 0);
HEX3 :
OUT std_logic_vector(6 DOWNTO 0);
LEDR :
OUT std_logic_vector(2 DOWNTO 0);
LEDG :
OUT std_logic_vector(2 DOWNTO 0));
END TrafficLightIntersection;
ARCHITECTURE Behavior OF TrafficLightIntersection IS
COMPONENT DecodeHex IS
PORT ( BitInput:
HexOutput:
END COMPONENT DecodeHex;

IN std_logic_vector(3 DOWNTO 0);

OUT std_logic_vector(6 DOWNTO 0));

COMPONENT ClockCounter IS
GENERIC (UpperBound: integer);
PORT (
Clock: IN std_logic;
Enable: OUT std_logic);
END COMPONENT ClockCounter;
component TrafficControl IS
PORT (
EffClock:
IN STD_LOGIC;
Clock :
IN STD_LOGIC;
crosswalktraffic:
IN STD_LOGIC;
lowpriortraffic:
IN STD_LOGIC;
reset :
IN STD_LOGIC;
HIP :
OUT STD_LOGIC;
LOWP :
OUT STD_LOGIC;
PED :
OUT STD_LOGIC;
HiDone :
OUT STD_LOGIC;
LowDone :
OUT STD_LOGIC;
PedDone :
OUT STD_LOGIC;
HiCount :
OUT STD_LOGIC_VECTOR (3 downto 0);
LowCount :
OUT STD_LOGIC_VECTOR (3 downto 0);
PedCount :
OUT STD_LOGIC_VECTOR (3 downto 0));
END component TrafficControl;

COMPONENT Edge_Detect is
Port( Clock:
IN std_logic;
Enable:
IN std_logic;
Input:
IN std_logic;
Output:
OUT std_logic);
END COMPONENT Edge_Detect;
signal
signal
signal
signal
signal
signal
signal

Enable1s :
Enable1ms :
PedXing :
reset :
HiCountsig :
LowCountsig :
PedCountsig :

STD_LOGIC;
STD_LOGIC;
STD_LOGIC;
STD_LOGIC;
STD_LOGIC_VECTOR (3 downto 0);
STD_LOGIC_VECTOR (3 downto 0);
STD_LOGIC_VECTOR (3 downto 0);

begin
PedCross: Edge_Detect port map (Clock => CLOCK_50,
Input => KEY(0),
Enable => Enable1ms,
Output=> PedXing);
Rst: Edge_Detect port map(

Clock => CLOCK_50,

Input => KEY(1),
Enable => Enable1ms,
Output => reset);

OneSec: ClockCounter Generic map (

UpperBound=>49999999)
port map( Clock => CLOCK_50,
Enable => Enable1s);
OneMilliSec: ClockCounter Generic map( UpperBound=>49999)
port map( Clock => CLOCK_50,
Enable => Enable1ms);
ControlIntersect: TrafficControl port map (EffClock => Enable1s,
Clock => CLOCK_50,
crosswalktraffic => PedXing,
lowpriortraffic => SW(0),
reset => reset,
HIP => LEDG(2),
LOWP => LEDG(1),
PED => LEDG(0),
HiDone => LEDR(2),
LowDone => LEDR(1),
PedDone => LEDR(0),
HiCount => HIcountsig,
LowCount => LOWcountsig,
PedCount => PEDcountsig);

Pedestrian: DecodeHex port map(BitInput => PEDcountsig,

HexOutput => HEX0);
LowPriority: DecodeHex port map(BitInput => LOWcountsig,
HexOutput => HEX1);
HighPriority: DecodeHex port map(BitInput => HIcountsig,
HexOutput => HEX2);
HEX3 <= "1111111"; --Always off-end Behavior;
Figure.6. Top Level Entity VHDL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY ClockCounter IS
GENERIC (UpperBound: integer);
PORT (
Clock:
IN std_logic;
Enable:
OUT std_logic);
END ClockCounter;
ARCHITECTURE behavior OF ClockCounter IS
signal count : integer range 0 to(UpperBound-1);
BEGIN
PROCESS (Clock)
BEGIN
IF (rising_edge(Clock)) then
IF(count = (UpperBound-1)) then
count <= 0;
Enable <= '1';
else
count <= count+1;
Enable <= '0';
end if;
end if;
END PROCESS;
END behavior;

Figure.7. Modular Clock Counter Component VHDL Code

library ieee;
use ieee.std_logic_1164.all;
ENTITY DecodeHex IS
PORT(
BitInput:
IN std_logic_vector(3 downto 0);
HexOutput: OUT std_logic_vector(6 downto 0));
END DecodeHex;
ARCHITECTURE Behavior OF DecodeHex IS
BEGIN
WITH BitInput SELECT
HexOutput <=
"1000000" WHEN "0000",
"1111001" WHEN "0001",
"0100100" WHEN "0010",
"0110000" WHEN "0011",
"0011001" WHEN "0100",
"0010010" WHEN "0101",
"0000010" WHEN "0110",
"1111000" WHEN "0111",
"0000000" WHEN "1000",
"0011000" WHEN "1001",
"0001000" WHEN "1010",
"0000011" WHEN "1011",
"1000110" WHEN "1100",
"0100001" WHEN "1101",
"0000110" WHEN "1110",
"0001110" WHEN "1111",
"1111111" WHEN others;
END Behavior;

Figure.8. Modular 7 Segment Display Decoder VHDL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity Edge_Detect is
Port( Clock: IN std_logic;
Input: IN std_logic;
Output: OUT std_logic);
END Edge_Detect;
Architecture structural of Edge_Detect IS
signal Q1:std_logic;
signal Q0:std_logic;
Begin
Process(Clock)
BEGIN
if (rising_edge (Clock)) then
Q0<=not Input;
Q1<=Q0;
Output <= not(Q0) and (Q1);
END IF;
end process;
end structural;

Figure.9. Modular Edge Detection VHDL File

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
Entity TrafficControl is
PORT (EffClock: IN STD_LOGIC;
Clock : IN STD_LOGIC;
crosswalktraffic : IN STD_LOGIC;
lowpriortraffic : IN STD_LOGIC;
reset : IN STD_LOGIC;
HIP : OUT STD_LOGIC;
LOWP : OUT STD_LOGIC;
PED : OUT STD_LOGIC;
HiDone : OUT STD_LOGIC;
LowDone : OUT STD_LOGIC;
PedDone : OUT STD_LOGIC;
HiCount : OUT STD_LOGIC_VECTOR (3 downto 0);
LowCount : OUT STD_LOGIC_VECTOR (3 downto 0);
PedCount : OUT STD_LOGIC_VECTOR (3 downto 0));
end TrafficControl;
architecture Behavioral of TrafficControl is
type State is (HighPriority, LowPriority, Pedestrian, COUNTDOWN5Ped,
COUNTDOWN5Low, L2Ped);
signal CurrentState , NextState : State;
signal countdown9 : std_logic_vector (3 downto 0);
signal countdown4 : std_logic_vector (3 downto 0);
signal countdown5 : std_logic_vector (3 downto 0);
signal resetsig : std_logic;
signal HiEnable : std_logic;
signal LowEnable : std_logic;
signal PedEnable : std_logic;
signal register5 : std_logic;
signal register9 : std_logic;
signal register4 : std_logic;
signal trip5 : std_logic;
signal trip9 : std_logic;
signal trip4 : std_logic;
signal Go2Ped : std_logic;
begin

HiCount <= countdown5;

LowCount <= countdown9;
PedCount <= countdown4;
resetsig <= reset;

Works : process (Go2Ped, reset, CurrentState, countdown4, countdown5,

countdown9, NextState, crosswalktraffic, lowpriortraffic, Clock)
begin
case CurrentState is
when HighPriority =>
NextState <= CurrentState;
HIP <= '1';

LOWP <= '0';

PED <= '0';
HiDone <= '0';
LowDone <= '1';
PedDone <= '1';
HIenable <= '0';
LowEnable <= '0';
PedEnable <= '0';
trip5 <= '1';
trip4 <= '1';
trip9 <= '1';
Go2Ped <= '0';
if crosswalktraffic = '1' then
NextState <= COUNTDOWN5Ped;
elsif lowpriortraffic = '1' then
NextState <= COUNTDOWN5Low;
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when Pedestrian =>
NextState <= CurrentState;
HIP <= '0';
LOWP <= '0';
PED <= '1';
HiDone <= '1';
LowDone <= '1';
PedDone <= '0';
HIenable <= '0';
LowEnable <= '0';
PedEnable <= '1';
trip4 <= '0';
Go2Ped <= '0';
if countdown4 = 0 and lowpriortraffic = '1' then
NextState <= LowPriority;
trip4 <= '1';
elsif countdown4 = 0 and lowpriortraffic = '0' then
NextState <= HighPriority;
trip4 <= '1';
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when LowPriority =>
NextState <= CurrentState;
HIP <= '0';
LOWP <= '1';
PED <= '0';
HiDone <= '1';
LowDone <= '0';

PEDdone <= '1';

HiEnable <= '0';
LowEnable <= '1';
PedEnable <= '0';
trip9 <= '0';
if countdown9 = 0 and Go2Ped = '0' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
elsif countdown9 = 0 and Go2Ped = '1' then
NextState <= L2Ped;
trip4 <='1';
trip5 <='1';
trip9 <='1';
elsif crosswalktraffic = '1' then
Go2Ped <= '1';
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when COUNTDOWN5Ped =>
NextState <= CurrentState;
HIP <= '1';
LOWP <= '0';
PED <= '0';
HiDone <= '0';
LowDone <= '1';
PedDone <= '1';
HiEnable <= '1';
LowEnable <= '0';
PedEnable <= '0';
trip5 <= '0';
Go2Ped <= '0';
if countdown5 = 0 then
NextState <= pedestrian;
trip5 <= '1';
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when COUNTDOWN5low =>
NextState <= CurrentState;
HIP <= '1';
LOWP <= '0';
PED <= '0';
HiDone <= '0';
LowDone <= '1';
PedDone <= '1';
HiEnable <= '1';

LowEnable <= '0';

PedEnable <= '0';
trip5 <= '0';
Go2Ped <= '0';
if countdown5 = 0 then
NextState <= LowPriority;
trip5 <='1';
elsif crosswalktraffic = '1' then
NextState <= COUNTDOWN5Ped;
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when L2Ped =>
NextState <= CurrentState;
HIP <= '1';
LOWP <= '0';
PED <= '0';
HiDone <= '0';
LowDone <= '1';
PedDone <= '1';
HiEnable <= '1';
LowEnable <= '0';
PedEnable <= '0';
trip5<='0';
if countdown5 = 0 then
NextState <= Pedestrian;
trip5 <= '1';
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
end case;

end process;

CountDOWN5Down : process (EffClock, HiEnable, resetsig, countdown5, trip5)

begin
if register5 = '1' or resetsig = '1' then
countdown5 <= "0101";
elsif (RISING_EDGE (EffClock)) and HiEnable = '1' THEN
if countdown5 = 0 then
countdown5 <= "0101";
else
countdown5 <= countdown5 - 1;
end if;
end if;
end process;
count9Down : process (EffClock, LowEnable, resetsig, countdown9, trip9)
begin
if register9 = '1' or resetsig = '1' then

countdown9 <= "1001";

elsif (Rising_Edge(EffClock)) and LowEnable = '1' THEN
if countdown9 = 0 then
countdown9 <= "1001";
else
countdown9 <= countdown9 - 1;
end if;
end if;
end process;
count4Down : process (EffClock, PedEnable, resetsig, countdown4, trip4)
begin
if register4 = '1' or resetsig = '1' then
countdown4 <= "0100";
elsif (rising_edge (EffClock)) and PedEnable = '1' THEN
if countdown4 = 0 then
countdown4 <= "0100";
else
countdown4 <= countdown4 - 1;
end if;
end if;
end process;
PROCESS(Clock)
begin
IF Rising_Edge(Clock) THEN
CurrentState <= NextState;
register5 <= trip5;
register4 <= trip4;
register9 <= trip9;
END IF;
END PROCESS;
end Behavioral;

Figure.10. ControlTraffic VHDL File

Performance Results and Analysis

Figure.11. Flow Summary of Compilation Report

The design implemented based on the specifications was successful. It is a
possibility that the circuit might experience failure due to issues with timing and
metastability from the asynchronous inputs and outputs.