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Performance
Agenda
DDR4
GDDR5
Voltage
1.5 V / 1.35 V
1.2 V
1.5 V / 1.35 V
Strobe
Bi-directional differential
Bi-directional differential
Free-running differential
WRITE clock
Strobe Configuration
Per byte
Per byte
Per word
Strobe based
Strobe based
Data Termination
Address/Command
Termination
Burst Length
VDDQ/2
VDDQ
VDDQ
VDDQ/2
VDDQ/2
VDDQ
BC4, 8
BC4, 8
Bank Grouping
No
No
Configuration
x16, x32
Package
170-ball FBGA
800 2,133
1,600 3,200+
4,000 7,000
Component Density
1 GB 8 GB
512 MB 2 GB
Stacking Options
DDP, QDP
2 GB 16 GB
Up to 8H (128-GB stack);
single load
No
Based on temperature
New DDR4 low-power auto self-refresh (LPASR) capability
Changes refresh rate based on temperature
Package/board
Package / BoardMargin
Margin
Chip Margin
2,500
DDR1
DDR2
DDR3
DDR4
Data Valid
Window
DRAM
Margin
Package/
Board
Margin
Chip
Margin
2,500
938
469
313
900
425
188
125
800
256
140
93
800
256
140
93
938
469
DDR1
400 Mbps
DDR2
DDR3
313
DDR4
3,200 Mbps
10
Vref step
Vref_set_tol
0.50%
0.65%
0.80%
VDDQ
-1.625%
0.00%
1.625%
VDDQ
3, 4, 6
-0.15%
0.00%
0.15%
VDDQ
3, 5, 7
11
+/-2%
DQS
+/-2%
DQ
Timing Parameters by Speed Bin for DDR4-2400 to DDR4-3200
Speed
DDR4-2400
DDR4-2666
DDR4-3200
Units
NOTE
22
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
tCK (DLL_OFF)
tCK (avg)
tCH (avg)
0.48
0.52
0.48
0.52
0.48
0.52
tCK (avg)
tCL (avg)
0.48
0.52
0.48
0.52
0.48
0.52
tCK (avg)
Clock Timing
12
TBD
p-p jitter
f
jTIE (t )
I ( f ) Z ( f ) S ( f ) P ( f ) = J ( f ) iFFT
13
Different timing within a group and between groups (tCCD, tWTR, tRRD)
Long timing: bank-to-bank within a group
Short timing: access to different bank groups
Bank 3
Bank Group 0
Bank 0
Bank 1
Bank 2
Bank 3
Bank Group 1
Bank 0
Bank 1
Bank 2
Bank 3
Short Timings
Long Timings
Bank 2
Bank 3
Bank Group 2
Bank 0
Bank 1
Bank 2
Bank 3
Bank Group 3
Bank 0
Bank 0
Bank 1
Bank 1
Bank Group 1
14
0.5
Margin (ns)
0.4
0.3
External
Effects
Calibration Calibration
Effects
Uncertainty
0.2
0.1
0
-0.1
15
FPGA Effects
No Margin Without
Calibration
What is Calibration?
Capture Calibration (De-skew)
Before de-skew
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
15
30
45
60
DQs
75 90 105 120 135 150 165 180
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQs
0 15 30 45 60 75 90 105 120 135 150 165 180
Resync Calibration
Benefit: Accurate strobe placement
More resync margin
DQ0
DQ1
DQ2
DQ3
*
*
DQ70
DQ71
0 15 30 45 60
VT Compensation
Data shifts
due to VT
variations
Voltage and
temperature
tracking
Benefit: Dynamic phase adjustment to match shifting
data valid window Robust over VT
16
ptap control
DQS
X+90 phase
X phase
DQ OUT1 Delay
DQ OUT2 Delay
DQ out dtap1
control
DQ out dtap2
control
DQ
Calibration knobs
pins
DQS-out1 and DQS-out2 delay : Control the delay applied to outgoing DQS
pins
Write leveling output : Changes the delay on both DQ and DQS relative to
the memory clock-in phase taps
17
vfifo control
X phase
VFIFO
DDIOin
LFIFO
Lfifo control
Calibration knobs
18
DQS
Enable
DQS IN Delay
DQS en dtap
control
DQS En Delay
DQS
DQS in dtap
control
DQ
DQ IN Delay
DQ in dtap
control
Calibration Stages
LFIFO training
19
Write leveling
Post-amble tracking
Start
DQS-enable calibration
Process DPRIO
user command
User mode loop
N
User command
found in RAM?
N
Process RAM
user command
0.5
Margin (ns)
0.4
0.3
External
Effects
Calibration Calibration
Effects
Uncertainty
0.2
0.1
0
-0.1
20
FPGA Effects
No Margin Without
Calibration
21
DDR3 Push-Pull
Overshoot
VDD
VSS
Undershoot
Jitter
Content Courtesy of Micron
23
Overshoot
VIHdc
VIHac
Hi-Ringback
Vref
Lo-Ringback
VILdc
VILac
Undershoot
DDR3
DDR4
Density / Speed
512 Mb ~ 8 GB
1.6 ~ 2.1 Gbps
2 GB ~ 16 GB
1.6 ~ 3.2 Gbps
Voltage
(VDD / VDDQ / VPP)
1.5 V / 1.5 V / NA
(1.35 V / 1.35 V / NA)
VREF
Data I/Os
CMD/ADDR I/Os
CTT
CTT
Strobe
Bi-directional / differential
Bi-directional / differential
Number of banks
16 (4 GB)
1 KB / 1 KB / 2 KB
512 B / 1 KB / 2 KB
Number of prefetch
8 bits
8 bits
Added function
78 / 96 BGA
78 / 96 BGA
DIMM type
R, LR, U, SoDIMM
+ ECC SoDIMM
DIMM pins
Interface
Core
Architect
Physical
25
26
DDR3
SSO
Timing and noise issues generated due to rapid changes in voltage and
Layer changes
VREF noise
ISI
Signal edges jitter due to previous bits energy still on the bus
Minimize ISI
Optimize layout
Terminate nets
Crosstalk
RPDs
When aggressors fire at the same time as victim (e.g. data-to-data coupling)
Victim edge speeds up or slows down, causing jitter
When aggressors do not fire at the same time as victim (e.g. data-to-
command/address coupling)
Minimize crosstalk
Example: 5-mil trace located 5 mils from a reference plane should have a 15-mil gap
Cin mismatch
RTT mismatch
Cap
40
Before calibration
is the out
standard
Calibrating
some
timing
analysis
of the process
Calibrating
to the
variation
in the
FPGA
variations
memory
(deskew
+
pessimism removal)
Errors in the
calibration
algorithm
Effects
of
temperature and
voltage changes on
the calibration
41
ranks
Eye monitor support of data valid window
Loopback support for bit error rate (BER) testing
42
Reports section
Tasks section
Commands run
Shown in console
43
Access same calibration data as the EMIF toolkit, now via FPGA logic
Via Avalon Memory-Mapped (Avalon-MM) interface
44
45
Very unlikely
46
Conclusion
47
Thank You