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Instructions
CSE 410,
410 Spring 2009
Computer Systems
http://www.cs.washington.edu/410
3/31/2009
Other References
See MIPS Run,
Run D Sweetman
section 8.6, Instruction encoding
section 10.2,
10 2 Endianness
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Todays
y Agenda
g
//pick
p a language
g g
A = B + C;
//say, c
Lets convert this to a much more primitive
programming
i language
l
Assume A,B,C are associated with $t0,$t1,$t2
#say,
y, MIPS
A veryy simple
p organization
g
program counter
main
memoryy
registers
functional units
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Instructions in memoryy
...
...
...
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...
...
instruction
addresses
20
16
12
8
4
0
instruction value
instruction value
Fetch/Execute Cycle
y
Operation of a computer:
while (processor not halted) {
fetch instruction at memory location (PC)
PC = PC + 4 (increment to point to next instruction)
execute fetched instruction
}
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unit
it
# bits
bit
byte
half-word
16
word
32
double word
64
Alignment
g
An object
j in memoryy is aligned
g
when its
address is a multiple of its size
Byte: always aligned
Halfword: address is multiple of 2
Word:
W d address
dd
iis multiple
lti l off 4
Double word: address is multiple of 8
Alignment simplifies load/store hardware
And is required
q
by
y MIPS,, but not x86
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System
y
organization
g
so far
instructions
i
t
ti
and
d
data
program counter
increments by 4
main
memory
32-bit
instructions
registers
functional units
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10
MIPS Registers
g
32 bits wide
32 bits is 4 bytes
same as a word in memoryy
signed values from -231 to +231-1
unsigned values from 0 to 232-11
11
Register
g
addresses
32 ggeneral purpose
p p
registers
g
how many bits does it take to identify a
register?
5 bits, because 25 = 32
12
Register
g
numbers and names
number
name
usage
zero
always
l
returns 0
at
2-3
v0, v1
4-7
a0-a3
8-15, 24, 25
t0-t9
16-23
s0-s7
26,27
k0, k1
28
gp
global pointer
29
sp
stack pointer
30
fp or s8
frame pointer
31
ra
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13
For example
add $t1, $a0, $t0
add a0 and t0 and put result in t1
add $t1,$zero,$a0
move contents of a0 to t1 (t1 = 0 + a0)
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14
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15
R-format fields
op code
d
6 bits
source 1 source 2
5 bits
5 bits
d t
dest
shamt
h t
f
function
ti
5 bits
5 bits
6 bits
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16
17
System
y
organization
g
again
g
instructions
i
t
ti
and
d
data
program counter
increments by 4
main
memory
32-bit
instructions
registers 32
32
bits wide
in number
functional units
implement
p
instructions
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18
rt,
rt,
rt,
rt,
rt,
address
address
address
dd
address
address
19
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sw
rt, address
half word: sh
rt, address
byte:
rt, address
sb
20
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$t0,0($s0)
$t0
0($s0)
$t0,$t0,$t1
$ , ($ )
$t0,0($s0)
21
I-format fields
op
p code
6 bits
base reg
g src/dest
5 bits
5 bits
Th
The contents off the
h base
b
register
i
andd the
h
offset value are added together to generate
th address
the
dd
for
f the
th memory reference
f
Can also use the 16 bits to specify an
immediate value, rather than an address
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22
program counter
increments by 4
main
memoryy
instructions
and data
registers 32
32
bits wide
in number
functional units
implement instructions
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23
The eye
y of the beholder
Bit p
patterns have no inherent meaning
g
A 32-bit word can be seen as
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24
Big-endian,
g
, little-endian
A 32-bit word in memory
y is 4 bytes
y longg
But which byte is which address?
Consider the 32-bit
32 bit number 0x01234567
four bytes: 01, 23, 45, 67
mostt significant
i ifi t bits
bit are 0x01
0 01
least significant bits are 0x67
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25
...
...
...
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...
...
12
8
4
0
01
23
45
67
byte # contents
7
6
5
4
67
45
23
01
b t offsets
byte
ff t
26
...
...
...
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...
...
12
8
4
0
01
23
45
67
byte # contents
7
6
5
4
01
23
45
67
b t offsets
byte
ff t
27