EL 512

VLSI Subsystem Design

Instructor:
Mazad S. Zaveri
Faculty Block 4, Room 4206
Email: mazad_zaveri@daiict.ac.in
http://intranet.daiict.ac.in/~mazad_zaveri/

Capacitance
For an isolated wire
Capacitance due to the parallel plates bottom of wire with the
substrate
Fringing capacitance arising from fringing fields along all the
edges of the conductor with finite thickness
Fringe = border or periphery

For a non-isolated wire, i.e. wire that has adjacent wires

Parallel plate capacitance bottom with substrate
Fringing capacitance with the substrate
Parallel plate capacitance side with the side of the other wire
And some fringing capacitance between the two wire
edges/surfaces

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How to calculate the values of these capacitances ?

Parallel plate capacitances

C = ox A/d
With appropriate interpretation of area A and d

Between wire-bottom and substrate

Between wire-side and other wires side

Fringing capacitance with substrate

See next slide

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Fringing capacitance
Two formulas proposed by some authors
Includes both the fringing capacitance and the bottom-parallel
plate capacitance
Obviously, these formulae do not account for the capacitances
with neighbors above or on the sides.
[Yuan et al.]

[Meijs et al.]
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Upper Bound and Lower Bound for a wire capacitance

Upper Bound:
Assume that the layers above and below the conductor of interest are solid ground
planes
Assume, the layers above and below, are not switching, hence, can be modeled as ground
planes

Assume, that the capacitance to neighbors, other than the most adjacent ones, is
negligible
Note: Table 4.8 (on the next slide) gives the upper bound

Lower Bound:
Assume that there are no conductors in the system except the substrate
Note: Table 4.9 does not provide lower bound, because it assumes adjacent wires (on the
same layer) to be present. Hence, Table 4.9 is for a condition between upper bound and
lower bound.
To calculate lower bound, we can use equations on the previous slide (or we can neglect
Cadj from Table 4.9)
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Capacitance table

Capacitance to neighbors accounts for more than 50% of total capacitance

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Capacitance table

Overall capacitance is slightly smaller, because there is no layer above

But, the Cadj is slightly higher, because the fringing fields now terminate on the neighbors

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 In practice, the layers above and below

the conductor of interest are neither solid
planes nor totally empty
The density of the metal on each level will be
dependent on the layout/implementation of
the overall circuit functionality/connectivity

Delay

Wires have distributed resistance and capacitance along its length

Wires can be approximated by lumped elements
L-model
-model
T-model

-model is generally used to model long wires, and at least 3 to 4

segments are generally considered

Because both wire resistance and capacitance increase with length,

wire RC-delay grows quadratically with length
Some ways to reduce delay
Thicker and wider wires, low resistance materials/metals,
Low di-electric materials between conductors

Polysilicon and diffusion

based wires (also called
runners) have very high
resistance, even when
silicided.
Do not use diffusion as wire.
Use polysilicon sparingly,
usually in latches and FF
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Crosstalk
Crosstalk phenomenon
When a wire A switches, it tends to bring its neighbor B along
with it, due to capacitive coupling
Crosstalk effect is dependent on the direction of switching of A and
switching of B

Crosstalk leads to undesirable effects in terms of

Delay
Noise

Crosstalk depends on the ratio of Cadj to the total

capacitance. The total capacitance may include the load
capacitance (if there is any)
For short wires, with large loads, crosstalk is unimportant
For long wires, crosstalk is important

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Crosstalk Delay Effects

When two adjacent wires A and B switch (creating V),
the direction of switching affects the amount of charge
that must be delivered (Q=Cadj V), and the delay of
switching (Ceff)
Delay will be the worst case, when A and B switch in
opposite directions (V=2VDD)
Coupling capacitor effectively becomes twice as large (2Cadj)
(Miller Coupling effect/factor = 2)

Delay will be least, when A and B switch in same

direction (V=0)
Coupling capacitor effectively absent (Cadj=0)

(A is switching)

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Crosstalk Noise Effects

Wire A switches, while wire B is supposed to remain constant

But A will try to switch B partially, creating noise on B

Modeled as Aggressor and Victim network

Condition: Victim is floating (not-driven)
Capacitive voltage divider to compute victim noise

Condition: Victim is actively driven

Victims driver will supply current to oppose and reduce the victim noise, induced
by the aggressor
Drivers are modeled with resistors

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Crosstalk Noise (Victim is undriven/driven)

Waveform shows
Step signal on the aggressor wire
Coupled noise-signal on the victim wire
Victim is driven with inverters of different inverter gate-size (current driving capacity)

When victim is not driven (i.e. floating) noise remains indefinitely

When victim is driven, the victims driver opposes the transition, and restores the
victims voltage level

Depending on the
wires voltage,
Aggressor (driver)
transistor will be in
LIN/SAT, and victim
transistor will be in
LIN/SAT
Accordingly, that will
affect Raggressor and
Rvictim

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