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Capacitance
For an isolated wire
Capacitance due to the parallel plates bottom of wire with the
substrate
Fringing capacitance arising from fringing fields along all the
edges of the conductor with finite thickness
Fringe = border or periphery
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Fringing capacitance
Two formulas proposed by some authors
Includes both the fringing capacitance and the bottom-parallel
plate capacitance
Obviously, these formulae do not account for the capacitances
with neighbors above or on the sides.
[Yuan et al.]
[Meijs et al.]
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Upper Bound:
Assume that the layers above and below the conductor of interest are solid ground
planes
Assume, the layers above and below, are not switching, hence, can be modeled as ground
planes
Assume, that the capacitance to neighbors, other than the most adjacent ones, is
negligible
Note: Table 4.8 (on the next slide) gives the upper bound
Lower Bound:
Assume that there are no conductors in the system except the substrate
Note: Table 4.9 does not provide lower bound, because it assumes adjacent wires (on the
same layer) to be present. Hence, Table 4.9 is for a condition between upper bound and
lower bound.
To calculate lower bound, we can use equations on the previous slide (or we can neglect
Cadj from Table 4.9)
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Capacitance table
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Capacitance table
But, the Cadj is slightly higher, because the fringing fields now terminate on the neighbors
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Delay
Crosstalk
Crosstalk phenomenon
When a wire A switches, it tends to bring its neighbor B along
with it, due to capacitive coupling
Crosstalk effect is dependent on the direction of switching of A and
switching of B
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(A is switching)
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Waveform shows
Step signal on the aggressor wire
Coupled noise-signal on the victim wire
Victim is driven with inverters of different inverter gate-size (current driving capacity)
Depending on the
wires voltage,
Aggressor (driver)
transistor will be in
LIN/SAT, and victim
transistor will be in
LIN/SAT
Accordingly, that will
affect Raggressor and
Rvictim
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