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Packaging of two-dimensional smart pixel arrays

D.N. Kabal, G.C. Boisset, D.R. Rolston and D.V. Plant
McGill University
Dept. of Electrical Engineering
3480 University St., Montreal, Quebec, Canada, H3A 2A7
Introduction

Chip-on-board packaging

The optomechanical and electronic packaging of twodimensional smart pixel arrays present a series of constraints that complicate the application of standard electrical packaging approaches in system applications.
Through the construction of demonstrator systems, we
have designed, fabricated, and implemented smart pixel
packaging which uniquely addresses the critical issues
associated with successfully integrating two-dimensional optoelectronic device arrays into systems. In order
to take full advantage of this class of optoelectronics,
aggressive packaging solutions which use both existing
and new microelectronic packaging technologies have
been employed. Key system design considerations such
as electrical bandwidth and connectivity, thermal management, and optical alignability have played a role in
the choice of packaging solution. In this paper, we will
describe smart pixel packaging designed, modelled, fabricated and demonstrated for board-to-board optical
interconnect applications.

In the system demonstrator to be completed by the

McGill Photonic Systems Group, a four-stage HybridCMOS modulator-based free-space optical link is the
objective [3].

Standard packaging techniques

A standard approach to electronic packaging of a smart
pixel array could include the use of a chip carrier
mounted on a printed circuit board that is interfaced to
support electronics. This chip carrier can be either a
through-hole carrier or a surface mount device (SMD)
carrier.

Through-hole carriers include pin grid arrays (PGAs)and

dual in-line packages (DIPS).These are flexible and
reusable carriers that are socketable, thus allowing for
testability and modularity.

To accomplish the packaging task, the following packaging hierarchy and constraints were proposed:
1. The Hybrid-CMOS smart pixel arrays should reside
on a small daughterboard to prevent interference
with the rest of the optomechanics. The small
daughterboard should preserve the system's bandwidth and be highly maneuverable for optical alignment. The chip's mount should be low profile so as
not to interfere with closely-spaced lenslet arrays.
2. Ths daughterboard should be connected to the next
level of hierarchy by a high-speed connector that
provides a large number of 1/0 pins and can
mechanically isolate the daughterboard from other
electrical components.
3. A motherboard should hold the support electronics
for the smart pixel, as well as connectivity to the outside world and any application-specific electronics.
The resulting daughterboard (Fig. 1) follows an impedance controlled microstrip design with 4 layers of copper interspersed with FR-4. The two inner layers are
planes of copper to support ground and power, while
the outer layers contain traces for signal interconnec-

Figure 1 : Daughterboardl

The SMDs include leaded chip carriers, leadless c h p

carriers, ball-grid arrays, land grid arrays and quad flat
packs. These are all fast carriers with relatively high 1/0
connectivity (for example, a BGA or LGA package could
support up to 600 I/O at 3-5 GHz [ 11).
For smart-pixel arrays, however, an alternate approach
may be attempted, such that the use of an explicit chipcarrier in the system becomes unnecessary or impossible. When the optical system has 1/0 counts and volume
constraints that prohibit the use of standard packages,
the smart pixel array may be mounted directly on the
boarcl, employing the alternative approach of chip-onboard or MCM-L mounting [2].

H
1 cm

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Figure 2 : Chip-on-board mounting

Figure 3:

Die (GaAs,Si)
Finger (Au on Cu]
Printed circuit
board (FR-4)
Wire-bond (Al.Au)

Central ground pad (Au on Cu)

printed circuit

CMOS-SEED
die (si-fl)

Future packaging

Finger (Au on Cu)

I

I
Peltier cooler

Heat sink (Al)

tion. By fixing the thickness of the dielectric (FR-4)

bemreen signal and ground planes, as well as the thickness of the outer signal traces and their width, we have
designed a microstrip transmission line with a nominal
characteristic impedance of 50 0.

A prototype of the daughterboard was fabricated to verify the system design, and the measured -3 dB bandwidth was found to be greater than 1.5 GHz. In addition
to providing a first and second level package for the
chip, this daughterboard supports a single high-speed
AMP'" microstrip connector for connection to the motherboard via a flexible, impedance-controlled (50!2) ribbon. In this way, optical alignment of the photonic
interconnect fabric is decoupled from the support electronics, while a reasonably high number of interconnects (40) is maintained at a bandwidth of more than 1
GHz per connection [4].
Due to space and connectivity constraints imposed by
our optical design, we found it impossible to exploit any
of the standard chip carriers described previously. With
this in mind we chose to mount the Hybrid-CMOS chip
directly on the daughterboard using a MCM-L arrangement (chip-on-board) [2].
The daughterboard provides for chip-on-board mounting with a central, round die-attachment pad surrounded by 44 bond fingers. All exposed copper is
plated with immersion gold to allow for direct wirebonding.

One of the constraints imposed by the system was the

positional tolerance of the chip. With this in mind, we
have devised an alignment, bonding and gluing rig
("puck") for the chip attachment to daughterboard [5].
The daughterboard is first attached to the circular aluminum "puck" by means of mounting screws. A TeflonrM
spacer is then located on the daughterboard by means
of two mounting rods. This L-shaped spacer is designed
to provide a stop to chip-travel during placement of the
chip die, thereby providing an effective alignment
mechanism. The entire "puck can be moved to a heating unit to set the epoxy and then wirebonded on a
height-adjustable, stable base. The anticipated die to
daughterboard positional accuracy will be k 100 pn.

Discussion
The packaging used in this system can be expanded and
improved upon to suit future application needs. We have
addressed many of the issues and concerns facing a
system designer when confronted with the task of packaging a two-dimensional array of smart pixels, but others still require attention. For example, thermal
management is a key system parameter which must be
aJdressed in order to build and package large smart
pixel arrays for system applications. Figure 3 shows the
schematic of a package incorporating chip-on-board
technology and cooling via both a passive heat-sink and
a Peltier cooler. This, or other similar solutions will be
required in future system applications.

References
[l] M.R. Otazo, M.Eng. Thesis, McGill University, 1995.

[2] R.R. Johnson, IEEE Spectrum, March 1990, pp34-36,

46, 48.
[3] A.L. Lentine, K.W.Goosen, J.A. Walker, L.M.F. Chirovsky, et al, IEEE Photonics TechnologyLetters, Feb.
1996, V01.8, NO. 2, ~ ~ 2 2 1 - 2 2 3 .
[4] AMPTMproduct literature, microstrip connectors.
[5] D.N. Kabal, D.R. Rolston, McGill CMOS-SEED Phase II
Chip-On-Board Assembly Procedure, McGill Photonic Systems Group internal document, Mar. 1996.

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