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[11]
[45]
Irabu
[54]
1211
[22]
[30]
4,513,286
[75] Inventor:
[73]
Patent Number:
Date of Patent:
[57]
ABSTRACT
[52]
[58]
[56]
References Cited
U.S. PATENT DOCUMENTS
4,031,364
6/1977
3/1982
343/5 CF X
OTHER PUBLICATIONS
RADAR SlGNAL
A/D
selected value of K.
VARIABLE
CONVERTING
SECTION
..
CLK
6' -
SETTING
40~ UNIT
CFAR
SETTING
UNlT
\ 50
Sheetl ofS
4,513,286
FIG.|
10W
RADAR SIGNAL
201
MD
(30
CVOANRVIEAFEJTLIENG
SECTION
UAR
TARGETDETECTIONSIGNAL
CLK
G-
smme
smme
40~ UNIT
3n
WG- LOG
mm \50
312
F12
-N+l -- 2~2~4
CLK v
m3j
L |/2N
3x4!
315
sum.
FIG.4
31s
ANTILOG. /
Th-
fm50-""sEm
UNIT
Th
/37
come
3|8
_> LOG
fm 50 K
226
fm40 U
VD" [I
SheetZofS
4,513,286
Sheet4of5
4,513,286
FIGS
VurIZI/gZ
H06
SheetS 0f5
4,513,286
4,513,286
(CFAR) PROCESSOR
PR(X)=(ZX/0'2)-e>tp {_X1/<T2}
BACKGROUND OF THE INVENTION
(3)
ability.
Among known techniques for removing undesirable
signals other than target signals in a radar system, a
Z= ~10g [1 MX)l
(4)
output of the logarithmic converter, subtracting the 35 value and the false alarm rate in CFAR processing
Weibull clutter, it is known that the false alarm rate for
resulting average from a signal of interest, and subject
ing the difference to an antilogarithmic conversion.
This originates from the fact that not all the clutters
the Weibull function except for limited cases. This was 45 on p. 825, and the aforementioned paper Radar Detec
Pw(X)=(K/r)(X/<r)K_ up {-(X/<T)K}
(1)
55
4,513,286
follows.
ing the false alarm rate and surely detecting even target
25
tion.
In accordance with the present invention, a radar
dFAX)
11X
stant 0', not only lowers the false alarm rate to a signi?
(10)
(IX
(l2)
55
4,513,286
d)
(19)
(14)
mm =5-(l
ily selected.
Comparing equation (16) with equation (19), it is now
We) pl-e121
(20)
Y=(X/v)'1/2
given by
(21)
(17)
Wat) aft-rt]
45
obtain
lFX(X)=exp [(X/v)"l]
(18)
65
4,513,286
<X2> _ <X>; :
J?
(26)
According, K is given by
K' = __._______l L
(27)
W W
From equation (24),
ln 0'' = <X>
(28)
(30) '
which is given by
is expressed as
(22)
(31)
40
eXdX=dy
(32)
45
Accordingly,
(23)
F(Iny): of
lny
1
_
(33)
_(e (a-Zr) )d
_
(34)
are expressed as
F(X) : l - exp(
Thus,
4,513,286
9
A.
(36)
1- FtXi=exp(-%)
Turning back to FIG. 2, the Weibull clutter signal V
is processed by a known logarithmic converter 211 into
a signal X and then coupled to an averaging circuit 212.
The averaging circuit 212 comprises a known shift reg
ister 2120 having a predetermined number of shift stages
(in this embodiment, (2N+ 1) stages where N is a natu
10
the conversion.
Referring to FIG. 3, there is shown a detailed block
diagram of the variable converting section 20 for Log
Normal clutter.
As is well known in the art, the signal amplitude V of
(37)
1
f(V) = --exp
In ( V
21w V l: 2B1 { M
<X> prepared by a square calculator 214 and the 40 in order to enlarge the available dynamic range and
square average <X2>. The difference is supplied to a
simplify the construction for the variable conversion, as
K extractor 218. The K extractor 218 calculates K
has been discussed in conjunction with the embodiment
from the output <X2> <X>2 of the subtractor 217
of FIG. 2.
'y/K'.
A subtractor 213 subtracts the 'y/ K from the average
<X> to produce an output <X> 'y/K as is shown
in equation (28). This substractor output is applied to an
(39)
(40)
X lnM
[3
erf(y) =
J 217'
y e M";
Of
(41)
dX
11
1
4,513,286
12
(42)
ln M = N [21 X,
(43)
B =
10
(X-ln M).
55
(44)
W=Z <Z>
(45)
(46)
output
13
4,513,286
14
(Eulers constant).
In equation (47), the variance Var(N) depends on the
parameter K selected, but it will remain constant re
_ 0.5772
)K
K
(49)
0.5772
K
(50)
15
4,513,286
16
said K signal,
averaging means,
20
averaging means,
second square means for squaring an output of said
time,
?rst square means for squaring an output of said ?rst
averaging means,
second square means for squaring an output of said
time,
second subtractor means for subtracting an output of
said ?rst square means from an output of said sec
17
4,513,286
18
means,
subtractor means,
means.
and
9. An adaptive CFAR processor as claimed in claim
multiplier means for multiplying an output of said
8, in which said averaging means comprises a shift regis
power means by said signal from said cr setting
ter which receives an output of said logarithmic conver
unit.
sion means and has a predetermined number (2N+ l) of
7. An adaptive CFAR processor as claimed in claim 20 shift stages including a central stage, where N is a natu
6, in which said third subtractor means comprises an
ral number, an adder for summing signals stored in a
adder for adding a numerical value of 0.5 to an output of
plurality of stages of said shift register other than said
said error function generator means, and a subtractor
central stage, and a divider for dividing an output of
for subtracting an output of said adder from a signal
said adder by 2N, said subtractor receiving a signal
which indicates a numerical value of 1.0.
25 from said central stage of said shift register as said sec
8. An adapative CFAR processor as claimed in claim
ond input thereof.
*
*
*
it
*
1, in which said CFAR processing means includes:
35
45
50
55
60
65
CERTIFICATE OF CORRECTION
4,513,286
PATENT NO.
DATED
It is certified that error appears in the above-identified patent and that said Letters Patent is hereby
corrected as shown below:
Column 10, line 68, delete the "." and insert --by.
D a y of October I 985
[SEAL]
Arresr:
DONALD J. QUIGG
Arresring Officer
Trademarks-burglar:
CERTIFICATE OF CORRECTION
PATENTNOYP 1
4'5l3'286
DATED
;_
INVENTO HIS)? =
Takeru IRABU
It is certi?ed that error appears in the above-identified patent and that said Letters Patent is hereby
corrected asshown below:
Column 10, line 68, delete the "." and insert --by--.
Column 11, lines 11 and 12, delete "in practicible";
line 21, insert -of-- before "the";
D a y of October 1985
[SEAL]
Arrest:
DONALD J. QUIGG
Arresting Of?cer