A novel supply-independent biasing scheme for

use in CMOS voltage reference

Luis Toledo, Carlos Dualibe, Pablo Petrashin, and Walter Lancioni
Laboratorio de Microelectrnica, Facultad de Ingeniera, Universidad Catlica de Crdoba, Argentina

Abstract Two new supply-independent bias circuits, which

take advantage of the temperature dependence of NMOS and
PMOS threshold voltages to form a CMOS voltage reference,
are presented. Due to the circuit architecture the mobility
factor is completely cancelled. They do not use resistors and all
transistors works in strong inversion. The circuit is simple,
opamp-less and can be implemented in a standard CMOS
process. The supply voltage sensitivity is 6 mV/V from a 3V
supply and the PSRR without any filtering capacitor at 1 KHz
are -65dB for the PMOS circuit and -41dB for the NMOS
circuit.
Index TermsSupply independent biasing, supply voltage
sensitivity, temperature dependence, threshold voltage based
reference.

I. INTRODUCTION

references find applications in a variety of

circuits and systems including linear and switching
regulators, Analog to Digital (A/D) and Digital to
Analog (D/A) converters, voltage to frequency converters,
power supply supervisory circuits, power converters and
other circuits requiring an accurate reference voltage. An
ideal voltage reference must be, inherently, well-defined and
its output voltage should be independent of temperature,
power supply variations, load variations and other operating
conditions [1].
Mixed-signals CMOS integrated circuits for future
portable systems will have to operate down to supply
voltage just exceeding the MOS threshold voltage.
The most popular voltage reference, i.e., the bandgap
voltage reference is bipolar in nature and when the supply
voltage is below the bandgap voltage, i.e., about 1.2V, a
conventional bandgap reference does not operate well [2],
[3]. Therefore IC designers are challenged with designing
circuits that can be implemented in low cost CMOS
technology and with performance comparable to the
performance of the bandgap voltage references.
In addition, high-frequency supply interference, generally
present in digital systems, has to be rejected to enable
quality analog functions to be realized.
OLTAGE

II. BASIC CONCEPTS

A. Theory review
A reference voltage is generated by adding two voltages
that have temperature coefficients of opposite sign, or by
Manuscript received April 13, 2005. This work was supported by
Secretara de Investigacin y posgrado, Universidad Catlica de Crdoba
and in part by the SeCyT under Grant BID 1201/OC-AR PAV 2003-076-0.
e-mail: {toledo, dualibe, petra, lancioni} @uccor.edu.ar.

subtracting two voltages that have temperature coefficients

of same sign, using in both cases suitable multiplication
constants. The resulting voltage is independent of
temperature.
To successfully design a CMOS current/voltage
reference, one must have a thorough understanding of the
temperature behavior of MOS transistors.
The threshold voltage and the mobility are the main
temperature-dependent parameters. As the temperature
increases, both the threshold voltage and the mobility
decrease. But the decrease of VTH and the decrease of have
opposite effects on the drain current; a lower threshold
voltage tends to increase the drain current, but a lower
mobility tends to decrease it. It has been shown in [4] that
the threshold voltage decreases approximately linearly with
an increase in temperature. The temperature dependency of
the threshold voltage usually used is:

VTH (T ) = VTH (T 0) VT (T T 0) ,

(1)

where VT is the temperature coefficient of the threshold

voltage. The value of VT varies from 1mV/C to 4mV/C, it
is technology dependent and differs from a NMOS to a
PMOS transistor.
On the other hand, a general expression which is used to
describe the temperature dependency of the mobility is
given by:

T
(T ) = (T0 )
T0

m
,

(2)

where (T0) is the mobility at the reference temperature,

T0 , and 1 m 2.5.
Since mobility is a nonlinear function of temperature, it
is difficult to build voltage references that rely on MOS
characteristics [5]. Nevertheless, the mobility factor can be
totally cancelled if transistors NMOS are not combined with
the PMOS in a same branch.
In this design, following the criterion mentioned above,
voltages proportional to the threshold voltage of both a
PMOS and a NMOS device, thus linearly dependent on the
temperature, are generated and then subtracted to yield the
voltage reference.
B. Proposed voltage reference principle
The first step to realize a voltage reference is to find a
stable voltage unit, such as the bandgap voltage used in the
so-called voltage references. A typical parameter in CMOS
process is the threshold voltage. However, as it was
discussed in section A, the threshold voltage is temperature

V
VP

K1

VREF

a) Supply-independent
threshold-referenced
PMOS voltage relative
to VDD.

VN

c)Scaled supply-independent
threshold-referenced PMOS
voltage relative
to Ground.
T10

T2 T4

K2

V4

V5

V6

K1VTHP

T1 T3

T9

Fig. 1- Voltage reference concept.

dependent and cannot be used as a reference over a wide
temperature range.
A subtraction of two threshold voltages may result in the
cancellation of temperature-sensitive parameters of the
threshold voltages. Therefore, threshold-voltage subtraction
can be used for the design of CMOS voltage reference.
The principle of the circuit relies on two independent
groups of NMOS and PMOS transistors generating two
voltages VN and VP. By canceling the negative temperature
dependence of one group of transistors with the also
negative temperature dependence of the other group of
transistors (by subtraction of the voltages delivered by each
group), a fixed DC voltage which doesnt change with the
temperature is generated.
For example, for the two threshold voltages VTHP and
VTHN that vary in the same direction with temperature (but
different in magnitude), we choose k1 and k2 so as to
accomplish:
VTHN
V
k1 THP k 2
= 0
(3)
T
T
In this way, a reference voltage is given by:
VREF = k1VTHP k 2VTHN
(4)
This concept is illustrated in Fig. 1 [6]. Fig. 2 shows the
proposed bias circuit schematic embedded in the block
diagram of the voltage reference.
III. CIRCUIT IMPLEMENTATION
A. Architecture and Operation
The proposed bias circuit showed in Fig. 2.a generates a
supply-independent threshold-referenced PMOS voltage
relative to VDD. It is the dual circuit (replacing NMOS by
PMOS) of the circuit shown in Fig. 2.b, which generates a
supply-independent threshold-referenced NMOS voltage
relative to ground.
To provide a qualitative understanding of the circuit
behavior, the circuit can be analyzed using a simple squarelaw MOS model. The circuit of Fig. 2.b operates as follows;
transistors T6, T7 and T8 are saturated and T5 works in the
triode region. The effect of supply-voltage variations is
twofold. Suppose VDD increases. First, since the currents of
T5 and T6 are the same, the gate-source voltage of T5 will
increase proportional to the increase in VDD. Therefore the
voltage V2 will also increase proportionally. Secondly, the
gate-source voltage of T7 increases with VDD due to its gate
is connected to V2. Therefore, despite the body effect, its
drain current will increase proportionally with the increase
in VDD. The circuit is designed so that the required increase

VREF

T6

T8

V2

V3
T5

K2VTHN
T7

b) Supply-independent
threshold-referenced
NMOS voltage relative
to Ground.

d) Voltage
subtractor.

Fig. 2- Bias circuit schematic.

in current through T7 is provided by the increase in T8s
current. As a result V3 will remain constant with changing
VDD.
It can be demonstrated that, without consider body effect,
the voltages V2 is:

V2 = (VDD VTHN ) 1

with 3 =

(W L )5
(W L )6
1

4 =
1

1 + 3

(5)

. If the condition

is fulfilled, with 4 =

(W L )7
, then
(W L )8

1 + 3

V3 = 4 VTHN .

(6)

As expected, the voltage V3 is independent of the supply

voltage but still a linear function of temperature.
A similar analysis can be applied for the behavioral
description of the dual circuit of the Fig 2.a. It operates as
follows; transistors T2, T3 and T4 are saturated and T1 works
in the triode region. The effect of supply-voltage variations
is twofold. Suppose VDD increases. First, since the currents
of T1 and T2 are the same, the gate-source voltage of T2 will
increase proportional to the increase in VDD. Therefore the
voltage V4 will also increase proportionally. Secondly, the

gate-source voltage of T4 increases with VDD due to its gate

is connected to V4. Therefore, its drain current will increase
proportionally with the increase in VDD. The circuit is
designed so that the required increase in current through T4
is provided by the increase in T3s current due to the
increase of V5. The result is that VDDV5 will remain
constant with changing VDD. It can be demonstrated that, the
voltage V4 is:

V4 =

VDD
1 + 1

with 1 =

+ VTHP 1

,
1 + 1
1

(7)

(W L )1
. If the condition
(W L )2

= 2

1 + 1

VTHP

V 5 = VDD

(8)

10

2
W (V6 VTHP )

2
L 9

P c0 X

From (9), V6 is derived as:

V6 =

+ 5VTHP VTHP

(W L )9
(W L )10

where 5 =

V6 =

VTHP

VTHP + GVO3 min V5 V4 + VTHP

(12)

in order to T4 and T3 remains saturated. GVO3 is the gate

voltage overdrive of T3. Thus, the minimum supply voltage
is given by:

VDD min = 2VTHP + 2GVOmin .

(13)
A sub-1-V supply operation can be achieved only with
low-threshold-voltage devices.

The circuit shown in Fig. 2 was designed for realization

in 1.5 m AMI Technology using the BSIM3v.3 MOS
model. The dimensions of transistors used for simulation are
indicated in table 1. Long-channel devices are chosen in
order to minimize channel-length modulation effect.

In Fig. 2.c a translator is employed in order to change the

voltage relative to VDD by another relative to ground. The
same circuit allows adding a scale factor to the input
voltage. Since the currents of T9 and T10 are the same, we
can write:
2

VTHP
V DD V DD +
VTHP

2
W
=
P c0 X
(9)
2
L

VTHP

B. Minimum Supply Voltage

The above analysis is based on the following assumption:

IV. SIMULATION RESULTS

(W L )3
is fulfilled, with 2 =
, then
(W L )4

transresistance that cancels the nonlinearity in i and provides

the required gain M.

Transistors
T1
T2,T6,T8,T9
T3
T4
T5
T7
T10

Size [M/M]
98/12
12/12
20.5/12
36/12
4/12
48/12
28/12

Table 1. Device sizes.

The PSRR for a 3V supply voltage, without using a
filtering capacitor to improve the high-frequency behavior,
is shown in Fig. 3.
Fig. 4 shows a DC sweep analysis in which a flat region
between 2.5V and 3.5V can be observed, which is ideal to
be used in the design of the reference.
With a power supply of 3V, the circuitry generating VP
and VN dissipates 0.301mW at room temperature (power
consumption of the subtractor circuit is not included).
V. CONCLUSION

(10)

. If 5=1, then

(11)

The last block (Fig 2.d) is a voltage subtractor. It can be

implemented by means of the concept of the inverse
function technique as it was used by Buck et al. in [7]. The
main idea in the inverse function technique is to apply a pair
of functions f and f -1S to VTH so that f -1S [f (VTH)] = M
(VTH). In electrical terms, f might be a transconductance
(possibly nonlinear) that maps VTH to some current i.
Then f -1S, which is a scaled version of f -1, should be a

A novel supply- independent bias circuit was presented.

A startup circuit commonly present in other configurations
is not necessary. In standard digital CMOS technologies,
models for the resistors may not be available or reliable. For
this reason it is advantageous to avoid them. The proposed
circuit does not use resistors.
This reference is suitable for standard low-cost CMOS
technologies since additional fabrication steps are not
needed.
The devices operate in strong inversion, for which
accurate device models are usually available, simplifying
the design procedure, especially in digital CMOS
technologies.
Mobility compensation is not necessary. Since the NMOS
transistors are not combined in the same branch with PMOS
transistors the mobility factor is completely cancelled.

REFERENCES
[1]
[2]

[3]

[4]

[5]

[6]

[7]

Behzad Razavi, Design of Analog CMOS Integrated Circuits,

McGraw-Hill Higher Education, chap. 11, 2000.
Laleh Najafizadeh, and Igor M. Filanovsky, Towards a sub-1V
CMOS voltage reference, IEEE ISCAS 2004, Canada, pp. I-53 I56, May 2004.
J. Doyle, Young Jun Lee, Yong-Bin Kim, H. Wilsch, and F.
Lombardi, A CMOS subbandgap reference circuit with 1-V power
supply voltage, IEEE Journal of solid-state circuits, vol. 39, no. 1,
pp. 252-255, January 2004.
I.M. Filanovsky, and A. Allam, Mutual compensation of mobility
and threshold voltage temperature effects with application in CMOS
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pp. 876-883, July 2001.
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based on weighted VGS for CMOS low-dropout linear regulators,
IEEE Journal of solid-state circuits, vol. 38, no. 1, pp. 146-150,
January 2003.
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2002.

.
0

-40

-80
1.0Hz
10Hz
DB(V(6)/V(1))

100Hz
1.0KHz
DB(V(3)/V(1))

10KHz

100KHz

1.0MHz

10MHz

100MHz

Frequency

Fig.3. Simulated PSRR of the proposed supply-independent bias circuit.

1.5V

1.0V

0.5V

0V
0V
V(3)

0.5V
V(6)

1.0V

1.5V

2.0V

2.5V

3.0V

3.5V

4.0V

V1

Fig.4. DC sweep for the proposed supply-independent bias circuits.

4.5V

5.0V