FPGA

200510501136
05 1

FSK

FSK
FPGA FSK ;,
,(m
) ALTERA Quartus Cyclone
FPGA
,
FSKFPGAVHDL

Design of Full Digital FSK Modem Based on

FPGA
To design a FSK modem based on FPGA adopting the method
of hiberarchy and module on the grounds of the principle of digital
signal FSK modulation and demodulation;at the same time design
pseudo-random sequence module corresponding with the system
performance.The whole design is implemented on FPGA based on
the development platform of ALTERA Quartus .The designed modem has
the characteristics of small size,low consume,high integration,strong soft replant and
high anti-interference,it is accordance with the direction of future communication
technology design.

Keyword

sequence;frequencyider;VHDL

II

FSK;FPGA;pseudo-random

.....................................................................................................................................................I
Design of Full Digital FSK Modem Based on FPGA........................................................................II
1 ..................................................................................................................................................1
1.1 EDA ......................................................................................................................1
1.2 EDA ..........................................................................................................1
1.2.1 CAD ..............................................................................................1
1.2.2 CAE ..............................................................................................1
1.2.3 ESDA ...........................................................................................1
1.2.4 ESDA .......................................................................2
1.3 ESDA .......................................................................................................3
1.4 EDA .................................................................................................4
1.4.1 ................................................................................................................4
1.4.2 ................................................................................................................4
1.5 ...........................................................................................................................4
2 Quartus II..........................................................................................................................................5
2.1 Quartus II .....................................................................................................................5
2.2 Quartus II .................................................................................................................7
3 ......................................................................................8
3.1 .........................................................................8
3.1.1 2FSK ................................................................................8
3.1.2 2FSK ....................................................................................................9
3.1.3 2FSK ..................................................................................................10
3.1.4 2FSK ..................................................................................................10
3.2 (FSK) VHDL ..........................................................11
3.2.1 FSK VHDL .........................................................................................11
3.2.2 FSK VHDL ........................................................................................17
3.3 ....................................................................................................19
4 ........................................................................................................................................20
5 ........................................................................................................................................21
6 ................................................................................................................................................22

III

1
1.1 EDA
EDA Electronic Design Automation 20
90 CADCAM
CATCAEEDA
EDA HDL

1.2 EDA
30 EDA

1.2.1 CAD
IC PCB

1.2.2 CAE
CAD

CAE
PCB

1.2.3 ESDA
CAD/CAE
EDA

ESDA

1.2.4 ESDA
"" : 10
""Bottom-Up

""Top-Down

ASIC :

ASIC (Application Specific Integrated

Circuits)ASIC ASIC
ASIC ASIC ASIC

IC

ASIC

ASIC
, IC

PALGALCPLDFPGA CPLD/FPGA
200 / ASIC

ASIC
ASIC CPLD/FPGA

: HDL-Hardware Description
Language

32
500 1000 VHDL A=B+C
VHDL ABELHDLAHDL EDA
1985
VHDL(Very High Speed IC Hardware Description Language) 1987
IEEE VHDL IEEE STD-1076 ---- VHDL

2

, VHDL

VHDL VHDL VHDL

VHDL

VHDL VHDL
EDA
: EDA (Framework)
EDA EDA Cadence
Design FrameworkMentor Falcon Framework
CFI (CAD Framework Initiative)
Framework EDA

Top-Down

1.3 ESDA
ESDA
""
ASIC
HDL

1.4 EDA

1.4.1

PCB
PCB

PCB

EDA

1.4.2
90

1.5
""


EDA

""
: VHDL

VHDL

VHDL
, ASIC

VHDL

FPGA CPLD
ASIC

2 Quartus II
2.1 Quartus II
Quartus II Altera PLD
VHDLVerilogHDL AHDLAltera Hardware Description Language

PLD
Quartus II XPLinux Unix Tcl

Quartus II Altera IP LPM/MegaFunction

EDA
EDA
Quartus II DSP Builder Matlab/Simulink
DSP Altera SOPC

Maxplus II Altera PLD

Altera Maxplus II
Quartus II Altera
Quartus II SignalTap IIChip Editor RTL Viewer
SOPC HardCopy Maxplus II

Altera Quartus II ,

Altera Quartus II PLD

Internet
Quartus Cadence ExemplarLogic MentorGraphics Synopsys
Synplicity EDA LogicLock
FastFit
MAX7000/MAX3000
Quartus II design system-on-aprogrammable

chip (SOPC)QuartusII design timing closure

LogicLock QuartusII design timing
closure programmable logic device (PLD)
Quartus II
FPGA mask-programmed devices

Altera Quartus II ,

Altera Quartus II 3.0 FPGA

HardCopy
Stratix FPGA HardCopy Stratix
Quartus II HardCopy
Stratix
Altera Quartus II PLD
Internet
Quartus Cadence ExemplarLogic MentorGraphics Synopsys
Synplicity EDA LogicLock
FastFit

2.2 Quartus II
MAX7000/MAX3000
2.0 Quartus II Altera APEX 20KE APEX

20KC APEX IIARM Excalibur MercuryFLEX10KE

ACEX1K MAX3000AMAX7000 MAX3000A MAX7000
QuartusII

QuartusII2.0 290M, 700M,
Excalibur 460M, QuartusII1.1
ALTERA
1.1
LogicLock 15%
QuartusII2.0 LogicLock
15%LogicLock
LogicLock
SOPC
2.0 Quartus II LogicLock
Altera

QuartusII2.0
50%
6

2.0 Quartus II
SOPC SignalProbe

SignalProbe SignalTap
HDL HDL
2.0 Quartus II QuartusII
HDL
2.0 Quartus II I/O I/O
IBIS EDA IBIS
I/O

3
3.1
ft

(FSK)

3.1.1 2FSK
(2FSK) s(t) 01
Uct

2FSK

--- 3.1
st l01001 2FSK 3.1

3.1.1 2FSK

3.1.2 2FSK
2FSK

(FM)
3.1.2

3.1.2 2FSK

3.1.3

3.1.3 2FSK

fc1 fc2 1 0
fc1 fc2

3.1.3 2FSK
2FSK 49
410 2A5K

3.1.4 2FSK

3.1.5 2FSK

3.1.4 2FSK
(3.1)2FSK
9

(B)

3.2 (FSK) VHDL

(F3K)
.

3.2.1 FSK VHDL

1.FSK
FSK 728 FSK 2
I 728 2 *2 l
0 f1
1 f2 FSK

3.2.1 FSK
2.FSK VHDL
FSK VHDL

10

3.2.2 FSK

3.FSK VHDL
LIBRARY IEEE;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FSK IS
PORT(CLK:IN STD_LOGIC;
START:IN STD_LOGIC;
X:IN STD_LOGIC;
Y:OUT STD_LOGIC);
END FSK;
ARCHITECTURE BEHAV OF FSK IS
SIGNAL Q1:INTEGER RANGE 0 TO 11;
SIGNAL Q2:INTEGER RANGE 0 TO 3;
SIGNAL F1,F2:STD_LOGIC;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF START='0' THEN Q1<=0;
ELSIF Q1<=5 THEN F1<='1';Q1<=Q1+1;
ELSIF Q1=11 THEN F1<='0';Q1<=0;
ELSE F1<='0';Q1<=Q1+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF START='0' THEN Q2<=0;
ELSIF Q2=1 THEN F2<='0';Q2<=0;
ELSIF Q2<=0 THEN F2<='1';Q2<=Q2+1;
ELSE F2<='0';Q2<=Q2+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,X)
11

BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF X='0' THEN Y<=F1;
ELSE Y<=F2;
END IF;
END IF;
END PROCESS;
END BEHAV;
4.FSK VHDL
1 VHDL file
2

3 PROJECT

12

13

14

8
FSK

FSK

15

3.2.2 FSK VHDL

1.FSK
FSK 730
. 728() 1
2 FSK
f1 f2 f12f2l f1
0 f2 730 f1
1 1/f1 0
1f2 01
f1

3.2.3 FSK

16

2. FSK VHDL

3.2.4 FSK

3. FSK
LIBRARY IEEE;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FSK2 IS
PORT(CLK:IN STD_LOGIC;
START:IN STD_LOGIC;
X:IN STD_LOGIC;
Y:OUT STD_LOGIC);
END FSK2;
ARCHITECTURE BEHAV OF FSK2 IS
SIGNAL Q:INTEGER RANGE 0 TO 11;
SIGNAL XX:STD_LOGIC;
SIGNAL M:INTEGER RANGE 0 TO 5;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN XX<=X;
IF START='0' THEN Q<=0;
ELSIF Q=11 THEN Q<=0;
ELSE Q<=Q+1;
END IF;
END IF;
END PROCESS;
PROCESS(XX,Q)
BEGIN
IF Q=11 THEN M<=0;
ELSIF Q=10 THEN
IF M<=3 THEN Y<='0';
ELSE Y<='1';
END IF;
ELSIF XX'EVENT AND XX='1' THEN M<=M+1;
END IF;
17

VHDL

END PROCESS;
END BEHAV;
4.FSK VHDL
FSK FSK

1 FSK

FSK

3.3
FPGA FPGA
FPGA

18

4
FPGA
Quartus
FPGA

Quartus

5
[ 1 ] .VHDL .,2006.
19

[ 2 ] .EDA CPLD/FPGA .,2007.

[ 3 ] . Quartus FPGA/CPLD .
2007.
[ 4 ] ..2003.
[ 5 ] .EDA .2004.
[ 6 ] .VHDL .2003 .
[ 7 ] .CPLD/FPGA .2002.
[ 8 ] .VHDL .2004.
[ 9 ] .VHDL .1997.
[ 10 ] ..2004.
[ 11 ] ASIC .VHDL 100 .1999.
[ 12 ] . EDA .2003.
[ 13 ] .VHDL .2003.

20

Vista
Proteus

VHDL
CPLD/FPGA

21