OR

8. For the common gate circuit shown in the following fig.4 calculate
the transfer function and the input impedance, Zin, explain why
Zin becomes independent of CL as it increases.
12

UNIT-V
9. a) Describe Op-amp design parameters providing why and where
each of them become important.
b) Explain the stability considerations in op-amps.

6
6

OR

10. a) Bring out a detailed comparison of various performance aspects

of op-amp topologies.
6
b) Explain the slewing characteristics in two stage op-amps.

[12/IS/209]

[EPRVD 104]

M.Tech. DEGREE EXAMINATION

VLSI Design
I SEMESTER
ANALOG IC DESIGN
(Effective from the DSSP admitted batch 200910)

Time: 3 Hours
Max.Marks: 60
----------------------------------------------------------------------------------Instructions: Each Unit carries 12 marks.
Answer all units choosing one question from each unit.
All parts of the unit must be answered in one place only.
Figures in the right hand margin indicate marks allotted.

----------------------------------------------------------------------------------UNIT-I
1. a) Explain the concept of MOS transistor with necessary V-I
relationships and describe the second order effects.
b) Consider an NMOS device with VG = 1.5V and VS = 0.
Explain what happens if we continuously decrease VD below
zero or increase Vswb above zero.

OR

2. a) What are the parasitic capacitances of MOSFET and derive a

small signal model that have an impact on the electrical
behavior of the circuit and influence its electrical properties.
Give a graphical overview of different operations involved in a
typical photolithographic process.
b) For an NMOS transistor, the threshold voltage is known but
= = 0. If we cannot
nCox and W/L are not. Assume
measure Cox independently, is it possible to devise a sequence
of dc measurement tests to determine nCox and W/L? What if
we have two transistors and we know one has twice the aspect
ratio of the other?
UNIT-II
3. a) Explain the low frequency behavior of a single stage CMOS
amplifier with necessary analysis.

b) In the circuit of the fig 1 M1 is biased in saturation with a

drain current equal to I1. The current source Is = 0.7 I1 is
added to the circuit. Derive the expression for Voltage gain
and comment on gm2.

OR

4. a) Derive the small signal voltage gain of CS stage with Diode

connected load configuration.

b) What is the importance of cascade amplifier? Obtain the

expression for voltage gain and output impedance.

UNIT-III
5. a) Quantify the behavior of a MOS differential pair as a function
of the input differential voltage and arrive at an expression with
large signal analysis.
6
b) For the basic differential transistor pairs with MOS and
current source loads, calculate the differential voltage gain if
Iss = 1 ma, (W/L)1,2 = 50/0.5 and (W/L)3,4 = 50/1. What is the
minimum allowable input CM level if Iss required atleast 0.4v
across it? Using this value for VinCM. Calculate the maximum
output voltage swing in each case.
6
OR

6. a) For the following circuit of fig.2

Assume (W/L)1.2 = 25/0.5, nCox = 50 A/V2, VTH = 0.6V,
= = 0, and VDD = 3V.
i) What is the required input CM for which RSS sustains
0.5 v?
ii) Calculate RD for a differential gain of 5.
iii) What happens at the output if the input CM level is 50 mV
higher than the value calculated in (a)?

b) Give the analysis of small signal behavior of basic current

mirror and bring out the importance of active and cascade
current mirrors.
UNIT-IV
7. a) Calculate the transfer characteristics and output impedance of
the following circuit shown in Fig.3.

b) Explain the loading in voltage-voltage feedback and currentcurrent feed back in MOS amplifiers.