EE/CS 499/599

Verilog HDL
Final Examination
Take Home
Due Friday May 15, 2004 @ Midnight.

Name:

Instructions (Read this first!!!):

The exam is worth 200 points. There are 10 Problems. Each problem is worth 25 points.
You must complete problem 1 (true/false) and at least 7 other problems. If you do more
than the 7 problems, your overall score will be based on your best 7 problems and
problem 1. This exam is take-home. Do your own work, please dont work together on
this exam. Type all of your answers in this document. E-mail the completed exam to me
by Midnight, Friday, May 15, 2004.
1) Answer True or False for each statement.
a. UDPs are synthesizable.
b. = = is the case equality operator.
c. != = is the case inequality operator.
d. ^ is the power operator in Verilog 2001.
e. The OR reduction of vector A would be written as: |A
f. initial is a synthesizable construct.
g. The system task: $display executes only when it is called.
h. Switch level modeling is a level of abstraction in Verilog.
i. The reg datatype is used primarily in gate-level modeling.
j. The integer datatype is unsigned.
k. A scalar wire is the default datatype in Verilog.
l. Port order doesnt matter when using port order instantiations.
m. (4b1000 | 4b0000) would give the result: 4b1000.
n. signed is a keyword in Verilog 95.
a. Synthesis may have a hard time inferring clock trees.
b. assign statements are not synthesizable.
c. Synthesis tools always assume a complete sensitivity list when there is an
incomplete sensitivity list in the RTL code.
d. In Verilog 2001 the statement always @(*) infers a complete sensitivity
list.
e. RTL coding can synthesize to synchronous logic.
f. Non-blocking assignments are used when inferring synchronous logic.
g. Non-blocking assignments are used when inferring combinational logic.
h. UDPs always have the output listed last.
i. The $setup system task has to be in the specify block.
j. A task without timing control is NOT synthsizable.
k. A function synthesizes to combinational logic.
l. %t is setup and defined by $realtime system task.
m. $monitor displays the steady-state value.
n. $readmem is a system task to read files into a 2D array.
o. 74LS74 is a legal identifier.
p. In the statement assign a = b both a and b have to be reg data type.
q. $setup is a timing check system task.

r. The $hold system task can be declared anywhere in the module.

s. Lumped Delay, Distributed Delay, and Triplet modeling are the three
different ways to specify delay in a simulation model.
t. UDPs cannot be initialized.
u. Only combinational logic can be modeled with a UDP.
v. UDP is an acronym for Unified Development Program.
w. SDF files are a subset of the Verilog language.
x. The statement `include myfile.txt should end with a semicolon.
y. Verilog is a Hardware Description Language

2) Write the Verilog code for a negative edge triggered D flip flop with an active low
asynchronous RESET. Name the module dffrn. Name the ports (in this order) Q, D,
CLK, RESET. Write the full module, declaring ALL data types. Write a testbench to
stimulate the dffrn module. Instantiate the module using named port mapping. You
chose the period of CLK.

3) Create a Verilog simulation model that represents the following circuit. Be sure to
include all pin-to-pin delays. Use specparams to define the pin-to-pin rise and fall
times. The default timing on the pin-to-pin delays is 0.125ns. Name the module
anxnna.

A
B

w1

w2
C

OUT
w3

w4
D
S1 S2

4) Write the Verilog code for the following diagram. Assume negative edge triggered
flops, and an active low synchronous reset. Use dataflow modeling (assign statements)
for the combinational elements. Use separate procedures for each flop element.

5) Write the Verilog code to implement a device that will shift in serial data and
increment a counter every time the pattern 16hAFAF is found. The counter will reset
every 1000 clock cycles. Assume positive edge triggered flop(s) and asynchronous active
high reset. The only output of the device will be the counter. The only inputs will be
data, clock, and reset. Use normal procedural statements to create the design.

6) Recode problem 5 as a finite state machine. Declare all state variables. Put the
synchronous elements in one process and the combinational in the other. Create a
separate module for the timer that is controlled by the State Machine. State names
and encoding is up to you.

7) Create a User Defined Primitive (UDP) for a positive edge triggered D Flip-Flop
with an active low reset and a notifier. Name the ports: Q, CLK, DATA, RN,
NOTIFY.

8) Instantiate the UDP in problem 7 in a higher level module. Write a testbench for
the higher level module. In the testbench, use constructs to create an output file
called simulation.txt. The simulation.txt file should be the results from
monitoring all inputs and output(s) of the UDP.

9) Write the full Verilog module that creates 4 flip-flops with the output of the first
flop feeding the input of the second flop, the output of the second flop feeding the
input of the third flop, and so forth. The ports will be declared as DATA,
CLOCK, RESETN, Q. Q will be the output. RESETN is an active low
asynchronous reset. The flops are rising edge CLOCK triggered.

10) Write the Verilog code for Problem 4 using Verilog 2001 constructs described in
section 18 of the class lectures. Declare the ports and data types in a manner that
is the least verbose. Put the combinational elements in procedures separate from
the synchronous elements. Use constructs that ensure full sensitivity lists for the
combinational elements. Write a testbench that instantiates the design 4 times.
Use bussed port names in the testbench. Use the generate loop to create the
instantiations.