Madan H R

Phone +91 81090 34545 / +91 90607 34545

E-Mail madan.shaanbhog@gmail.com
Summary

Senior Consultant to Vice-Chancellor

-Chhattisgarh Swami Vivekanand Technical University, Bhilai

(Feb 2014 Till date)

Assisting the Honble Vice-Chancellor in Academic and Administrative activities
Involved in revamping of Research Cell of the University
Instrumental in getting assistance of 40 Galileo Gen II Microcontroller Kits from Intel India Higher Education
and in organizing training programs
B M S Institute of Technology, Bangalore

- Assistant Professor

Department of Electronics and Communication Engineering

(July 2013 to Jan 2014)
Responsibilities
Teaching, preparation of Lab manuals
Residential Warden, BMSIT Boys Hostel
Accomplishments
Guided seven academic projects in a short span of one semester.
Involved in execution of MoUs with Industries and educational institutions/universities (Executed 13 MoUs).
Assisting Chief Mentor of the Institute in administrative and research related matters
Served as Residential Warden at BMSIT Hostel.
Sorted out many issues relating to indiscipline and chaos and brought discipline in the college hostel.
Have a very good rapport with students who are still in communication, executing academic and research
projects under my guidance
Mentoring students in executing academic and research projects
Karnataka State Higher Education Council, Government of Karnataka - Coordinator, (On deputation
from Tumkur University)
(May 2013 June 2013)
Responsibilities
Coordination of RUSA activities
To assist the Vice-Chairman, Karnataka State Higher Education Council, Government of Karnataka
Accomplishments
Was coordinating with universities and higher education institutions across the state
Played a key role in bringing out VISION 2020 book published by Karnataka State Higher Education
Council
Was responsible in organizing 15 national seminars and conferences
Organized a seminar on Rashtriya Ucchatar Shiksha Abhiyan (RUSA)
Tumkur University - Coordinator for Center for VLSI Design (CVLSID),
Intel Embedded System Design laboratory
(November 2012 April 2013)
Responsibilities
Establishment of Center for VLSI Design Research center and Intel Embedded System Design Laboratory
Accomplishments
With the support of Honble Vice-Chancellor, established Center for VLSI Design (CVLSID)
Established Intel embedded System Design Laboratory sponsored by Intel India Higher education
Was instrumental in designing MSc in VLSI & Embedded System Design and MSc in Digital Design course

Guest LecturerDepartment of Electronics, University College of Science,

Tumkur University (August 2011 - October 2012) Promoted as Coordinator for Intel laboratory
in November 2012

Involved in teaching B.Sc PME Students

Was guiding students in final semester academic projects
Was a member of Organizing Committee in organizing National Conference in Recent Trends in
Communication Systems

RV College of Engineering - Teaching Assistant Department of ECE, RV College of Engineering,

Bengaluru
(October 2008 - August 2011)
Departmental Placement Coordinator for the academic year 2010-2011
Involved in the execution of two funded research projects
1. Project Name
:Real time rudder actuation system of autonomous ship
Client
: Naval Research Board
Duration
: 24 months
Role
: Co-principal Investigator
1. Project Name
: Power Optimization in underwater Ad Hoc Sensor Networks
Client
: Naval Research Board
Duration
: 24 months
Role
: Co-principal Investigator
100% result in all the subjects taught (theories and labs)
Was the departmental placement coordinator in the academic year 2010-11
Lecturer - MN Degree College, Bengaluru
(July 2008 - Oct 2008)
Teaching Basic Electronics and Basics of Computer Programming to BCA students
Project 1

Project Name
: Characterization of Reversible Gates
Planned Duration
: 10 months
Role
: Designer
Objectives of project
Characterize Reversible gates and to include the same in VLSI tools and execute the following:
Understanding Reversible Logic Design
Study and Analysis of Reversible circuits and Reversible gates
To learn tools that supports circuit characterization like LIBERTY.NCX supported by Synopsys
To characterize Reversible gates using tool/s that supports circuit characterization like LIBERTY.NCX
(To verify the same and add them to VLSI tools such as Cadence and Synopsys based tools)
Scope of proposed work
Design of Ideally Zero power dissipating Circuits using VLSI tools like Synopsys and Cadence based tools
To familiarize Reversible circuits (Zero Power Dissipating Circuits) to VLSI Designers
Summary of the proposed research:

Learning Circuit Characterizing tools like LIBERTY.NCX

Characterize Reversible gates which ideally dissipates zero power

Adding the same models or symbols to VLSI tools; advantage: Easier Design of Zero Power Dissipating Circuits

Necessity and advantages: Planned models / gates will be

More robust

Reliable

Flexible

Consumes very less power and

Ideally dissipates zero power.

Test and Validation includes Simulation considering all Variation Corners and dynamics.
Project 2:

Project Name

: Design and performance comparison of 6T, 8T and 9T SRAM cells

Abstract
This thesis explores the analysis and comparative study of SRAMs, focusing on the important parameters like static
noise margin (SNM), read and write noise margin, read and write delay, data retention voltage, read and write
stability and leakage current.
Duration

: One Year

Place of work

: RVCenter for Cognitive Technologies (RVCCT), Bangalore

Project 3:

Project Name

: Automation of Railway Department using Embedded Microcontroller

Abstract
Project implements the Wireless technique and provides the easiest automation to the railway department. This is
basically made of five sub-projects, whose combination makes the railway automation still stronger.

Wireless Signaling System

Anti-collision System

Automatic Gate Control

Train Approaching Indicator

Signaling at track junction:

Main features of the project

Simple in design, Robust and highly reliable

Low power consumption, and compact size
Remote signaling lights can be monitored using only one Receiver.
High reliability, due to the usage of power semiconductor devices
Greater control range due the usage of Frequency Modulation.
Devices monitored simultaneously from a remote area ('line-of-sight arrangement not required)
Place of work

: Dr. AIT, Bangalore

Duration

: 3 months

Role

: Developer

Academic Profile

Examination

University

(Ph.D)

Tumkur University

(MBL)

National Law School of India, Bangalore

(2012 - )
Pursuing
(2013 - )

Sikkim Manipal University, Bengaluru

2012

RVCCT, Mangalore University

2010

VisvesvarayaTechnological University,
Belgaum

2008

MBA
(PROJECT MANAGEMENT)
MS
(ASIC DESIGN)
Bachelor of Engineering (ECE)

Year
Pursuing

Areas of Interest:

Reconfigurable computing
Low Power VLSI (Reversible Logic)
Circuit Characterization
SoC and NoC (system on Chip and Network on Chip)
Semiconductor memories
VLSI and Embedded system Design
Microprocessors and Microcontrollers
Digital Communication System
Wired and Wireless Communication
Publications

Papers Published in Refereed International Journals :

International Journals
1. Comparative Study of DRAM for High & Low Power CMOS process technology, M. Akshay Bhounsley1, H.
R. Madan2, H. V. Ravish Aradhya3, V. Ebenezer4, International Journal of Science Research Volume 01, Issue
03, December 2012, pp. 137-138
2. Considerations Of FinFET Based 6T SRAM Cells, M. Girish Kumar1 , H. R. Madan2, H. V. Ravish
Aradhya3 , VEbenezer4, International Journal of Science Research Volume 01, Issue 03, December 2012, pp.
134-136
3. Comparative Study of SRAM & DRAM for various CMOS process technology, M. Akshay Bhounsley11, H. R.
Madan2, H. V. RavishAradhya3, V. Ebenezer4, International Journal of Science Research Volume 01, Issue 03,
December 2012, pp. 141-143
4. Design and Performance Analysis of 8T SRAM for Different Scaled Technologies, M. F. Md.Luqman1, H. R.
Madan2, H. V.RavishAradhya3, K.Suresh4, International Journal of Science Research Volume 01, Issue 03,
December 2012, pp. 151-153
5. Design and Optimization of Reversible Carry Look Ahead Adder Circuit, Abhijith A Bharadwaj, Madan H R,
Keith Saures, H V Ravish Aradhya, International Journal of Engineering and Science Invention (IJESI), April 2014,
Received Best paper award
6. Bio-inspired route for the synthesis of spherical shaped MgO: Fe3+ nanoparticles: Structural,
Photoluminescence and Photocatalytic investigation, Madan H R, S C Sharma, H Nagabhushana,
Darukaprasad, Suresh D, Spectrochemica Acta, Molecular and Biomolecular Spectroscopy, Elsevier, Submitted
for publication October 2014, Under review, Impact Factor: 2.129
7. Facile Green Fabrication of Nanostructure ZnO Plates, Bullets, Flower, Prismatic tip, Closed pine cone: Their
Antibacterial, Antioxidant, Photoluminescent and Photocatalytic Properties, Madan H R, H Nagabhushana, S C
Sharma, D Suresh, Darukaprasad, S C Prashantha, Y S Vidya, Spectrochemica Acta, Molecular and Biomolecular
Spectroscopy, Elsevier, Submitted for publication, Submitted on December 2014, Under review, Impact
Factor: 2.129
Research Publication under progress

1. Design and optimization of Graphene based SRAM.

Involves designing a 64x8 SRAM using Graphene Nano-Ribbon FETs, at
10nm gate length and evaluation of design parameters such as power
dissipation, various capacitances, noise margin, power-delay product. (PRESENT
STATUS: Work completed. Pending documentation)
2. Design and optimization of Hybrid Reversible Carry look-ahead adder
circuit.
Involves designing a 16 bit Hybrid Carry Look-Ahead adder using reversible
logic in 10nm Graphene FET, Carbon Nano-Tube (CNTFET) andfinFET
technology. Three reversible designs are provided in comparison to the
conventional CMOS design. (PRESENT STATUS: Work completed. Pending
documentation)

3. Design and performance comparison of decomposed 1:32 De-multiplexers

Involves performance (Transistor cost, Power dissipation, input-output delay,
power delay product) comparison of multiple decomposed 1:32 Demultiplexers using Graphene Nano Ribbon FET, CNT-FET and FINFET at
10nm gate length. (PRESENT STATUS: Work completed. Pending
documentation)
4. Design of Graphene based microcontroller.
Involves designing a microcontroller using Graphene Nano-Ribbon FETs, at 10nm
gate length and evaluation
of design parameters such as power dissipation, power-delay product. (PRESENT STATUS:
Work is under
progress).
International Conferences:
1.

FPGA Implementation of SoC using softcore processors and Custom Peripherals, custom instructions for
Robotics and Automation, Anil Kumar D, Madan H R, Research & Reviews: Journal of Embedded System &
Applications, 2321 - 8533 , November 2013, pp. 01-06

National Conferences:
1. Design and Performance Analysis of 6T SRAM for Different Scaled Technologies, Md.Luqman M F,
M.GirishKumar,Madan H.R, H.V. Ravish Aradhya, Dr.K.Suresh, National conference on Recent Trends in
Communication Technology, Vol. no. 01, pp 238 244, Bangalore, January 2012
2. CMOS Realization of Reversible BCD Adder, Girish.R, AkshayBhounsley M, Madan.H.R, Mr.
H.V.RavishAradhya, Mrs. MehrunnisaBegum.S.P, National conference on Recent Trends in Communication
Technology, Vol. no. 01, pp 227 233, Bangalore, January 2012
3. Comparative Study of logic circuits based on MOSFET and FinFET under 32 nm process technology, M
Girish Kumar, Girish R, Madan H R, Mr. H V Ravish Aradhya, Mr.V Ebenezer, National conference on Recent
Trends in Communication Technology, Vol. no. 01, pp 234 237, Bangalore, January 2012
4. Comparative Study of DRAM for various CMOS process technology, AkshayBhounsley M, M D Luqman M F,
Madan H R, Mr. H V Ravish Aradhya, Mr. V Ebenezer, National conference on Recent Trends in Communication
Technology, Vol. no. 01, pp 245 251, Bangalore, January 2012
5. Cloud Security- Grand challenge for adoption of Cloud Computing, ShreyasHirethota, Srinvasa Murthy,
Madan H R, Sheshadri N, National conference on Recent Trends in Communication Technology, Vol. no. 01, pp
221 226, Bangalore, January 2012
6. CMOS Implementation of Reversible Comparators, AkshathaShrinivas, ShreyasHirethota, Madan H R,
Ravish Aradhya H V, National conference on Recent Trends in Communication Technology, Vol. no. 01, pp 252
258, Bangalore, January 2012
7. Overview of Reversible Logic, Saranya S, Ravi Raj Singh, Soumya, SapnaUpadhyay, Madan H R, National
Conference on Emerging Trends in VLSI & Embedded Systems, ISBN 978-81-928203, Oct 2013
8. Design, Analysis and Performance comparison of Finfet based and MOSFET based Carry look-ahead adder,
Madan H R, Arjun Krishna Murthy, National Symposium on Instrumentation (NSI -38) , BVB college of
Engineering,Hubli, , Oct-2013
Member

1.

Expert Committee Member, Institute of Academic and Research Council

2.

Member, Editorial Board,International Journal of Advance Research in Science and Engineering

Expert Lectures Delivered

1.

Recent Trends in VLSI Designs, Advances in Engineering & Technology (AET-2013),Institute of

Academic and Research Council, Bangalore, 2013

Awards and recognitions

Reviewer, NCKITE-2015 April 2015

1st prize -National Level Business Model Competition, RVIM, Bangalore, April 2011

1st prize in national level Science Fair, Allahabad, Nov 2001.

Best explanation award in the zonal level science fair, Pondicherry, Nov 2001.

1st prize in Zonal Level Science fairs, Pondicherry and Tirupathi, 1999 and 2000.

1st prize in state level Science Fairs thrice, 1999, 2000 and 2001.

1st prize in district level science fairs thrice, 1999, 2000 and 2001.

Taluk level SSLC topper award, BramhanaSabha, Maddur

Personal Profile:

Father

Date of Birth

RAMAMURTHY
23-June-1986

Permanent Address

:
Madan H R S/O Ramamurthy
No. 386, S I Honnalagere (Post),
Via Bharathi Nagar, C A KereHobli, MaddurTaluk,
Mandya District, Karnataka 571422

Present Address

Madan H R
No. QA 06, Behind Hanuman Mandir,
Near TV Tower, Anupamnagar, Raipur (C.G) 492 007

Can Exchange Ideas In

References

English, Kannada and Hindi.

:

Only on request

Passport

PAN

Date

January 2015

Place

Raipur

L7038432
AEGPH2720E

( Madan H R )