Sunder Deep Group of Institutions

Department of Electronics & Communication Engg.

VLSI Design
B.Tech, EC- 4th Year
Paper code: EEC-703
Section A
1. Discuss the hierarchy of various semiconductor technologies with
Moores Law and VLSI Design flow.
2. Explain the Fabrication Process of N-MOS transistor
3. Why silicon is preferred over germanium? Explain.
4. Write a short note on MOSFET Scaling.
5. Explain the Accumulation, Depletion and Inversion process in MOS
System under. External bias
6. Write a short note on channel length modulation.
7. Discuss different steps involved in a typical N- well process.
8. List the parameter that affect the switching speed of an MOS
transistor. How does the figure of merit is related to the
transconductance of an MOS transistors.
9. Discuss the important feature of Lambda based design rules.
10. What is FPGA? Discuss the design of an FPGA chip. Mention
certain advantages of it.
11. With the help of a block diagram, explain the sequence of steps to
design an ASIC. Explain the term semi-custom and full custom ASICs.
12. Write a short note on Controllability and Observability.
13. Explain Packaging Technology.

14. Define the term pull-up and pull-down network used in an inverter
circuit. Will NMOS and PMOS alone be used for PUN as well as PDN ?
Give reasons in support of your answers.
15. Explain the difference between polycide and silicide CMOS process.
Which would be likely to have higher performance and why.
16. List the parameters that affect the threshold voltage of a MOS
transistor. What is effect of high-K dielectric when used instead of SiO2
in MOSFET?
17. Which polysilicon gate ( n+ or p+) are preferred and why? Does the
present technology
18. In which region I-V characteristics the MOSFET simply acts as a
like a resistor? How does the gate voltage modify its resistivity?
19. Comparison the pass transistor logic circuit with that of transmission
gates.
20. What is the basic difference between diffusion and ion implantation
process? Why ion-implantation is preferred in modern VLSI Design
21. Explain symbol , different colours and lines used for drawing stick
diagram. Draw a stick diagram of CMOS inverter.
22. Draw a stick diagram for 2 input NAND Logic Gate using CMOS
Logic.
23. Write short notes on MOSFET Scaling and Channel Length
Modulation.
24. Draw mask layout diagram of CMOS INVERTER using lambda
based design rules.
25. Explain the concept of MOSFET as switches with help of diagram.
26. Explain the operation of MOSFET .Also discuss its VTC
characteristics.
27. Calculate threshold voltage VTO at VSB=0, for a polysilicon gate n
channel MOS transistor, with the following parameters: substrate doping
density NA=1016 cm-3 ,polysilicon gate doping density ND=2x1020
cm-3,gate oxide thickness tox=500 A0,and oxide interface fixed charge
density Nox=4x10 cm-2.

Section-B
21. Sketch the cross section and explain the operation of n-channel
enhancement type MOS transistor. Draw the characteristics of the
device. How many diffusion steps are required to form it.
22. What are different methods for CMOS fabrication process? Explain
any one of them in detail with suitable diagram.
23. Draw and Explain N-MOS inverter with enhancement mode pull up
and its transfer characteristics. Why depletion load is preferred
compared to enhancement load.
24. What a VLSI design rules? Why it is required? Describe the Lambda
based design rules and layout methodology for CMOS circuit design.
Explain with suitable diagram.
25. What do you mean by sheet resistance? Explain how the sheet
resistance concept is applied to MOS transistor and inverter.
26. Describe the standard cell based design. Enlist the various standard
cell library. What is the parameter of good VLSI Design?
27. Write a short note on Built-in-self test (BIST) techniques
28. Draw and explain the generic FPGA architecture. Discuss the
various programming technique employed in FPGA. Explain with
suitable sketch.
29. What is VLSI testing? Explain different types of fault models used in
VLSI testing.
30. Discuss stuck at fault model. Explain a stuck at 1/0 mode for testing
a logic gate with suitable example.
31. Explain N-MOS fabrication with suitable sketch.
32. Explain the MOSFET Scaling and Channel length Modulation.
33. Design a 2 input XOR logic using CMOS Transmission Gate and
compare with pass transistor and CMOS logic circuit.
34. What are the various sources of power dissipation in CMOS circuits.
35. Explain how DOMINO CMOS logic overcomes the charge sharing
problem.
36. Explain the term voltage bootstrapping in CMOS logic with suitable
example.
37. Draw the Y- chart and explain the VLSI design process.

38. Enlist the classification of CMOS digital logic families. Why CMOS
VLSI Design is better techniques than its counterpart.
39. Explain the Concept of regularity, modularity, semi custom and full
custom styles of VLSI system design.
40. Explain the scaling down of MOS transistor using Constant field
Scaling and its limitations.
42. Prove that pull-up to pull-down ratio for an NMOS inverter driven
by another NMOS inverter is 4/1.
43. Calculate the delay involved in cascade pass transistors.
44. Explain depletion Load Inverter with suitable sketch.

Section-C
41. Explain the behavior of pass transistor in dynamic CMOS logic
implementation. With a neat schematic diagram, explain SR flip flop
implementation using pass transistor logic.
42.Design the circuit describe by the Boolean function Y = A. (B+C)
(D+E) using MOS logic
Calculate the equivalent CMOS inverter circuit for simultaneous
switching of all inputs assuming that [W/L]= 5 for PMOS transistor and
[W/L]= 2 for all NMOS transistor.
43. Draw a 4 x1 multiplexer using transmission gate (TG).
44. Explain leakage currents and refresh operation in DRAM cells.
45. Give a logic circuit example in which stuck at 0 fault and stuck at 1
fault are indistinguishable.
46. Explain the different kinds of physical defect (faults) that can occur
on a CMOS circuit.
47. Explain an Adiabatic logic circuit.
48. Discuss in brief Ad-Hoc Testable design techniques.
49 .Draw six transistors SRAM cell and explain Different modes of
operation.
50. Draw a CMOS shift register circuit.
51. Draw CMOS SR and JK FLIP Flop.

 +   +
52. Implement the Boolean function
, ,   = .
 using COMS logic.
53. Derive the expression for VIH, VIL, NML, and NMH for CMOS inverter.
54. Explain CMOS edge triggered flip flop with help of input and output
waveforms.

Section-D
1. Explain Leakage current and Refresh operation in DRAM cell..
2. Write the Difference between Dynamic CMOS logic circuit and
Static CMOS logic circuit.
3. Write a short note on DRAM cells. Explain leakage currents and
refresh operation in DRAM cells.
4. Discuss with a neat diagram the operation of CMOS SRAM
CELL.
5. Explain and draw 2X4 decoder circuit and implement with a
suitable diagram.
6. Explain the behaviour of Pass Transistor in dynamic CMS logic
implementation.
7. Draw CMOS Shift register and full adder circuit.
8. Explain how DOMINO CMOS logic overcome the charge sharing
problem.
9. Enlist the advantage of dynamic logic circuit over sttic logic
circuit. Explain DOMINO and NORA CMOS logic circuit with
suitable example.
10. What is Flash Memory ? Explain NAND flash memory cell.
11. Explain the classification of Dynamic CMOS logic circuit and
design a 2 input EXOR logic Gate using Domino logic.

Section-E
1. Explain the effect of constant voltage scaling on delay and power
delay product.
2. Explain the term voltage bootstrapping in CMOS logic with
suitable example.
3. Explain various types of power dissipation in CMOS circuits.
4. Write a short note on adiabatic logic circuit. Differentiate between
single struct-at fault and multiple struct-at fault.
5. Define the term controllability and observability. Discuss in brief
Ad-hoc testable design techniques.
6. Write a short note on Built-in-self test (BIST) techniques
7. Explain the following :
(i) Scan Based Technique.
(ii)Fault types and models.