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FEATURES
ANALOG I/O
8-Channel, 247 kSPS 12-Bit ADC
DC Performance: 1 LSB INL
AC Performance: 71 dB SNR
DMA Controller for High Speed ADC-to-RAM Capture
2 12-Bit (Monotonic) Voltage Output DACs
Dual Output PWM/- DACs
On-Chip Temperature Sensor Function 3C
On-Chip Voltage Reference
Memory
62 kBytes On-Chip Flash/EE Program Memory
4 kBytes On-Chip Flash/EE Data Memory
Flash/EE, 100 Yr Retention, 100 kCycles Endurance
2304 Bytes On-Chip Data RAM
8051-Based Core
8051 Compatible Instruction Set (16 MHz Max)
32 kHz Ext Crystal, On-Chip Programmable PLL
12 Interrupt Sources, 2 Priority Levels
Dual Data Pointer
Extended 11-Bit Stack Pointer
On-Chip Peripherals
Time Interval Counter (TIC)
UART, I2C , and SPI Serial I/O
Watchdog Timer (WDT), Power Supply Monitor (PSM)
Power
Specified for 3 V and 5 V Operation
Normal, Idle, and Power-Down Modes
Power-Down: 25 A @ 3 V with Wake-Up cct Running
APPLICATIONS
Optical NetworkingLaser Power Control
Base Station Systems
Precision Instrumentation, Smart Sensors
Transient Capture Systems
DAS and Communications Systems
Upgrade to ADuC812 Systems. Runs from 32 kHz
External Crystal with On-Chip PLL.
Also Available: ADuC831 Pin Compatible Upgrade to
Existing ADuC812 Systems that Require Additional
Code or Data Memory. Runs from 1 MHz16 MHz
External Crystal.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
ADC0
T/H
ADC1
12-BIT
DAC
BUF
DAC
12-BIT
DAC
BUF
DAC
12-BIT ADC
16-BIT
DAC
MUX
ADC5
ADC6
ADC7
HARDWARE
CALIBRATON
16-BIT
DAC
PWM0
MUX
16-BIT
PWM
TEMP
SENSOR
PWM1
16-BIT
PWM
INTERNAL
BAND GAP
VREF
VREF
4 PARALLEL
PORTS
OSC
XTAL1
XTAL2
GENERAL DESCRIPTION
The ADuC832 is a complete smart transducer front end, integrating a high performance self-calibrating multichannel 12-bit ADC,
dual 12-bit DACs, and programmable 8-bit MCU on a single chip.
The device operates from a 32 kHz crystal with an on-chip PLL
generating a high frequency clock of 16.77 MHz. This clock is, in
turn, routed through a programmable clock divider from which
the MCU core clock operating frequency is generated. The microcontroller core is an 8052 and therefore 8051 instruction set
compatible with 12 core clock periods per machine cycle. 62 kBytes
of nonvolatile Flash/EE program memory are provided on-chip.
4 kBytes of nonvolatile Flash/EE data memory, 256 bytes RAM,
and 2 kBytes of extended RAM are also integrated on-chip.
The ADuC832 also incorporates additional analog functionality
with two 12-bit DACs, power supply monitor, and a band gap
reference. On-chip digital peripherals include two 16-bit -
DACs, dual output 16-bit PWM, watchdog timer, time interval
counter, three timers/counters, Timer 3 for baud rate generation,
and serial I/O ports (SPI, I2C, and UART)
On-chip factory firmware supports in-circuit serial download and
debug modes (via UART) as well as single-pin emulation mode
via the EA pin. The ADuC832 is supported by QuickStart and
QuickStart Plus development systems featuring low cost software
and hardware development tools. A functional block diagram of
the ADuC832 is shown above with a more detailed block diagram
shown in Figure 1.
The part is specified for 3 V and 5 V operation over the extended
industrial temperature range and is available in a 52-lead plastic
quad flatpack package and a 56-lead chip scale package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 Analog Devices, Inc., 2002. All rights reserved.
ADuC832
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
15
15
15
15
16
16
16
18
18
18
18
19
20
21
22
23
24
24
25
25
25
27
27
27
27
28
28
28
32
33
35
36
39
41
43
44
45
46
48
48
51
56
56
57
57
58
58
59
60
61
61
62
62
63
63
64
64
65
65
66
66
66
DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . 66
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . 67
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . 77
REV. 0
ADuC832
= DV = 2.7 V to 3.3 V or 4.5 V to 5.5 V; V = 2.5 V Internal Reference, F
T = T to T , unless otherwise noted.)
SPECIFICATIONS1 (AVall specifications
DD
DD
REF
Parameter
MIN
VDD = 5 V
CORE
=16.78 MHz;
MAX
VDD = 3 V
Unit
Test Conditions/Comments
12
1
0.3
0.9
0.25
1.5
+1.5/0.9
1
Bits
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB max
LSB typ
4
1
2
85
4
1
3
85
LSB max
LSB typ
LSB max
dB typ
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)7
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Channel-to-Channel Crosstalk8
ANALOG INPUT
Input Voltage Ranges
Leakage Current
Input Capacitance
TEMPERATURE SENSOR9
Voltage Output at 25C
Voltage TC
Accuracy
71
85
85
80
dB typ
dB typ
dB typ
dB typ
0 to VREF
1
32
0 to VREF
1
32
V
A max
pF typ
650
2.0
3
1.5
650
2.0
3
1.5
mV typ
mV/C typ
C typ
C typ
12
3
1
1/2
50
1
1
0.5
12
3
1
1/2
50
1
1
0.5
Bits
LSB typ
LSB max
LSB typ
mV max
% max
% typ
% typ
ANALOG OUTPUTS
Voltage Range_0
Voltage Range_1
Output Impedance
0 to VREF
0 to VDD
0.5
0 to VREF
0 to VDD
0.5
V typ
V typ
typ
DAC AC CHARACTERISTICS
Voltage Output Settling Time
15
15
s typ
10
10
nV sec typ
Offset Error
Gain Error
Gain Error Mismatch
REV. 0
ADuC832
SPECIFICATIONS (continued)
Parameter
VDD = 5 V
VDD = 3 V
Unit
Test Conditions/Comments
12
3
1
1/2
5
0.3
0.5
12
3
1
1/2
5
0.3
0.5
Bits
LSB typ
LSB max
LSB typ
mV max
% typ
% max
VREF Range
VREF Range
% of Full-Scale on DAC1
ANALOG OUTPUTS
Voltage Range_0
0 to VREF
0 to VREF
V typ
REFERENCE INPUT/OUTPUT
REFERENCE OUTPUT14
Output Voltage (VREF)
Accuracy
Power Supply Rejection
Reference Temperature Coefficient
Internal VREF Power-On Time
2.5
2.5
47
100
80
2.5
2.5
57
100
80
V
% max
dB typ
ppm/C typ
ms typ
0.1
VDD
20
1
0.1
VDD
20
1
V min
V max
k typ
A max
12, 13
2.63
4.37
V min
V max
3.5
% max
0
2000
0
2000
ms min
ms max
100,000
100
100,000
100
Cycles min
Years min
2.4
0.8
10
1
2
0.4
10
1
V min
V max
A max
A typ
10
1
75
40
660
400
10
1
25
15
250
140
A max
A typ
A max
A typ
A max
A typ
VIN = 0 V or VDD
VIN = 0 V or VDD
VIN = VDD
VIN = VDD
VIL = 450 mV
VIL = 2 V
VIL = 2 V
REV. 0
ADuC832
Parameter
VDD = 5 V
VDD = 3 V
Unit
Test Conditions/Comments
1.3
3.0
0.8
1.4
0.3
0.85
0.95
2.5
0.4
1.1
0.3
0.85
V min
V max
V min
V max
V min
V max
CRYSTAL OSCILLATOR
Logic Inputs, XTAL1 Only
VINL, Input Low Voltage
VINH, Input High Voltage
XTAL1 Input Capacitance
XTAL2 Output Capacitance
0.8
3.5
18
18
0.4
2.5
18
18
V typ
V typ
pF typ
pF typ
16.78
16.78
MHz max
2.4
2.6
V min
V typ
V min
V typ
0.4
0.2
0.4
0.4
0.4
0.2
0.4
0.4
V max
V typ
V max
V max
ISINK = 1.6 mA
ISINK = 1.6 mA
ISINK = 4 mA
ISINK = 8 mA, I2C Enabled
10
1
10
10
1
10
A max
A typ
pF typ
500
100
500
100
ms typ
s typ
150
150
150
30
3
400
400
400
30
3
s typ
s typ
s typ
ms typ
ms typ
DIGITAL OUTPUTS
Output High Voltage (VOH)
REV. 0
2.4
4.0
ADuC832
SPECIFICATIONS (continued)
Parameter
POWER REQUIREMENTS
Power Supply Voltages
AVDD/DVDD AGND
VDD = 5 V
VDD = 3 V
Unit
Test Conditions/Comments
2.7
3.3
V min
V max
V min
V max
AVDD/DVDD = 3 V nom
19, 20
4.5
5.5
Power Supply Currents Normal Mode
DVDD Current4
AVDD Current
DVDD Current
AVDD Current
Power Supply Currents Idle Mode
DVDD Current
AVDD Current
DVDD Current4
AVDD Current
Power Supply Currents Power-Down Mode
DVDD Current4
AVDD Current
DVDD Current
Typical Additional Power Supply Currents
PSM Peripheral
ADC
DAC
AVDD/DVDD = 5 V nom
6
1.7
23
20
1.7
3
1.7
12
10
1.7
mA max
mA max
mA max
mA typ
mA max
4
0.14
10
9
0.14
2
0.14
5
4
0.14
mA typ
mA typ
mA max
mA typ
mA typ
80
38
2
35
25
25
14
1
20
12
A max
A typ
A typ
A max
A typ
A typ
mA typ
A typ
50
1.5
150
Osc. Off
AVDD = DVDD = 5 V
NOTES
1
Temperature Range 40C to +125C.
2
ADC linearity is guaranteed during normal MicroConverter core operation.
3
ADC LSB Size = V REF/212 i.e., for Internal V REF = 2.5 V, 1 LSB = 610 V and for External VREF = 1 V, 1 LSB = 244 V.
4
These numbers are not production tested but are guaranteed by design and/or characterization data on production release.
5
Offset and Gain Error and Offset and Gain Error Match are measured after factory calibration.
6
Based on external ADC system components, the user may need to execute a system calibration to remove additional external channel errors and achieve these
specifications.
7
SNR calculation includes distortion and noise components.
8
Channel-to-channel crosstalk is measured on adjacent channels.
9
The Temperature Monitor will give a measure of the die temperature directly; air temperature can be inferred from this result.
10
DAC linearity is calculated using:
Reduced code range of 100 to 4095, 0 to V REF range.
Reduced code range of 100 to 3945, 0 to V DD range.
DAC Output Load = 10 k and 100 pF.
11
DAC differential nonlinearity specified on 0 to V REF and 0 to VDD ranges.
12
DAC specification for output impedance in the unbuffered case depends on DAC code.
13
DAC specifications for I SINK, voltage output settling time and digital-to-analog glitch energy depend on external buffer implementation in unbuffered mode. DAC in
unbuffered mode tested with OP270 external buffer, which has a low input leakage current.
14
Measured with VREF and CREF pins decoupled with 0.1 F capacitors to ground. Power-up time for the internal reference will be determined by the value of the
decoupling capacitor chosen for both the V REF and CREF pins.
15
When using an external reference device, the internal band gap reference input can be bypassed by setting the ADCCON1.6 bit. In this mode, the V REF and CREF
pins need to be shorted together for correct operation.
16
Flash/EE Memory reliability characteristics apply to both the Flash/EE program memory and the Flash/EE data memory.
17
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at 40C, +25C, and +125C. Typical endurance at 25C is 700,000 cycles.
18
Retention lifetime equivalent at junction temperature (T J) = 55C as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6 eV
will derate with junction temperature as shown in Figure 18 in the Flash/EE Memory description section.
19
Power supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions:
Normal Mode:
Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop.
Idle Mode:
Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in
idle mode.
Power-Down Mode:
Reset = 0.4 V, All Port 0 pins = 0.4 V, All other digital I/O and Port 1 pins are open circuit, Core Clk changed via CD bits in PLLCON,
PCON.0 = 1, Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in PLLCON SFR
20
DVDD power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.
Specifications subject to change without notice.
REV. 0
ADuC832
ABSOLUTE MAXIMUM RATINGS*
(TA = 25C, unless otherwise noted.)
ORDERING GUIDE
Model
ADuC832BS
ADuC832BCP
EVAL-ADuC832QS
EVAL-ADuC832QSP
Temperature
Range
Package
Description
Package
Option
40C to +125C
40C to +85C
S-52
CP-56
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADuC832 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
ADuC832
MCU
CORE
PSEN
44
43
EA
P0.0/AD0
27
28
P3.7/RD
SCLOCK
26
P3.6/WR
16-BIT
- DAC
PWM0
MUX
16-BIT
PWM
PWM1
T0
16-BIT
COUNTER
TIMERS
T1
T2
PROG. CLOCK
DIVIDER
SS
MISO
SDATA/MOSI
SYNCHRONOUS
SERIAL INTERFACE
(SPI OR I2C )
SCLOCK
SINGLE-PIN
EMULATOR
EA
ALE
UART
TIMER
INT0
INT1
TIME INTERVAL
COUNTER
(WAKEUP CCT)
PSEN
TxD
RxD
RESET
DGND
DGND
DVDD
DGND
DVDD
ALE
25
P3.5/T1/CONVST
DAC1
T2EX
DOWNLOADER
DEBUGGER
DVDD
45
P0.1/AD1
24
12-BIT
VOLTAGE
OUTPUT DAC
POWER SUPPLY
MONITOR
2 DATA POINTERS
11-BIT STACK POINTER
AGND
SDATA/MOSI
DAC0
WATCHDOG
TIMER
BUF
AVDD
P2.0/A8/A16
12-BIT
VOLTAGE
OUTPUT DAC
256 BYTES
USER RAM
8052
POR
P2.1/A9/A17
16-BIT
PWM
4 kBYTES DATA
FLASH/EE
ASYNCHRONOUS
SERIAL PORT
(UART)
XTAL2
XTAL1
16-BIT
- DAC
62 kBYTES PROGRAM
FLASH/EE INCLUDING
USER DOWNLOAD MODE
CREF
46
P0.2/AD2
47
23
DGND
15
P1.6/ADC6
P.7/ADC7
DAC
CONTROL
P3.4/T0/PWMC/PWM0/EXTCLK
13
14
21
22
P1.4/ADC4
P1.5/ADC5/SS
P3.3/INT1/MISO/PWM1
DVDD
12
20
P2.2/A10/A18
DAC1
P3.2/INT0
P2.3/A11/A19
32
31
30
29
19
33
11
ADC7
VREF
DVDD
DAC0
PWM
CONTROL
BAND GAP
REFERENCE
DGND
...
ADC6
TEMP
SENSOR
38
37
36
PLL
OSC
XTAL2
MUX
P2.4/A12/A20
DGND
10
XTAL1
ADC1
...
P2.5/A13/A21
39
VREF
ADC
CONTROL
AND
CALIBRATION
12-BIT
ADC
T/H
P2.6/PWM0/A14/A22
40
35
34
ADuC832
ADC0
48
TOP VIEW
(Not to Scale)
P3.7/RD
SCLOCK
P3.6/WR
P3.5/T1/CONVST
P3.4/T0/PWMC/PWM0/EXTCLK
DGND
P3.2/INT0
P3.3/INT1/MISO/PWM1
DVDD
P3.0/RxD
P3.1/TxD
P1.7/ADC7
RESET
14 15 16 17 18 19 20 21 22 23 24 25 26
DGND
P0.3/AD3
7
8
AGND
CREF
27 SDATA/MOSI
49
P3.1/TxD
28 P2.0/A8/A16
50
30 P2.2/A10/A18
P1.5/ADC5/SS 12
P1.6/ADC6 13
P0.4/AD4
DVDD
AGND
AGND
31 P2.3/A11/A19
29 P2.1/A9/A17
51
32 XTAL1
P1.4/ADC4 11
P0.5/AD5
AVDD
AVDD
P2.7/PWM1/A15/A23
42
41
PIN 1
IDENTIFIER
18
TOP VIEW
(Not to Scale)
VREF 8
DAC0 9
DAC1 10
52
34 DVDD
33 XTAL2
P0.6/AD6
P1.3/ADC3
35 DGND
AGND 6
CREF 7
53
1
2
17
36 P2.4/A12/A20
P1.1/ADC1/T2EX
P1.2/ADC2
RESET
P3.0/RxD
37 P2.5/A13/A21
54
P1.0/ADC0/T2
38 P2.6/PWM0/A14/A22
P1.2/ADC2 3
P1.3/ADC3 4
AVDD 5
P0.7/AD7
39 P2.7/PWM1/A15/A23
PIN 1
IDENTIFIER
16
P1.0/ADC0/T2 1
P1.1/ADC1/T2EX 2
56
52 51 50 49 48 47 46 45 44 43 42 41 40
55
PSEN
EA
P0.0/AD0
ALE
P0.1/AD1
P0.3/AD3
P0.2/AD2
DVDD
DGND
P0.5/AD5
P0.4/AD4
P0.7/AD7
P0.6/AD6
PIN CONFIGURATION
Figure 1. ADuC832 Block Diagram (Shaded Areas are Features Not Present on the ADuC812)
REV. 0
ADuC832
PIN FUNCTION DESCRIPTIONS
Mnemonic
Type Function
DVDD
AVDD
CREF
VREF
P
P
I/O
I/O
AGND
P1.0P1.7
G
I
ADC0ADC7
T2
I
I
T2EX
SS
SDATA
SCLOCK
MOSI
MISO
DAC0
DAC1
RESET
P3.0P3.7
I
I/O
I/O
I/O
I/O
O
O
I
I/O
PWMC
PWM0
PWM1
RxD
TxD
INT0
I
O
O
I/O
O
I
INT1
T0
T1
CONVST
I
I
I
EXTCLK
WR
RD
XTAL2
XTAL1
DGND
P2.0P2.7
(A8A15)
(A16A23)
I
O
O
O
I
G
I/O
REV. 0
ADuC832
PIN FUNCTION DESCRIPTIONS (continued)
Mnemonic
Type Function
PSEN
ALE
EA
P0.7P0.0
(A0A7)
I/O
Program Store Enable, Logic Output. This output is a control signal that enables the external program
memory to the bus during external fetch operations. It is active every six oscillator periods except during
external data memory accesses. This pin remains high during internal program execution. PSEN can also be
used to enable serial download mode when pulled low through a resistor on power-up or RESET.
Address Latch Enable, Logic Output. This output is used to latch the low byte (and page byte for 24-bit
address space accesses) of the address into external memory during normal operation. It is activated every
six oscillator periods except during an external data memory access.
External Access Enable, Logic Input. When held high, this input enables the device to fetch code from
internal program memory locations 0000H to 1FFFH. When held low, this input enables the device to fetch
all instructions from external program memory. This pin should not be left floating.
Port 0 is an 8-Bit Open-Drain Bidirectional I/O Port. Port 0 pins that have 1s written to them float and in
that state can be used as high impedance inputs. Port 0 is also the multiplexed low order address and data
bus during accesses to external program or data memory. In this application it uses strong internal pull-ups
when emitting 1s.
TERMINOLOGY
ADC SPECIFICATIONS
Integral Nonlinearity
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
DAC SPECIFICATIONS
Relative Accuracy
Offset Error
Gain Error
This is the deviation of the last code transition from the ideal
AIN voltage (Full Scale 1.5 LSB) after the offset error has
been adjusted out.
10
REV. 0
1.2
1.0
AVDD/DVDD = 5V
AVDD / DVDD = 5V
fS = 152kHz
0.8
0.4
0.6
WCPINL LSBs
0.2
0
0.2
0.4
0.6
0.2
WCP INL
0.4
0
0.2
0.2
0
WCN INL
0.2
0.6
WCNINL LSBs
0.8
0.4
LSBs
0.6
fS = 152kHz
1.0
0.4
0.4
0.8
0.6
0.6
1.0
0
511
1023
1535
2047 2559
ADC CODES
3071
3583
0.5
4095
5.0
1.0
0.8
AVDD/DVDD = 3V
fS = 152kHz
0.8
1.0
1.5
2.0
2.5
EXTERNAL REFERENCE V
0.8
AVDD/DVDD = 3V
fS = 152kHz
0.6
0.6
0.6
0.4
WCP INL
0.4
LSBs
0.2
0
0.2
0.2
0.2
0.2
0.2
WCNINL LSBs
WCPINL LSBs
0.4
0.4
WCN INL
0.4
0.4
0.6
0.6
0.8
1.0
0.8
0
511
1023
1535
2047
2559
ADC CODES
3071
3583
4095
0.8
0.5
REV. 0
0.6
1.5
2.5
1.0
2.0
EXTERNAL REFERENCE V
3.0
11
ADuC832
0.7
0.7
1.0
AV DD /DVDD = 3V
AV DD /DVDD = 5V
fS = 152kHz
0.8
fS = 152kHz
0.5
0.6
WCPDNL LSBs
0.2
0
0.2
0.4
0.3
0.3
0.1
0.1
0.1
0.1
WCN DNL
0.3
0.3
0.5
0.5
WCNDNL LSBs
WCP DNL
0.4
LSBs
0.5
0.6
0.8
0.7
0.7
1.0
0
511
1023
1535
2047
2559
ADC CODES
3071
3583
0.5
4095
1.0
1.5
2.0
2.5
EXTERNAL REFERENCE V
3.0
10000
1.0
AV DD /DVDD = 3V
fS = 152kHz
0.8
8000
0.6
OCCURRENCE
0.4
LSBs
0.2
0
0.2
6000
4000
0.4
0.6
2000
0.8
1.0
0
511
1023
1535
2047
2559
ADC CODES
3071
3583
4095
817
819
CODE
820
821
0.6
818
10000
0.6
AVDD / DVDD = 5V
fS = 152kHz
9000
0.4
0.4
WCP DNL
0.2
0.2
0.2
7000
OCCURRENCE
0.2
WCNDNL LSBs
WCPDNL LSBs
8000
6000
5000
4000
3000
WCN DNL
0.4
0.4
0.6
0.6
2000
1000
0.5
1.0
1.5
2.0
2.5
EXTERNAL REFERENCE V
5.0
817
818
819
CODE
820
821
12
REV. 0
ADuC832
20
80
80
70
60
dBs
75
SNR
SNR dBs
40
fS = 152kHz
75
80
100
THD
65
85
60
90
55
95
THD dBs
0
20
70
AV DD /DVDD = 3V
AVDD / DVDD = 5V
fS = 152kHz
fIN = 9.910kHz
SNR = 71.3dB
THD = 88.0dB
ENOB = 11.6
120
140
160
100
50
0
10
20
30
40
50
60
70
0.5
FREQUENCY kHz
80
AVDD / DVDD = 3V
fS = 149.79kHz
fIN = 9.910kHz
SNR = 71.0dB
THD = 83.0dB
ENOB = 11.5
0
20
AVDD / DVDD = 5V
78
76
74
SNR dBs
40
60
80
100
72
70
68
66
120
64
140
62
60
65.476 92.262
160
0
10
20
30
40
50
60
70
119.05
FREQUENCY kHz
172.62
199.41
226.19
0.80
70
80
AVDD / DVDD = 5V
fS = 152kHz
75
145.83
FREQUENCY kHz
0.75
75
SNR
60
90
55
95
VOLTAGE V
THD
THD dBs
85
65
AVDD / DVDD = 3V
SLOPE = 2mV/C
0.70
80
70
SNR dBs
3.0
20
dBs
1.0
2.0
1.5
2.5
EXTERNAL REFERENCE V
0.65
0.60
0.55
0.50
0.45
0.40
100
50
0.5
1.0
1.5
2.0
2.5
EXTERNAL REFERENCE V
40
5.0
REV. 0
20
25
0
TEMPERATURE C
50
85
13
ADuC832
MEMORY ORGANIZATION
7FH
GENERAL-PURPOSE
AREA
30H
2FH
BANKS
BIT-ADDRESSABLE
(BIT ADDRESSES)
SELECTED
VIA
20H
BITS IN PSW
1FH
11
18H
If the user applies power or resets the device while the EA pin is
pulled low, the part will execute code from the external program
space; otherwise the part defaults to code execution from its
internal 62 kBytes of Flash/EE program memory. Unlike the
ADuC812, where code execution can overflow from the internal
code space to external code space once the PC becomes greater
than 1FFFH, the ADuC832 does not support the rollover from
F7FFH in internal code space to F800H in external code space.
Instead the 2048 bytes between F800H and FFFFH will appear
as NOP instructions to user code.
This internal code space can be downloaded via the UART
serial port while the device is in-circuit. 56 kBytes of the program
memory can be reprogrammed during runtime; thus the code
space can be upgraded in the field using a user defined protocol
or it can be used as a data memory. This will be discussed in
more detail in the Flash/EE Memory section.
17H
10
10H
0FH
01
08H
07H
00
RESET VALUE OF
STACK POINTER
00H
General-Purpose RAM
07FFH
UPPER 1792
BYTES OF
ON-CHIP XRAM
(DATA + STACK
FOR EXSP = 1,
DATA ONLY
FOR EXSP = 0)
CFG832.7 = 0
CFG832.7 = 1
100H
FFH
14
00H
256 BYTES OF
ON-CHIP DATA
RAM
(DATA +
STACK)
LOWER 256
BYTES OF
ON-CHIP XRAM
(DATA ONLY)
00H
REV. 0
ADuC832
External Data Memory (External XRAM)
4-kBYTE
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE DATA
MEMORY
62-kBYTE
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE PROGRAM
MEMORY
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
Internal XRAM
2304 BYTES
RAM
8-CHANNEL
12-BIT ADC
OTHER ON-CHIP
PERIPHERALS
TEMPERATURE
SENSOR
2 12-BIT DACs
SERIAL I/O
WDT
PSM
TIC
PWM
FFFFFFH
FFFFFFH
EXTERNAL
DATA
MEMORY
SPACE
(24-BIT
ADDRESS
SPACE)
EXTERNAL
DATA
MEMORY
SPACE
(24-BIT
ADDRESS
SPACE)
2 kBYTES
ON-CHIP
XRAM
000000H
CFG832.0 = 0
B SFR (B)
The B register is used with the ACC for multiplication and division operations. For other instructions, it can be treated as a
general-purpose scratch pad register.
Stack Pointer (SP and SPH)
000800H
0007FFH
000000H
CFG832.0 = 1
The SFR space is mapped into the upper 128 bytes of internal
data memory space and accessed by direct addressing only. It
provides an interface between the CPU and all on chip peripherals. A block diagram showing the programming model of the
ADuC832 via the SFR area is shown in Figure 5.
All registers, except the Program Counter (PC) and the four
general-purpose register banks, reside in the SFR area. The SFR
registers include control, configuration, and data registers that
provide an interface between the CPU and all on-chip peripherals.
REV. 0
15
ADuC832
Data Pointer (DPTR)
The PSW SFR contains several bits reflecting the current status
of the CPU as detailed in Table I.
SFR Address
Power-On Default Value
Bit Addressable
D0H
00H
Yes
Bit
Name
Description
7
6
5
4
3
CY
AC
F0
RS1
RS0
2
1
0
OV
F1
P
Carry Flag
Auxiliary Carry Flag
General-Purpose Flag
Register Bank Select Bits
RS1
RS0
Selected Bank
0
0
0
0
1
1
1
0
2
1
1
3
Overflow Flag
General-Purpose Flag
Parity Bit
SFR Address
Power-On Default Value
Bit Addressable
87H
00H
No
Bit
Name
Description
7
6
5
4
3
2
1
0
SMOD
SERIPD
INT0PD
ALEOFF
GF1
GF0
PD
IDL
16
REV. 0
ADuC832
the figure below (NOT USED). Unoccupied locations in the
SFR address space are not implemented i.e., no register exists
at this location. If an unoccupied location is read, an unspecified
value is returned. SFR locations reserved for on-chip testing are
shown lighter shaded below (RESERVED) and should not be
accessed by user software. Sixteen of the SFR locations are also
bit addressable and denoted by '1' in the figure below, i.e., the
bit addressable SFRs are those whose address ends in 0H or 8H.
All registers except the program counter and the four generalpurpose register banks reside in the special function register
(SFR) area. The SFR registers include control, configuration,
and data registers that provide an interface between the CPU
and other on-chip peripherals.
Figure 6 shows a full SFR memory map and SFR contents on
Reset. Unoccupied SFR locations are shown dark-shaded in
ISPI
WCOL
SPE
SPIM
CPOL
CPHA
SPR1
SPR0
FFH
0 FEH
0 FDH
0 FCH
0 FBH
0 FAH
1 F9H
0 F8H
F7H
0 F6H
0 F5H
0 F4H
0 F3H
0 F2H
0 F1H
0 F0H
EFH
0 EEH
E7H
0 E6H
ADCI
DFH
0 CEH
PSI
BFH
RD
B7H
EA
AFH
A7H
0 CDH
1 A6H
SM0
SM1
PT2
0 BDH
T1
1 B5H
EADC
0 AEH
0 DCH
0 EBH
ET2
0 ADH
1 A5H
SM2
PS
0 BCH
T0
1 B4H
ES
0 ACH
1 A4H
REN
0 E2H
CS3
0 DBH
CS2
0 DAH
RS0
0 D3H
OV
0 D2H
EXEN2
0 CBH
PRE0
0 C4H
0 EAH
0 E3H
TCLK
0 CCH
I2CRS
I2CM
RS1
0 D4H
PRE1
0 C5H
WR
1 B6H
0 E4H
RCLK
PADC
0 BEH
0 ECH
F0
0 D5H
PRE2
0 C6H
MDI
CCONV SCONV
0 DDH
EXF2
PRE3
C7H
0 E5H
AC
0 D6H
TF2
CFH
0 EDH
DMA
0 DEH
CY
D7H
MCO
MDE
MDO
TR2
0 CAH
WDIR
1 C3H
WDS
0 C2H
PT1
PX1
0 BBH
0 BAH
INT1
1 B3H
INT0
1 B2H
ET1
0 ABH
EX1
0 AAH
1 A3H
1 A2H
TB8
RB8
I2CTX
0 E9H
0 E1H
WDE
0 C1H
PT0
0 B9H
TxD
1 B1H
ET0
0 A9H
1 A1H
TI
0 9EH
0 9DH
0 9CH
0 9BH
0 9AH
0 99H
97H
1 96H
1 95H
1 94H
1 93H
1 92H
1 91H
TF0
TR0
IE1
IT1
P
0 D0H
CAP2
0 C8H
WDWR
0 C0H
PX0
0 B8H
RxD
1 B0H
EX0
0 A8H
1 A0H
RI
0
T2
1
IT0
8FH
0 8EH
0 8DH
0 8CH
0 8BH
0 8AH
0 89H
0 88H
87H
1 86H
1 85H
1 84H
1 83H
1 82H
1 81H
1 80H
04H
F0H
00H
I2CCON1
BITS
E8H
DAC0H
00H
FAH
00H
DAC1L
FBH
00H
DAC1H
FCH
00H
F1H
00H
RESERVED
F2H
20H
RESERVED
F3H
00H
RESERVED
F4H
00H
RESERVED
IE0
89H
E0H
RESERVED
RESERVED
BITS
D8H
00H
PSW1
BITS
D0H
C8H
C0H
RESERVED
B8H
RESERVED
RESERVED
00H
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
B0H
ECON
B9H
BITS
A8H
PWM0L
A0H
FFH
A9H
BITS
98H
00H
A1H
P11, 2
BITS
90H
88H
80H
00H
RESERVED
TL2
CCH
00H
PWM0H
PWM1L
00H
RESERVED
EDATA1
BCH
RESERVED
00H
RESERVED
TH2
CDH
00H
RESERVED
RESERVED
EDARL
EDATA2
BDH
00H
00H A3H
00H 9BH
NOT USED
00H
I2CADD
BEH
00H
NOT USED
00H
RESERVED
RESERVED
MIN
HOUR
A4H
00H
A5H
00H
T3FD
EDARH
C7H
A6H
00H
EDATA4
BFH
00H
SPH
00H
CFG832
00H AFH
INTVAL
00H
DPCON
00H A7H
00H
T3CON
NOT USED
NOT USED
9DH
NOT USED
53H
RESERVED
B7H
PWMCON
55H
NOT USED
00H
EDATA3
AEH
SEC
PLLCON
00H
PWM1H
00H B4H
RESERVED
HTHSEC
9AH
PSMCON
D7H
NOT USED
00H B3H
I2CDAT
TMOD
89H
FFH
TL0
00H
SP
81H
TCON
IT0
0 88H
RESERVED
00H
C6H
RESERVED
00H A2H
NOT USED
P01
BITS
00H
00H 9EH
NOT USED
00H
NOT USED
NOT USED
RESERVED
RESERVED
FFH
TCON1
BITS
CBH
RESERVED
RESERVED
SBUF
99H
RCAP2H
DMAP
D4H
A0H
TIMECON
SCON1
00H
2XH
00H B2H
IEIP2
P21
00H
DMAH
D3H
00H
FFH B1H
00H
00H
RCAP2L
C2H
IE1
BITS
00H
ADCCON1
DFH DEH
00H
CHIPID
RESERVED
P31
BITS
SPIDAT
F7H
RESERVED
DMAL
CAH
10H
00H
DAH
D2H
IP1
BITS
00H
00H
WDCON1
BITS
D9H
00H
T2CON1
BITS
RESERVED
00H
88H
DEFAULT VALUE
8AH
00H
TL1
8BH
DPL
07H
82H
00H
00H
DPH
83H
00H
TH0
8CH
00H
DPP
84H
00H
00H
MNEMONIC
DEFAULT VALUE
SFR ADDRESS
NOTES
1SFRs WHOSE ADDRESS ENDS IN 0H OR 8H ARE BIT ADDRESSABLE.
2THE PRIMARY FUNCTION OF PORT1 IS AS AN ANALOG INPUT PORT;
3CALIBRATION
REV. 0
F5H
RESERVED
04H
EFH
DACCON
FDH
00H
ACC1
BITS
DAC0L
F9H
B1
BITS
1 90H
IE0
F8H
CS0
0 98H
T2EX
TR1
0 D8H
CNT2
0 C9H
0 E0H
FI
0 D1H
9FH
TF1
0 E8H
CS1
0 D9H
I2CI
SPICON1
BITS
17
TH1
8DH
00H
RESERVED
RESERVED
PCON
87H
00H
ADuC832
ADC CIRCUIT INFORMATION
General Overview
The analog input range for the ADC is 0 V to VREF. For this
range, the designed code transitions occur midway between
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs,
5/2 LSBs . . . FS 3/2 LSBs). The output coding is straight
binary with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV when
VREF = 2.5 V. The ideal input/output transfer characteristic for
the 0 to VREF range is shown in Figure 7.
OUTPUT
CODE
111...111
111...110
111...101
111...100
1LSB =
FS
4096
000...011
000...010
000...001
000...000
0V 1LSB
VOLTAGE INPUT
+FS
1LSB
Once configured via the ADCCON 1-3 SFRs, the ADC will convert the analog input and provide an ADC 12-bit result word in the
ADCDATAH/L SFRs. The top four bits of the ADCDATAH
SFR will be written with the channel selection bits so as to
identify the channel result. The format of the ADC 12-bit result
word is shown in Figure 8.
ADCDATAH SFR
CHID
TOP 4 BITS
HIGH 4 BITS OF
ADC RESULT WORD
ADCDATAL SFR
LOW 8 BITS OF THE
ADC RESULT WORD
18
REV. 0
ADuC832
ADCCON1 (ADC Control SFR #1)
Name
Description
ADCCON1.7
MD1
ADCCON1.6
EXT_REF
ADCCON1.5
ADCCON1.4
CK1
CK0
The Mode bit selects the active operating mode of the ADC.
Set by the user to power up the ADC.
Cleared by the user to power down the ADC.
Set by the user to select an external reference.
Cleared by the user to use the internal reference.
The ADC clock divide bits (CK1, CK0) select the divide ratio for the PLL master clock used to generate the
ADC clock. To ensure correct ADC operation, the divider ratio must be chosen to reduce the ADC clock
to 4.5 MHz and below. A typical ADC conversion will require 17 ADC clocks.
The divider ratio is selected as follows:
CK1 CK0 MCLK Divider
0
0
8
0
1
4
1
0
16
1
1
32
ADCCON1.3
ADCCON1.2
AQ1
AQ0
The ADC acquisition select bits (AQ1, AQ0) select the time provided for the input track-and-hold amplifier
to acquire the input signal. An acquisition of three or more ADC clocks is recommended; clocks are
selected as follows:
AQ1
0
0
1
1
ADCCON1.1 T2C
ADCCON1.0 EXC
REV. 0
AQ0
0
1
0
1
#ADC Clks
1
2
3
4
The Timer 2 conversion bit (T2C) is set by the user to enable the Timer 2 overflow bit be used as
the ADC convert start trigger input.
The external trigger enable bit (EXC) is set by the user to allow the external Pin P3.5 (CONVST) to
be used as the active low convert start input. This input should be an active low pulse (minimum
pulsewidth >100 ns) at the required sample rate.
19
ADuC832
ADCCON2 (ADC Control SFR #2)
D8H
00H
YES
Name
ADCCON2.7 ADCI
ADCCON2.6 DMA
ADCCON2.5 CCONV
ADCCON2.4 SCONV
ADCCON2.3
ADCCON2.2
ADCCON2.1
ADCCON2.0
CS3
CS2
CS1
CS0
Description
The ADC interrupt bit (ADCI) is set by hardware at the end of a single ADC conversion cycle or at
the end of a DMA block conversion. ADCI is cleared by hardware when the PC vectors to the ADC
Interrupt Service Routine. Otherwise, the ADCI bit should be cleared by user code.
The DMA mode enable bit (DMA) is set by the user to enable a preconfigured ADC DMA mode operation. A more detailed description of this mode is given in the ADC DMA Mode section. The DMA bit is
automatically set to 0 at the end of a DMA cycle. Setting this bit causes the ALE output to cease, it will
start again when DMA is started and will operate correctly after DMA is complete.
The continuous conversion bit (CCONV) is set by the user to initiate the ADC into a continuous mode of
conversion. In this mode, the ADC starts converting based on the timing and channel configuration
already set up in the ADCCON SFRs; the ADC automatically starts another conversion once a previous conversion has completed.
The single conversion bit (SCONV) is set to initiate a single conversion cycle. The SCONV bit is
automatically reset to 0 on completion of the single conversion cycle.
The channel selection bits (CS30) allow the user to program the ADC channel selection under
software control. When a conversion is initiated, the channel converted will be that pointed to by
these channel selection bits. In DMA mode, the channel selection is derived from the channel ID
written to the external memory.
CS3 CS2 CS1 CS0 CH#
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
Temp Monitor
Requires minimum of 1 s to acquire
1
0
0
1
DAC0
Only use with Internal DAC o/p buffer on
1
0
1
0
DAC1
Only use with Internal DAC o/p buffer on
1
0
1
1
AGND
1
1
0
0
VREF
1
1
1
1
DMA STOP
Place in XRAM location to finish DMA sequence, see
the section ADC DMA Mode.
All other combinations reserved
20
REV. 0
ADuC832
ADCCON3 (ADC Control SFR #3)
The ADCCON3 register controls the operation of various calibration modes as well as giving an indication of ADC busy status.
SFR Address:
SFR Power-On Default Value:
Bit Addressable:
F5H
00H
NO
Bit
Name
ADCCON3.7 BUSY
ADCCON3.6 GNCLD
ADCCON3.5 AVGS1
ADCCON3.4 AVGS0
ADCCON3.3 RSVD
ADCCON3.2 RSVD
ADCCON3.1 TYPICAL
ADCCON3.0 SCAL
REV. 0
Description
The ADC Busy Status Bit (BUSY) is a read-only status bit that is set during a valid ADC conversion or
calibration cycle. Busy is automatically cleared by the core at the end of conversion or calibration.
Gain Calibration Disable Bit.
Set to 0 to Enable Gain Calibration.
Set to 1 to Disable Gain Calibration.
Number of Averages Selection Bits.
This bit selects the number of ADC readings averaged during a calibration cycle.
AVGS1 AVGS0
Number of Averages
0
0
15
0
1
1
1
0
31
1
1
63
Reserved. This bit should always be written as 0.
This bit should always be written as 1 by the user when performing calibration.
Calibration Type Select Bit.
This bit selects between Offset (zero-scale) and Gain (full-scale) calibration.
Set to 0 for Offset Calibration.
Set to 1 for Gain Calibration.
Start Calibration Cycle Bit.
When set, this bit starts the selected calibration cycle. It is automatically cleared when the calibration
cycle is completed.
21
ADuC832
Driving the A/D Converter
The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. Figure 9 shows
the equivalent circuit of the analog input section. Each ADC
conversion is divided into two distinct phases as defined by the
position of the switches in Figure 9. During the sampling phase
(with SW1 and SW2 in the track position) a charge proportional to the voltage on the analog input is developed across the
input sampling capacitor. During the conversion phase (with
both switches in the hold position) the capacitor DAC is
adjusted via internal SAR logic until the voltage on node A is
zero, indicating that the sampled charge on the input capacitor
is balanced out by the charge being output by the capacitor DAC.
The digital value finally contained in the SAR is then latched
out as the result of the ADC conversion. Control of the SAR,
and timing of acquisition and sampling modes, is handled
automatically by built-in ADC control logic. Acquisition and
conversion times are also fully configurable under user control.
ADuC832
VREF
AGND
DAC1
DAC0
TEMPERATURE MONITOR
AIN7
CAPACITOR
DAC
200
AIN0
TRACK
COMPARATOR
32pF
200
NODE A
sw2
TRACK
10
AIN0
0.1F
Source
Impedance
61
610
sw1
HOLD
ADuC832
HOLD
AGND
Error from 10 A
Leakage Current
610 V = 1 LSB
6.1 mV = 10 LSB
Op Amp Model
Characteristics
OP281/OP481
OP191/OP291/OP491
OP196/OP296/OP496
OP183/OP283
OP162/OP262/OP462
AD820/AD822/AD824
AD823
Micropower
I/O Good up to VDD, Low Cost
I/O to VDD, Micropower, Low Cost
High Gain-Bandwidth Product
High GBP, Micro Package
FET Input, Low Cost
FET Input, High GBP
22
REV. 0
ADuC832
ground, no amplifier can deliver signals all the way to ground
when powered by a single supply. Therefore, if a negative
supply is available, you might consider using it to power the
front end amplifiers. If you do, however, be sure to include the
Schottky diodes shown in Figure 10 (or at least the lower of
the two diodes) to protect the analog input from undervoltage
conditions. To summarize this section, use the circuit of
Figure 10 to drive the analog input pins of the ADuC832.
ADuC832
VDD
EXTERNAL
VOLTAGE
REFERENCE
2.5V
BAND GAP
REFERENCE
51
ADuC832
BUFFER
0 = INTERNAL
51
2.5V
BAND GAP
REFERENCE
VREF
1 = EXTERNAL
0.1F
ADCCON1.6
VREF
BUFFER
CREF
0.1F
0.1F
CREF
BUFFER
0.1F
To maintain compatibility with the ADuC812, the external reference may also be connected to the VREF pin as shown in Figure 13,
to overdrive the internal reference. Note this introduces a gain
error for the ADC that has to be calibrated out; thus the previous
method is the recommended one for most users. For this method
to work, ADCCON1.6 should be configured to use the internal
reference. The external reference will then overdrive this.
ADuC832
51
VDD
EXTERNAL
VOLTAGE
REFERENCE
2.5V
BAND GAP
REFERENCE
BUFFER
VREF
8
0.1F
CREF
0.1F
REV. 0
23
ADuC832
3. The external memory must be preconfigured. This consists of
writing the required ADC channel IDs into the top four bits
of every second memory location in the external SRAM, starting
at the first address specified by the DMA address pointer. As
the ADC DMA mode operates independent from the ADuC832
core, it is necessary to provide it with a stop command. This
is done by duplicating the last channel ID to be converted
followed by 1111 into the next channel selection field. A
typical preconfiguration of external memory is as follows:
STOP COMMAND
00000AH
000000H
a.
STOP COMMAND
24
000000H
NO CONVERSION
RESULT WRITTEN HERE
CONVERSION RESULT
FOR ADC CH#3
CONVERSION RESULT
FOR TEMP SENSOR
CONVERSION RESULT
FOR ADC CH#5
CONVERSION RESULT
FOR ADC CH#2
REV. 0
ADuC832
The DMA logic operates from the ADC clock and uses pipelining
to perform the ADC conversions and access the external memory
at the same time. The time it takes to perform one ADC conversion is called a DMA cycle. The actions performed by the logic
during a typical DMA cycle are shown in the following diagram.
READ CHANNEL ID
TO BE CONVERTED DURING
NEXT DMA CYCLE
DMA CYCLE
From the previous diagram, it can be seen that during one DMA
cycle, the following actions are performed by the DMA logic:
1. An ADC conversion is performed on the channel whose ID
was read during the previous cycle.
2. The 12-bit result and the channel ID of the conversion performed in the previous cycle is written to the external memory.
3. The ID of the next channel to be converted is read from
external memory.
For the previous example, the complete flow of events is shown
in Figure 16. Because the DMA logic uses pipelining, it takes
three cycles before the first correct result is written out.
Micro Operation during ADC DMA Mode
The only case in which the MCU will be able to access XRAM
during DMA is when the internal XRAM is enabled and the
section of RAM to which the DMA ADC results are being written
to lies in an external XRAM. Then the MCU will be able to
access the internal XRAM only. This is also the case for use of
the extended stack pointer.
The MicroConverter core can be configured with an interrupt to
be triggered by the DMA controller when it has finished filling
the requested block of RAM with ADC results, allowing the
service routine for this interrupt to postprocess data without any
real-time timing constraints.
System calibration can be initiated to compensate for both internal and external system errors. To perform system calibration
using an external reference, tie system ground and reference to
any two of the six selectable inputs. Enable external reference
mode (ADCCON1.6). Select the channel connected to AGND
via CS3CS0 and perform system offset calibration. Select the
channel connected to VREF via CS3CS0 and perform system
gain calibration.
The ADC should be configured to use settings for an ADCCLK
of divide by 16 and 4 acquisition clocks.
REV. 0
25
ADuC832
To calibrate system gain:
Connect system VREF to an ADC channel input (1).
MOV ADCCON2,#01H
MOV ADCCON3,#27H
26
;move ADCCON3 to A
;If Bit 7 is set jump to
WAIT else continue
REV. 0
ADuC832
NONVOLATILE FLASH/EE MEMORY
Flash/EE Memory Overview
A single Flash/EE
Memory
Endurance Cycle
EPROM
TECHNOLOGY
EEPROM
TECHNOLOGY
SPACE EFFICIENT/
DENSITY
IN-CIRCUIT
REPROGRAMMABLE
FLASH/EE MEMORY
TECHNOLOGY
250
ADI SPECIFICATION
100 YEARS MIN.
AT TJ = 55C
150
100
50
0
40
50
60
70
90
80
TJ JUNCTION TEMPERATURE C
100
110
REV. 0
200
27
ADuC832
after Reset. If using a bootloader, this option is recommended
to ensure that the bootloader always executes correct code
after reset.
62 kBYTES
OF USER
CODE
MEMORY
The parallel programming mode is fully compatible with conventional third party Flash or EEPROM device programmers.
In this mode, Ports P0, P1, and P2 operate as the external data
and address bus interface, ALE operates as the Write Enable
strobe, and Port P3 is used as a general configuration port that
configures the device for various program and erase operations
during parallel programming. The high voltage (12 V) supply
required for Flash programming is generated using on-chip
charge pumps to supply the high voltage program lines.
6 kBYTE
E000H
DFFFH
56 kBYTE
0000H
This mode locks the code memory, disabling parallel programming of the program memory. However, reading the memory in
parallel mode and reading the memory via a MOVC command
from external memory is still allowed. This mode is deactivated
by initiating a code-erase command in serial download or parallel
programming modes.
Secure Mode
FFFFH
2 kBYTE
F800H
F7FFH
28
REV. 0
ADuC832
BYTE 3
(0FFEH)
BYTE 4
(0FFFH)
BYTE 1
(0FF8H)
BYTE 3
(0FFAH)
BYTE 4
(0FFBH)
03H
BYTE 1
(000CH)
BYTE 2
(000DH)
BYTE 3
(000EH)
BYTE 4
(000FH)
02H
BYTE 1
(0008H)
BYTE 2
(0009H)
BYTE 3
(000AH)
BYTE 4
(000BH)
01H
BYTE 1
(0004H)
BYTE 2
(0005H)
BYTE 3
(0006H)
BYTE 4
(0007H)
00H
BYTE 1
(0000H)
BYTE 2
(0001H)
BYTE 3
(0002H)
BYTE 4
(0003H)
EDATA4 SFR
3FEH
BYTE 2
(0FFDH)
BYTE 2
(0FF9H)
EDATA3 SFR
BYTE 1
(0FFCH)
EDATA2 SFR
BYTE
ADDRESSES
ARE GIVEN IN
BRACKETS
3FFH
PAGE ADDRESS
(EADRH/L)
EDATA1 SFR
ECON VALUE
COMMAND DESCRIPTION
(NORMAL MODE) (Power-On Default)
01H
READ
Results in four bytes in the Flash/EE data memory, addressed Not Implemented. Use the MOVC instruction.
by the page address EADRH/L, being read into EDATA 1 to 4.
02H
WRITE
03H
Reserved Command
Reserved Command
04H
VERIFY
05H
ERASE PAGE
06H
ERASE ALL
81H
READBYTE
82H
WRITEBYTE
0FH
EXULOAD
F0H
ULOAD
REV. 0
29
COMMAND DESCRIPTION
(ULOAD MODE)
ADuC832
Example: Programming the Flash/EE Data Memory
Typical program and erase times for the ADuC832 are as follows:
NORMAL MODE (operating on Flash/EE data memory)
READPAGE (4 bytes)
WRITEPAGE (4 bytes)
VERIFYPAGE (4 bytes)
ERASEPAGE (4 bytes)
ERASEALL (4 kBytes)
READBYTE (1 byte)
WRITEBYTE (1 byte)
The two address registers EADRH and EADRL hold the high
byte address and the low byte address of the page to be addressed.
The assembly language to set up the address may appear as:
MOV EADRH,#0
; Set Page Address Pointer
MOV EADRL,#03H
5 machine cycles
380 s
5 machine cycles
2 ms
2 ms
3 machine cycle
200 s
We must now write the four values to be written into the page
into the four SFRs EDATA14. Unfortunately, we do not know
three of them. Thus, we must read the current page and overwrite the second byte.
MOV ECON,#1
; Read Page into EDATA1-4
MOV EDATA2,#0F3H ; Overwrite byte 2
Step 3: Program Page
15 ms
2 ms
2 ms
200 s
30
REV. 0
ADuC832
ADuC832 Configuration SFR (CFG832)
SFR Address
Power-On Default Value
Bit Addressable
AFH
00H
No
Bit
Name
Description
EXSP
PWPO
DBUF
EXTCLK
3
2
1
0
RSVD
RSVD
RSVD
XRAMEN
Extended SP Enable .
When set to 1 by the user, the stack will roll over from SPH/SP = 00FFH to 0100H.
When set to 0 by the user, the stack will roll over from SP = FFH to SP = 00H.
PWM pin out selection
Set to 1 by the user = PWM output pins selected as P3.4 and P3.3.
Set to 0 by the user = PWM output pins selected as P2.6 and P2.7.
DAC Output Buffer
Set to 1 by the user = DAC. Output Buffer Bypassed.
Set to 0 by the user = DAC Output Buffer Enabled.
Set by the user to 1 to select an external clock input on P3.4.
Set by the user to 0 to use the internal PLL clock.
Reserved This bit should always contain 0.
Reserved This bit should always contain 0.
Reserved This bit should always contain 0.
XRAM Enable Bit
When set to 1 by the user, the internal XRAM will be mapped into the lower 2 kBytes of the external
address space.
When set to 0 by the user, the internal XRAM will not be accessible and the external data memory
will be mapped into the lower 2 kBytes of external data memory.
REV. 0
31
ADuC832
USER INTERFACE TO OTHER ON-CHIP ADuC832
PERIPHERALS
SFR Address
Power-On Default Value
Bit Addressable
FDH
04H
No
Bit
Name
Description
MODE
RNG1
RNG0
CLR1
CLR0
SYNC
PD1
PD0
The DAC MODE bit sets the overriding operating mode for both DACs.
Set to 1 = 8-Bit Mode (Write 8 Bits to DACxL SFR).
Set to 0 = 12-Bit Mode.
DAC1 Range Select Bit.
Set to 1 = DAC1 Range 0VDD.
Set to 0 = DAC1 Range 0VREF.
DAC0 Range Select Bit.
Set to 1 = DAC0 Range 0VDD.
Set to 0 = DAC0 Range 0VREF.
DAC1 Clear Bit.
Set to 0 = DAC1 Output Forced to 0 V.
Set to 1 = DAC1 Output Normal.
DAC0 Clear Bit.
Set to 0 = DAC1 Output Forced to 0 V.
Set to 1 = DAC1 Output Normal.
DAC0/1 Update Synchronization Bit.
When set to 1, the DAC outputs update as soon as DACxL SFRs are written. The user can
simultaneously update both DACs by first updating the DACxL/H SFRs while SYNC is 0. Both
DACs will then update simultaneously when the SYNC bit is set to 1.
DAC1 Power-Down Bit.
Set to 1 = Power-On DAC1.
Set to 0 = Power-Off DAC1.
DAC0 Power-Down Bit.
Set to 1 = Power-On DAC0.
Set to 0 = Power-Off DAC0.
DACxH/L
Function
SFR Address
FBH
FCH
The 12-bit DAC data should be written into DACxH/L right-justified such that DACxL contains the lower eight bits, and the lower
nibble of DACxH contains the upper four bits.
32
REV. 0
ADuC832
Using the DAC
VDD
VDD50mV
VDD100mV
ADuC832
100mV
R
OUTPUT
BUFFER
50mV
0mV
DAC0
FFFH
000H
OUTPUT VOLTAGE V
HIGH Z
DISABLE
(FROM MCU)
1
DAC LOADED WITH 0000H
0
5
10
SOURCE/SINK CURRENT mA
15
REV. 0
33
ADuC832
To drive significant loads with the DAC outputs, external buffering may be required (even with the internal buffer enabled), as
illustrated in Figure 25. A list of recommended op amps is in
Table VI.
OUTPUT VOLTAGE V
DAC0
ADuC832
DAC1
5
10
SOURCE/SINK CURRENT mA
15
34
REV. 0
ADuC832
ON-CHIP PLL
PLL clock, with the modulator rate being the same as the crystal oscillator frequency. The above choice of frequencies ensures
that the modulators and the core will be synchronous, regardless
of the core clock rate. The PLL control register is PLLCON.
PLLCON
SFR Address
Power-On Default Value
Bit Addressable
D7H
53H
No
Bit
Name
Description
OSC_PD
LOCK
5
4
3
------FINT
2
1
0
CD2
CD1
CD0
REV. 0
35
ADuC832
PULSEWIDTH MODULATOR (PWM)
fXTAL/15
CLOCK
SELECT
PROGRAMMABLE
DIVIDER
fXTAL
P2.6
COMPARE
MODE
PWM0H/L
P2.7
PWM1H/L
The PWM uses five SFRs: the control SFR (PWMCON) and
four data SFRs (PWM0H, PWM0L, PWM1H, and PWM1L).
PWMCON (as described below) controls the different modes of
operation of the PWM as well as the PWM clock frequency.
PWM0H/L and PWM1H/L are the data registers that determine the duty cycles of the PWM outputs. The output pins that
the PWM uses are determined by the CFG832 register, and can
be either P2.6 and P2.7 or P3.4 and P3.3. In this section of the
data sheet, it is assumed that P2.6 and P2.7 are selected as the
PWM outputs.
To use the PWM user software, first write to PWMCON to
select the PWM mode of operation and the PWM input clock.
Writing to PWMCON also resets the PWM counter. In any of
the 16-bit modes of operation (modes 1, 3, 4, 6), user software
should write to the PWM0L or PWM1L SFRs first. This value
is written to a hidden SFR. Writing to the PWM0H or PWM1H
SFRs updates both the PWMxH and the PWMxL SFRs but
does not change the outputs until the end of the PWM cycle in
progress. The values written to these 16-bit registers are then
used in the next PWM cycle.
PWMCON
SFR Address
Power-On Default Value
Bit Addressable
Bit
Name
Description
SNGL
Turns off PWM Output at P2.6 or P3.4 Leaving Port Pin Free for Digital I/O.
6
5
4
MD2
MD1
MD0
3
2
CDIV1
CDIV0
1
0
CSEL1
CSEL0
36
REV. 0
ADuC832
PWM1L
PWM COUNTER
PWM0L
PWM1H
PWM0H
In Mode 1, both the pulse length and the cycle time (period) are
programmable in user code, allowing the resolution of the PWM
to be variable.
PWM1H/L sets the period of the output waveform. Reducing
PWM1H/L reduces the resolution of the PWM output but
increases the maximum output rate of the PWM. (e.g., setting
PWM1H/L to 65536 gives a 16-bit PWM with a maximum
output rate of 266 Hz (16.777MHz/65536). Setting PWM1H/L
to 4096 gives a 12-bit PWM with a maximum output rate of
4096 Hz (16.777MHz/4096)).
PWM0H/L sets the duty cycle of the PWM output waveform, as
shown in Figure 27.
PWM1H/L
0
P2.6
P2.7
PWM0H/L
PWM COUNTER
P2.7
In this mode, both PWM outputs are synchronized, i.e., once the
PWM counter rolls over to 0, both PWM0 (P2.6) and PWM1
(P2.7) will go high.
65536
In Mode 2, the duty cycle of the PWM outputs and the resolution
of the PWM outputs are both programmable. The maximum
resolution of the PWM output is eight bits.
PWM COUNTER
PWM1H/L
PWM1L sets the period for both PWM outputs. Typically, this
will be set to 255 (FFH) to give an 8-bit PWM although it is possible to reduce this as necessary. A value of 100 could be loaded
here to give a percentage PWM (i.e., the PWM is accurate to 1%).
PWM0H/L
0
The outputs of the PWM at P2.6 and P2.7 are shown in Figure 28.
As can be seen, the output of PWM0 (P2.6) goes low when the
PWM counter equals PWM0L. The output of PWM1 (P2.7) goes
high when the PWM counter equals PWM1H and goes low
again when the PWM counter equals PWM0H. Setting PWM1H
to 0 ensures that both PWM outputs start simultaneously.
REV. 0
37
P2.6
P2.7
ADuC832
MODE 4: Dual NRZ 16-Bit - DAC
PWM1L
PWM COUNTERS
PWM1H
PWM0L
In this mode P2.6 and P2.7 are updated every PWM clock
(60 ns in the case of 16 MHz). Over any 65536 cycles (16-bit
PWM) PWM0 (P2.6) is high for PWM0H/L cycles and low for
(65536 PWM0H/L) cycles. Similarly PWM1 (P2.7) is high for
PWM1H/L cycles and low for (65536 PWM1H/L) cycles.
For example, if PWM1H was set to 4010H (slightly above one
quarter of FS) then typically P2.7 will be low for three clocks
and high for one clock (each clock is approximately 60 ns). Over
every 65536 clocks, the PWM will compensate for the fact that
the output should be slightly above one quarter of full scale by
having a high cycle followed by only two low cycles.
PWM0H/L = C000H
CARRY OUT AT P1.0
16-BIT
60s
16-BIT
16-BIT
16.777MHz
16-BIT
0
P2.6
P2.7
LATCH
16-BIT
PWM0H
0
PWM0H/L = C000H
60s
PWM1H/L = 4000H
0 1
16-BIT
0 1
16-BIT
16-BIT
4MHz
16-BIT
LATCH
16-BIT
In Mode 5, the duty cycle of the PWM outputs and the resolution
of the PWM outputs are individually programmable. The maximum resolution of the PWM output is eight bits. The output
resolution is set by the PWM1L and PWM1H SFRs for the
P2.6 and P2.7 outputs, respectively. PWM0L and PWM0H sets
the duty cycles of the PWM outputs at P2.6 and P2.7, respectively.
Both PWMs have same clock source and clock divider.
38
0 1
16-BIT
240s
PWM1H/L = 4000H
REV. 0
ADuC832
SERIAL PERIPHERAL INTERFACE
SFR Address
Power-On Default Value
Bit Addressable
F8H
O4H
Yes
The Slave Select (SS) input pin is shared with the ADC5 input.
In order to configure this pin as a digital input, the bit must be
cleared, e.g., CLR P1.5.
This line is active low. Data is only received or transmitted in
slave mode when the SS pin is low, allowing the ADuC832 to be
used in single master, multislave SPI configurations. If CPHA = 1
then the SS input may be permanently pulled low. With CPHA = 0,
the SS input must be driven low before the first bit in a byte
wide transmission or reception and return high again after the
last bit in that byte wide transmission or reception. In SPI slave
mode, the logic level on the external SS pin can be read via the
SPR0 bit in the SPICON SFR.
The following SFR registers are used to control the SPI interface.
Bit
Name
Description
ISPI
WCOL
SPE
SPIM
CPOL
CPHA
1
0
SPR1
SPR0
The CPOL and CPHA bits should both contain the same values for master and slave devices.
REV. 0
39
ADuC832
SPIDAT
Function
The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to
read data just received by the SPI interface.
F7H
00H
No
SFR Address
Power-On Default Value
Bit Addressable
Using the SPI Interface
In master mode, the SCLOCK pin is always an output and generates a burst of eight clocks whenever user code writes to the
SPIDAT register. The SCLOCK bit rate is determined by
SPR0 and SPR1 in SPICON. It should also be noted that the
SS pin is not used in master mode. If the ADuC832 needs to
assert the SS pin on an external slave device, a port digital output
pin should be used.
SCLOCK
(CPOL = 1)
SCLOCK
(CPOL = 0)
SS
SAMPLE INPUT
(CPHA = 1)
DATA OUTPUT
ISPI FLAG
SAMPLE INPUT
DATA OUTPUT
(CPHA = 0)
ISPI FLAG
40
REV. 0
ADuC832
I2C COMPATIBLE INTERFACE
pins of the on-chip SPI interface. Therefore, the user can only
enable one or the other interface at any given time (see SPE in
SPICON previously). Application Note uC001 describes the
operation of this interface as implemented is available from the
MicroConverter website at www.analog.com/microconverter.
Three SFRs are used to control the I2C interface. These are described below:
I2CCON
SFR Address
Power-On Default Value
Bit Addressable
Bit
Name
Description
MDO
MDE
MCO
MDI
I2CM
I2CRS
I2CTX
I2CI
I2CADD
Function
SFR Address
Power-On Default Value
Bit Addressable
Holds the I2C peripheral address for the part. It may be overwritten by user code. Technical Note uC001
at www.analog.com/microconverter describes the format of the I2C standard 7-bit address in detail.
9BH
55H
No
I2CDAT
Function
The I2CDAT SFR is written by the user to transmit data over the I2C interface or read by user code to
read data just received by the I2C interface. Accessing I2CDAT automatically clears any pending I2C
interrupt and the I2CI bit in the I2CCON SFR. User software should only access I2CDAT once per
interrupt cycle.
9AH
00H
No
SFR Address
Power-On Default Value
Bit Addressable
*Purchase of licensed I2C components of Analog Devices or one of its sublicensed associated companies conveys a license for the purchaser under the Philips I 2C Patent
Rights to use the ADuC832 in an I 2C system, provided that the system conforms to the I 2C Standard Specification as defined by Philips.
REV. 0
41
ADuC832
The main features of the MicroConverter I2C interface are:
Only two bus lines are required; a serial data line (SDATA)
and a serial clock line (SCLOCK).
An I2C master can communicate with multiple slave
devices. Because each slave device has a unique 7-bit address,
single master/slave relationships can exist at all times even
in a multislave environment (Figure 34).
On-chip filtering rejects <50 ns spikes on the SDATA and
the SCLOCK lines to preserve data integrity.
The I2C peripheral will only generate a core interrupt if the user
has preconfigured the I2C interrupt enable bit in the IEIP2 SFR,
as well as the global interrupt bit EA in the IE SFR.
; Enabling I2C Interrupts for the ADuC832
MOV IEIP2,#01H
; enable I2C interrupt
SETB EA
On the ADuC832 an autoclear of the I2CI bit is implemented
so this bit is cleared automatically on a read or write access to
the I2CDAT SFR.
MOV
I2CDAT, A
; I2CI autocleared
MOV
A, I2CDAT
; I2CI autocleared
DVDD
I2C
MASTER
Once enabled in I2C slave mode the slave controller waits for a
START condition. If the ADuC832 detects a valid start condition, followed by a valid address, followed by the R/W bit, the
I2CI interrupt bit will automatically be set by hardware.
I2C
SLAVE 1
If for any reason the user tries to clear the interrupt more than
once i.e., access the data SFR more than once per interrupt
then the I2C controller will halt. The interface will then have to
be reset using the I2CRS bit.
I2C
SLAVE 2
The user can choose to poll the I2CI bit or enable the interrupt.
In the case of the interrupt, the PC counter will vector to 003BH
at the end of each complete byte. For the first byte when the user
gets to the I2CI ISR, the 7-bit address and the R/W bit will
appear in the I2CDAT SFR.
The ADuC832 can be used as an I2C master device by configuring the I2C peripheral in master mode and writing software
to output the data bit by bit. This is referred to as a software
master. Master mode is enabled by setting the I2CM bit in the
I2CCON register.
The I2CTX bit contains the R/W bit sent from the master. If
I2CTX is set then the master would like to receive a byte. Thus
the slave will transmit data by writing to the I2CDAT register.
If I2CTX is cleared the master would like to transmit a byte.
Therefore, the slave will receive a serial byte. Software can
interrogate the state of I2CTX to determine whether it should
write to or read from I2CDAT.
42
REV. 0
ADuC832
DUAL DATA POINTER
DPCON
SFR Address
Power-On Default Value
Bit Addressable
Bit
Name
Description
7
6
---DPT
5
4
DP1m1
DP1m0
3
2
DP0m1
DP0m0
----
DPSEL
Note 1: This is the only place where the main and shadow data
pointers are distinguished. Everywhere else in this data sheet
wherever the DPTR is mentioned, operation on the active DPTR
is implied.
Note 2: Only MOVC/MOVX @DPTR instructions are relevant
above. MOVC/MOVX PC/@Ri instructions will not cause the
DPTR to automatically post increment/decrement, and so on.
To illustrate the operation of DPCON, the following code will
copy 256 bytes of code memory at address D000H into XRAM
starting from address 0000H.
MOV
MOV
MOV DPTR,#0D000H
MOVELOOP:
CLR A
MOVC A,@A+DPTR
MOVX @DPTR,A
REV. 0
DPTR,#0
DPCON,#55H
MOV
JNZ
43
A, DPL
MOVELOOP
;
;
;
;
;
;
Main DPTR = 0
Select shadow DPTR
DPTR1 increment mode,
DPTR0 increment mode
DPTR auto toggling ON
Shadow DPTR = D000H
;
;
;
;
;
;
Get data
Post Inc DPTR
Swap to Main DPTR (Data)
Put ACC in XRAM
Increment main DPTR
Swap Shadow DPTR (Code)
ADuC832
POWER SUPPLY MONITOR
interrupt the core using the PSMI bit in the PSMCON SFR.
This bit will not be cleared until the failing power supply has
returned above the trip point for at least 250 ms. This monitor
function allows the user to save working registers to avoid possible data loss due to the low supply condition, and also ensures
that normal code execution will not resume until a safe supply
level has been well established. The supply monitor is also protected against spurious glitches triggering the interrupt circuit.
PSMCON
SFR Address
Power-On Default Value
Bit Addressable
DFH
DEH
No
Table XV. PSMCON SFR Bit Designations
Bit
Name
Description
7
6
---CMPD
PSMI
4
3
TPD1
TPD0
2
1
0
------PSMEN
Reserved.
DVDD Comparator Bit.
This is a read-only bit and directly reflects the state of the DVDD comparator.
Read 1 indicates the DVDD supply is above its selected trip point.
Read 0 indicates the DVDD supply is below its selected trip point.
Power Supply Monitor Interrupt Bit.
This bit will be set high by the MicroConverter if either CMPA or CMPD is low, indicating low analog
or digital supply. The PSMI bit can be used to interrupt the processor. Once CMPD and/or CMPA
return (and remain) high, a 250 ms counter is started. When this counter times out, the PSMI interrupt is
cleared. PSMI can also be written by the user. However, if either comparator output is low, it is not
possible for the user to clear PSMI.
DVDD Trip Point Selection Bits.
These bits select the DVDD trip point voltage as follows:
TPD1
TPD0
Selected DVDD Trip Point (V)
0
0
4.37
0
1
3.08
1
0
2.93
1
1
2.63
Reserved
Reserved
Power Supply Monitor Enable Bit.
Set to 1 by the user to enable the Power Supply Monitor Circuit.
Cleared to 0 by the user to disable the Power Supply Monitor Circuit.
44
REV. 0
ADuC832
WATCHDOG TIMER
WDCON
SFR Address
Power-On Default Value
Bit Addressable
C0H
10H
Yes
Bit
Name
Description
7
6
5
4
PRE3
PRE2
PRE1
PRE0
WDIR
WDS
WDE
WDWR
REV. 0
45
ADuC832
TCEN
ITS0, 1
8-BIT
PRESCALER
HUNDREDTHS COUNTER
HTHSEC
SECOND COUNTER
SEC
Six SFRs are associated with the time interval counter, TIMECON
being its control register. Depending on the configuration of the
IT0 and IT1 bits in TIMECON, the selected time counter register
overflow will clock the interval counter. When this counter is equal
to the time interval value loaded in the INTVAL SFR, the TII bit
(TIMECON.2) is set and generates an interrupt if enabled. If the
ADuC832 is in power-down mode, again with TIC interrupt
enabled, the TII bit will wake up the device and resume code
execution by vectoring directly to the TIC interrupt service vector
address at 0053H. The TIC-related SFRs are described below.
Note also that the timebase SFRs can be written initially with the
current time; the TIC can then be controlled and accessed by
user software. In effect, this facilitates the implementation of a
real-time clock. A block diagram of the TIC is shown in Figure 35.
TIMECON
SFR Address
Power-On Default Value
Bit Addressable
A1H
00H
No
INTERVAL
TIMEBASE
SELECTION
MUX
TIEN
MINUTE COUNTER
MIN
HOUR COUNTER
HOUR
INTERVAL TIMEOUT
TIME INTERVAL COUNTER INTERRUPT
8-BIT
INTERVAL COUNTER
COMPARE
COUNT = INTVAL
TIMER INTVAL
INTVAL
Bit
Name
Description
7
6
---TFH
5
4
ITS1
ITS0
STI
TII
TIEN
TCEN
REV. 0
ADuC832
INTVAL
Function
SFR Address
Power-On Default Value
Bit Addressable
Valid Value
User code writes the required time interval to this register. When the 8-bit interval counter is
equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is
set and generates an interrupt if enabled.
A6H
00H
No
0 to 255 decimal
HTHSEC
Function
SFR Address
Power-On Default Value
Bit Addressable
Valid Value
This register is incremented in 1/128 second intervals once TCEN in TIMECON is active. The
HTHSEC SFR counts from 0 to 127 before rolling over to increment the SEC time register.
A2H
00H
No
0 to 127 decimal
SEC
Function
SFR Address
Power-On Default Value
Bit Addressable
Valid Value
MIN
Function
SFR Address
Power-On Default Value
Bit Addressable
Valid Value
HOUR
Function
SFR Address
Power-On Default Value
Bit Addressable
Valid Value
REV. 0
47
ADuC832
8052 COMPATIBLE ON-CHIP PERIPHERALS
WRITE
TO LATCH
Port 1
Port 1 is also an 8-bit port directly controlled via the P1 SFR.
Port 1 digital output capability is not supported on this device.
Port 1 pins can be configured as digital inputs or analog inputs.
By (power-on) default, these pins are configured as analog inputs,
i.e., 1 written in the corresponding Port 1 register bit. To configure any of these pins as digital inputs, the user should write a
0 to these port bits to configure the corresponding pin as a
high impedance digital input.
These pins also have various secondary functions described in
Table XVIII.
Table XVIII. Port 1, Alternate Pin Functions
Pin
Alternate Function
P1.0
P1.1
P1.5
DVDD
CONTROL
READ
LATCH
INTERNAL
BUS
INTERNAL
BUS
P0.x
PIN
D
WRITE
TO LATCH
CL
LATCH
Q
READ
PIN
CL Q
LATCH
TO ADC
P1.x
PIN
READ
PIN
Port 2
48
REV. 0
ADuC832
In general-purpose I/O port mode, Port 2 pins that have 1s written
to them are pulled high by the internal pull-ups (Figure 39)
and, in that state, can be used as inputs. As inputs, Port 2 pins
being pulled externally low will source current because of the
internal pull-up resistors. Port 2 pins with 0s written to them will
drive a logic low output voltage (VOL) and will be capable of
sinking 1.6 mA.
DVDD
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
P2.6 and P2.7 can also be used as PWM outputs. In the case
that they are selected as the PWM outputs via the CFG832 SFR,
the PWM outputs will overwrite anything written to P2.6 or P2.7.
ADDR
CONTROL
READ
LATCH
WRITE
TO LATCH
CL
DVDD DVDD
2 CLK
DELAY
Q
FROM
PORT
LATCH
DVDD
*SEE FIGURE 39
FOR DETAILS OF
INTERNAL PULL-UP
ALTERNATE
INPUT
FUNCTION
Q2
DVDD
CL
P3.x
PIN
Q1
READ
PIN
LATCH
READ
PIN
INTERNAL
PULL-UP*
LATCH
INTERNAL
PULL-UP*
INTERNAL
BUS
ALTERNATE
OUTPUT
FUNCTION
DVDD
Q3
Q4
In I2C mode (SPE = 0), two pull-down FETs (Q3 and Q4) operate
in parallel in order to provide an extra 60% or 70% of current
sinking capability. In SPI mode, however, (SPE = 1) only one of
the pull-down FETs (Q3) operates on each pin resulting in sink
capabilities identical to that of Port 0 and Port 2 pins.
Px.x
PIN
Port 3
Port 3 is a bidirectional port with internal pull-ups directly
controlled via the P3 SFR. Port 3 pins that have 1s written to
them are pulled high by the internal pull-ups and, in that state,
can be used as inputs. As inputs, Port 3 pins being pulled externally low will source current because of the internal pull-ups.
Port 3 pins with 0s written to them will drive a logic low output
voltage (VOL) and will be capable of sinking 4 mA.
DVDD
Q2 (OFF)
Pin
Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.3 and P3.4 can also be used as PWM outputs. In the case
that they are selected as the PWM outputs via the CFG832 SFR,
the PWM outputs will overwrite anything written to P3.4 or P3.3.
REV. 0
49
SCLOCK
PIN
SCHMITT
TRIGGER
Q4 (OFF)
Q3
ADuC832
DVDD
Read-Modify-Write Instructions
Some 8051 instructions that read a port read the latch while
others read the pin. The instructions that read the latch rather
than the pins are the ones that read a value, possibly change it,
and then rewrite it to the latch. These are called read-modifywrite instructions. Listed below are the read-modify-write
instructions. When the destination operand is a port, or a port
bit, these instructions read the latch rather than the pin.
Q1
(OFF)
Q2
50ns GLITCH
REJECTION FILTER
SCLOCK
PIN
MCO
Q4
Q3
I2CM
ANL
ORL
XRL
JBC
CPL
INC
DVDD
SPE = 1 (SPI ENABLE)
Q1
Q2 (OFF)
SDATA/
MOSI
PIN
HARDWARE SPI
(MASTER/SLAVE)
Q4 (OFF)
MDI
CLR PX.Y*
SETB PX.Y*
Q4
MDO
MDE
SFR
BITS
DJNZ
Q3
HARDWARE I2C
(SLAVE ONLY)
DEC
Q3
I2CM
MISO is shared with P3.3 and as such has the same configuration
as that shown in Figure 40.
*These instructions read the port byte (all 8 bits), modify the addressed bit and
then write the new byte back to the latch.
50
REV. 0
ADuC832
Timers/Counters
User configuration and control of all Timer operating modes is achieved via three SFRs:
TMOD, TCON
Control and configuration for Timers 0 and 1.
T2CON
TMOD
SFR Address
Power-On Default Value
Bit Addressable
Bit
Name
Description
Gate
C/T
5
4
M1
M0
Gate
C/T
1
0
M1
M0
REV. 0
51
ADuC832
TCON
SFR Address
Power-On Default Value
Bit Addressable
88H
00H
Yes
Table XXI. TCON SFR Bit Designations
Bit
Name
Description
TF1
TR1
TF0
TR0
IE1*
IT1*
IE0*
IT0*
*These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins.
52
REV. 0
ADuC832
TIMER/COUNTER 0 AND 1 OPERATING MODES
CORE
CLK*
12
C/ T = 0
TL0
(8 BITS)
12
INTERRUPT
TF0
C/ T = 1
C/T = 0
TL0
TH0
(5 BITS) (8 BITS)
P3.4/T0
INTERRUPT
CONTROL
TF0
TR0
C/T = 1
P3.4/T0
RELOAD
TH0
(8 BITS)
GATE
CONTROL
P3.2/INTO
TR0
P3.2/INT0
CORE
CLK*
CORE
CLK/12
12
C/T = 0
CORE
CLK*
12
C/T = 0
TL0
TH0
(8 BITS) (8 BITS)
INTERRUPT
TL0
(8 BITS)
TF0
TH0
(8 BITS)
TF1
C/T = 1
INTERRUPT
P3.4/T0
TF0
CONTROL
C/T = 1
TR0
P3.4/T0
CONTROL
TR0
GATE
P3.2/INT0
GATE
P3.2/INT0
CORE
CLK/12
INTERRUPT
TR1
*CORE CLK IS DEFINED BY THE CD BITS IN PLLCON
REV. 0
53
ADuC832
T2CON
SFR Address
Power-On Default Value
Bit Addressable
C8H
00H
Yes
Table XXII. T2CON SFR Bit Designations
Bit
Name
Description
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
CNT2
CAP2
54
REV. 0
ADuC832
Timer/Counter Operation Modes
In the Capture mode, there are again two options, which are
selected by bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2
is a 16-bit timer or counter that, upon overflowing, sets bit TF2,
the Timer 2 overflow bit, which can be used to generate an
interrupt. If EXEN2 = 1, then Timer 2 still performs the above,
but a l-to-0 transition on external input T2EX causes the current
value in the Timer 2 registers, TL2 and TH2, to be captured
into registers RCAP2L and RCAP2H, respectively. In addition, the
transition at T2EX causes bit EXF2 in T2CON to be set, and
EXF2, like TF2, can generate an interrupt. The Capture mode
is illustrated in Figure 50.
CAP2
TR2
Mode
0
0
1
X
0
1
X
X
1
1
1
0
16-Bit Autoreload
16-Bit Capture
Baud Rate
OFF
12
C/ T2 = 0
TL2
(8 BITS)
TH2
(8 BITS)
RCAP2L
RCAP2H
C/T2 = 1
T2
PIN
CONTROL
TR2
RELOAD
TRANSITION
DETECTOR
TF2
TIMER
INTERRUPT
T2EX
PIN
EXF2
CONTROL
EXEN2
*CORE CLK IS DEFINED BY THE CD BITS IN PLLCON
12
C/ T2 = 0
TL2
(8 BITS)
TH2
(8 BITS)
TF2
C/ T2 = 1
T2
PIN
CONTROL
TR2
TIMER
INTERRUPT
CAPTURE
TRANSITION
DETECTOR
RCAP2L
T2EX
PIN
RCAP2H
EXF2
CONTROL
EXEN2
*CORE CLK IS DEFINED BY THE CD BITS IN PLLCON
REV. 0
55
ADuC832
while the SFR interface to the UART is comprised of SBUF
and SCON, as described below.
The serial port is full duplex, meaning it can transmit and receive
simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received
byte has been read from the receive register. However, if the first
byte still has not been read by the time reception of the second
byte is complete, the first byte will be lost. The physical interface
to the serial data network is via pins RXD(P3.0) and TXD(P3.1)
SBUF
The serial port receive and transmit registers are both accessed
through the SBUF SFR (SFR address = 99H). Writing to
SBUF loads the transmit register and reading SBUF accesses a
physically separate receive register.
SCON
SFR Address
Power-On Default Value
Bit Addressable
98H
00H
Yes
Table XXIV. SCON SFR Bit Designations
Bit
Name
Description
7
6
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
56
REV. 0
ADuC832
Mode 0: 8-Bit Shift Register Mode
Mode 0 is selected by clearing both the SM0 and SM1 bits in the
SFR SCON. Serial data enters and exits through RxD. TxD
outputs the shift clock. Eight data bits are transmitted or received.
Transmission is initiated by any instruction that writes to SBUF.
The data is shifted out of the RxD line. The eight bits are
transmitted with the least-significant bit (LSB) first, as shown
in Figure 51.
MACHINE
CYCLE 1
MACHINE
CYCLE 2
MACHINE
CYCLE 7
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4
MACHINE
CYCLE 8
To transmit, the eight data bits must be written into SBUF. The
ninth bit must be written to TB8 in SCON. When transmission
is initiated, the eight data bits (from SBUF) are loaded onto the
transmit shift register (LSB first). The contents of TB8 are loaded
into the ninth bit position of the transmit shift register. The
transmission will start at the next valid baud rate clock. The TI flag
is set as soon as the stop bit appears on TxD.
S4 S5 S6 S1 S2 S3 S4 S5 S6
CORE
CLK
ALE
RxD
(DATA OUT)
DATA BIT 0
DATA BIT 1
DATA BIT 6
DATA BIT 7
TxD
(SHIFT CLOCK)
STOP BIT
D0
D1
D2
D3
D4
D5
D6
D7
TI
(SCON.1)
SET INTERRUPT
I.E., READY FOR MORE DATA
This will be the case if, and only if, the following conditions are
met at the time the final shift pulse is generated:
RI = 0, and either SM2 = 0 or SM2 = 1, and the received
stop bit = 1.
If either of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
Mode 3: 9-Bit UART with Variable Baud Rate
57
ADuC832
Timer 1 Generated Baud Rates
When Timer 1 is used as the baud rate generator, the baud rates
in Modes 1 and 3 are determined by the Timer 1 overflow rate and
the value of SMOD as follows:
Table XXV shows some commonly used baud rates and how
they might be calculated from a core clock frequency of 16.78 MHz
and 2.0971 MHz. Generally speaking, a 5% error is tolerable
using asynchronous (start/stop) communications.
Table XXVI shows some commonly used baud rates and how they
might be calculated from a core clock frequency of 16.78 MHz
and 2.10 MHz.
Ideal
Baud
Core
CLK
(MHz)
SMOD
Value
TH1-Reload
Value
Actual
Baud
%
Error
9600
2400
1200
1200
16.78
16.78
16.78
2.10
1
1
1
0
9
36
73
9
9709
2427
1197
1213
1.14
1.14
0.25
1.14
(F9H)
(DCH)
(B7H)
(F4H)
Ideal
Baud
Core
CLK
(MHz)
RCAP2H
Value
RCAP2L
Value
Actual %
Baud Error
19200
9600
2400
1200
9600
2400
1200
16.78
16.78
16.78
16.78
2.10
2.10
2.10
1
1
1
2
1
1
1
27 (E5H)
55 (C9H)
218 (26H)
181 (4BH)
7 (FBH)
27 (ECH)
55 (C9H)
19418
9532
2405
1199
9362
2427
1191
(FFH)
(FFH)
(FFH)
(FEH)
(FFH)
(FFH)
(FFH)
1.14
0.7
0.21
0.02
2.4
1.14
0.7
TIMER 1
OVERFLOW
0
CORE
CLK*
SMOD
C/ T2 = 0
TL2
(8 BITS)
T2
PIN
TH2
(8 BITS)
TIMER 2
OVERFLOW
0
RCLK
C/ T2 =
1
16
1
TR2
RELOAD
16
RCAP2L
T2EX
PIN
RX
CLOCK
0
TCLK
TRANSITION
DETECTOR
CONTROL
EXF 2
TX
CLOCK
RCAP2H
TIMER 2
INTERRUPT
CONTROL
EXEN2
58
REV. 0
ADuC832
Timer 3 Generated Baud Rates
The high integer dividers in a UART block mean that high speed
baud rates are not always possible using some particular crystals.
For example, using a 12 MHz crystal, a baud rate of 115200 is
not possible. To address this problem, the ADuC832 has added
a dedicated baud rate timer (Timer 3) specifically for generating
highly accurate baud rates.
Timer 3 can be used instead of Timer 1 or Timer 2 for generating
very accurate high speed UART baud rates including 115200
and 230400. Timer 3 also allows a much wider range of baud
rates to be obtained. In fact, every desired bit rate from 12 bit/s
to 393216 bit/s can be generated to within an error of 0.8%.
Timer 3 also frees up the other three timers, allowing them to
be used for different applications. A block diagram of Timer 3
is shown in Figure 54.
CORE
CLK*
fCORE
log
32 Baud Rate
DIV =
log(2)
T3FD is the fractional divider ratio required to achieve the
required baud rate. We can calculate the appropriate value for
T3FD using the following formula:
Note: T3FD should be rounded to the nearest integer.
T 3FD =
(1 + T3FD/64)
TIMER 1/TIMER 2
RX CLOCK (FIG 53)
1
16
T3 RX/TX
CLOCK
TX CLOCK
REV. 0
(T 3FD + 64 )
Name
Description
T3BAUDEN
T3UARTBAUD Enable
Set to enable Timer 3 to generate
the baud rate. When set PCON.7,
T2CON.4 and T2CON.5 are ignored.
Cleared to let the baud rate be
generated as per a standard 8052.
Binary Divider Factor
DIV2 DIV1 DIV0 Bin Divider
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
DIV2
DIV1
DIV0
T3EN
6
5
4
3
2
1
0
2 fCORE
DIV
RX
CLOCK
Baud Rate
2DIV
Bit
Once the values for DIV and T3FD are calculated the actual
baud rate can be calculated using the following formula:
2
TIMER 1/TIMER 2
TX CLOCK (FIG 53)
FRACTIONAL
DIVIDER
2 fCORE
DIV
Ideal
Baud
CD
DIV
T3CON
T3FD
%
Error
230400
81H
09H
0.25
115200
115200
115200
0
1
2
2
1
0
82H
81H
80H
09H
09H
09H
0.25
0.25
0.25
57600
57600
57600
57600
0
1
2
3
3
2
1
0
83H
82H
81H
80H
09H
09H
09H
09H
0.25
0.25
0.25
0.25
38400
38400
38400
38400
0
1
2
3
3
2
1
0
83H
82H
81H
80H
2DH
2DH
2DH
2DH
0.2
0.2
0.2
0.2
19200
19200
19200
19200
19200
0
1
2
3
4
4
3
2
1
0
84H
83H
82H
81H
80H
2DH
2DH
2DH
2DH
2DH
0.2
0.2
0.2
0.2
0.2
9600
9600
9600
9600
9600
9600
0
1
2
3
4
5
5
4
3
2
1
0
85H
84H
83H
82H
81H
80H
2DH
2DH
2DH
2DH
2DH
2DH
0.2
0.2
0.2
0.2
0.2
0.2
59
ADuC832
INTERRUPT SYSTEM
IE
SFR Address
Power-On Default Value
Bit Addressable
A8H
00H
Yes
Table XXIX. IE SFR Bit Designations
Bit
Name
Description
7
6
5
4
3
2
1
0
EA
EADC
ET2
ES
ET1
EX1
ET0
EX0
IP
SFR Address
Power-On Default Value
Bit Addressable
B8H
00H
Yes
Table XXX. IP SFR Bit Designations
Bit
Name
Description
7
6
5
4
3
2
1
0
---PADC
PT2
PS
PT1
PX1
PT0
PX0
IEIP2
SFR Address
Power-On Default Value
Bit Addressable
A9H
A0H
No
Table XXXI. IEIP2 SFR Bit Designations
Bit
Name
Description
7
6
5
4
3
2
1
0
---PTI
PPSM
PSI
---ETI
EPSMI
ESI
REV. 0
ADuC832
Interrupt Priority
This section outlines some of the key hardware design considerations that must be addressed when integrating the ADuC832
into any hardware system.
Clock Oscillator
Source
Priority
Description
PSMI
WDS
IE0
ADCI
TF0
IE1
TF1
ISPI/I2CI
RI + TI
TF2 + EXF2
TII
1 (Highest)
2
2
3
4
5
6
7
8
9 (Lowest)
11(Lowest)
XTAL2
TO INTERNAL
TIMING CIRCUITS
Interrupt Vectors
ADuC832
EXTERNAL
CLOCK
SOURCE
P3.4
TO INTERNAL
TIMING CIRCUITS
REV. 0
Source
Vector Address
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
ADCI
ISPI/I2CI
PSMI
TII
WDS
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
0043H
0053H
005BH
61
ADuC832
External Memory Interface
SRAM
ADuC832
D0D7
(DATA)
P0
LATCH
ALE
A8A15
P2
RD
OE
WR
WE
ADuC832
D0D7
(DATA)
P0
LATCH
A0A7
ALE
A8A15
P2
LATCH
ADuC832
A0A7
EPROM
A16A23
D0D7
(INSTRUCTION)
P0
LATCH
A0A7
RD
OE
WR
WE
ALE
P2
PSEN
A8A15
OE
Note that program memory addresses are always 16 bits wide, even
in cases where the actual amount of program memory used is
less than 64 kBytes. External program execution sacrifices two of
the 8-bit ports (P0 and P2) to the function of addressing the program memory. While executing from external program memory,
Ports 0 and 2 can be used simultaneously for read/write access
to external data memory, but not for general-purpose I/O.
Though both external program memory and external data memory
are accessed by some of the same pins, the two are completely
independent of each other from a software point of view. For
example, the chip can read/write external data memory while
executing from external program memory.
Figure 58 shows a hardware configuration for accessing up to
64 kBytes of external RAM. This interface is standard to any
8051 compatible MCU.
62
REV. 0
ADuC832
Separate analog and digital power supply pins (AVDD and DVDD,
respectively) allow AVDD to be kept relatively free of noisy digital
signals often present on the system DVDD line. However, though
you can power AVDD and DVDD from two separate supplies if
desired, you must ensure that they remain within 0.3 V of one
another at all times in order to avoid damaging the chip (as per
the Absolute Maximum Ratings section). Therefore, it is recommended that unless AVDD and DVDD are connected directly
together, you connect back-to-back Schottky diodes between
them as shown in Figure 60.
ANALOG SUPPLY
DIGITAL SUPPLY
10F
10F
ADuC832
DVDD
AVDD
0.1F
it should also be noted that, at all times, the analog and digital
ground pins on the ADuC832 must be referenced to the same
system ground reference point.
Power Consumption
0.1F
DGND
VDD = 5 V
AGND
DIGITAL SUPPLY
+
10F
BEAD
1.6
10F
ADuC832
DVDD
AVDD
0.1F
0.1F
Core:
(Normal Mode) (1.6 nAs MCLK) +
6 mA
Core:
(0.75 nAs MCLK) +
(Idle Mode)
5 mA
ADC:
1.3 mA
DAC (Each):
250 mA
Voltage Ref:
200 mA
VDD = 3 V
(0.8 nAs MCLK) +
3 mA
(0.25 nAs MCLK) +
3 mA
1.0 mA
200 mA
150 mA
DGND
AGND
Notice that in both Figure 60 and Figure 61, a large value (10 mF)
reservoir capacitor sits on DVDD and a separate 10 mF capacitor
sits on AVDD. Also, local small-value (0.1 mF) capacitors are
located at each VDD pin of the chip. As per standard design practice, be sure to include all of these capacitors, and ensure the
smaller capacitors are close to each AVDD pin with trace lengths
as short as possible. Connect the ground terminal of each of
these capacitors directly to the underlying ground plane. Finally,
REV. 0
In idle mode, the oscillator continues to run but the core clock
generated from the PLL is halted. The on-chip peripherals
continue to receive the clock, and remain functional. The CPU
status is preserved with the stack pointer and program counter,
and all other internal registers maintain their data during idle
mode. Port pins and DAC output pins retain their states in this
mode. The chip will recover from idle mode upon receiving any
enabled interrupt, or upon receiving a hardware reset.
In full power-down mode, both the PLL and the clock to the core
are stopped. The on-chip oscillator can be halted or can continue
to oscillate depending on the state of the oscillator power-down
bit in the PLLCON SFR. The TIC, being driven directly from
63
ADuC832
the oscillator, can also be enabled during power down. All other
on-chip peripherals however, are shut down. Port pins retain
their logic levels in this mode, but the DAC output goes to a
high impedance state (three-state). During full power-down
mode, the ADuC832 consumes a total of approximately 20 A.
There are five ways of terminating power-down mode:
Asserting the RESET pin (Pin 15)
All registers are set to their default state and program execution
starts at the reset vector approximately 128 ms later.
Time Interval Counter (TIC) Interrupt
Although the ADuC832 has separate pins for analog and digital
ground (AGND and DGND), the user must not tie these to two
separate ground planes unless the two ground planes are connected
together very close to the ADuC832, as illustrated in the simplified example of Figure 63a. In systems where digital and analog
ground planes are connected together somewhere else (at the
systems power supply for example), they cannot be connected
again near the ADuC832 since a ground loop would result. In
these cases, tie the ADuC832s AGND and DGND pins all to
the analog ground plane, as illustrated in Figure 63b. In systems
with only one ground plane, ensure that the digital and analog
components are physically separated onto separate halves of the
board such that digital return currents do not flow near analog
circuitry and vice versa. The ADuC832 can then be placed between
the digital and analog sections, as illustrated in Figure 63c.
In all of these scenarios, and in more complicated real-life applications, keep in mind the flow of current from the supplies and
back to ground. Make sure the return paths for all currents are as
close as possible to the paths the currents took to reach their destinations. For example, do not power components on the analog
side of Figure 63b with DVDD since that would force return currents
from DVDD to flow through AGND. Also, try to avoid digital
currents flowing under analog circuitry, which could happen if
the user placed a noisy digital chip on the left half of the board
in Figure 63c. Whenever possible, avoid large discontinuities in
the ground plane(s) (such as are formed by a long trace on the
same layer), since they force return signals to travel a longer path.
And of course, make all connections to the ground plane directly,
with little or no trace separating the pin from its via to ground.
If the user plans to connect fast logic signals (rise/fall time < 5 ns)
to any of the ADuC832s digital inputs, add a series resistor to
each relevant line to keep rise and fall times longer than 5 ns at
the ADuC832 input pins. A value of 100 or 200 is usually
sufficient to prevent high speed signals from coupling capacitively
into the ADuC832 and affecting the accuracy of ADC conversions.
a.
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS
HERE
AGND
DGND
2.45V TYP
DVDD
1.0V TYP
128ms TYP
128ms TYP
1.0V TYP
b.
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS
HERE
AGND
DGND
INTERNAL
CORE RESET
c.
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS
HERE
GND
64
REV. 0
ADuC832
DOWNLOAD/DEBUG
ENABLE JUMPER
(NORMALLY OPEN)
DVDD
DVDD
1k
1k
46
45
44
43
42
41 40
EA
47
48
PSEN
49
DVDD
50
DGND
51
52
ADC0
ANALOG INPUT
AVDD
36
AVDD
AGND
VREF OUTPUT
10
DVDD
DGND 35
DVDD 34
ADuC832
CREF
XTAL2 33
VREF
XTAL1 32
DAC0
31
DAC1
30
32.768kHz
29
14
16
18
19
DGND
DVDD
TxD
RxD
ADC7
RESET
DAC OUTPUT
28
27
20
24
26
ADM202
C1+
V+
DVDD
9-PIN D-SUB
FEMALE
VCC
GND
C1
T1OUT
C2+
R1IN
C2
R1OUT
T1IN
T2OUT
T2IN
R2OUT
R2IN
8
9
REV. 0
65
ADuC832
Figure 65 shows the typical components of a QuickStart Development System. A brief description of some of the software tools
components in the QuickStart Development System follows.
Software:
Miscellaneous:
ASPIREIDE
66
REV. 0
ADuC832
QuickStart Plus Development System
The QuickStart Plus Development system offers users enhanced
nonintrusive debug and emulation tools. The System consists of
the following PC based (Windows compatible) hardware and
software development tools.
Hardware:
Software:
Miscellaneous:
CD-ROM Documentation.
TIMING SPECIFICATIONS1, 2, 3
(AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V;
all specifications TMIN to TMAX, unless otherwise noted.)
32.768 kHz External Crystal
Min
Typ
Max
Parameter
CLOCK INPUT (External Clock Driven XTAL1)
XTAL1 Period
tCK
tCKL
XTAL1 Width Low
XTAL1 Width High
tCKH
XTAL1 Rise Time
tCKR
tCKF
XTAL1 Fall Time
ADuC832 Core Clock Frequency4
1/tCORE
ADuC832 Core Clock Period5
tCORE
tCYC
ADuC832 Machine Cycle Time6
30.52
15.16
15.16
20
20
0.131
16.78
0.476
5.7
0.72
91.55
Unit
Figure
s
s
s
ns
ns
MHz
s
s
68
68
68
68
68
NOTES
1
AC inputs during testing are driven at DV DD 0.5 V for a Logic 1 and 0.45 V for a Logic 0. Timing measurements are made at V IH min for a Logic 1 and V IL max for
a Logic 0, as shown in Figure 69.
2
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the
loaded VOH/VOL level occurs, as shown in Figure 69.
3
CLOAD for all outputs = 80 pF, unless otherwise noted.
4
ADuC832 internal PLL locks onto a multiple (512 times) the external crystal frequency of 32.768 kHz to provide a Stable 16.78 MHz internal clock for the system.
The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
5
This number is measured at the default Core_Clk operating frequency of 2.09 MHz.
6
ADuC832 Machine Cycle Time is nominally defined as 12/Core_CLK.
tCKR
tCHK
tCKL
tCKF
tCK
DVDD 0.5V
0.45V
0.2DVDD + 0.9V
TEST POINTS
0.2DVDD 0.1V
VLOAD 0.1V
VLOAD
VLOAD + 0.1V
TIMING
REFERENCE
POINTS
REV. 0
67
VLOAD 0.1V
VLOAD
VLOAD + 0.1V
ADuC832
Parameter
Variable Clock
Min
Max
79
19
29
2tCK 40
tCK 40
tCK 30
Unit
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
70
70
70
70
70
70
70
70
70
70
70
ALE Pulsewidth
Address Valid to ALE Low
Address Hold after ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulsewidth
PSEN Low to Valid Instruction In
Input Instruction Hold after PSEN
Input Instruction Float after PSEN
Address to Valid Instruction In
PSEN Low to Address Float
Address Hold after PSEN High
138
4tCK 100
29
133
tCK 30
3tCK 45
73
3tCK 105
0
34
193
25
tCK 25
5tCK 105
25
MCLK
tLHLL
ALE (O)
tAVLL
tLLPL
tPLPH
tLLIV
tPLIV
PSEN (O)
PORT 0 (I/O)
tPXIZ
tPLAZ
tLLAX
tPXIX
INSTRUCTION
(IN)
PCL (OUT)
tAVIV
PORT 2 (O)
tPHAX
PCH
68
REV. 0
ADuC832
Parameter
Variable Clock
Min
Max
257
19
24
6tCK 100
tCK 40
tCK 35
Unit
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
71
71
71
71
71
71
71
71
71
71
71
71
RD Pulsewidth
Address Valid after ALE Low
Address Hold after ALE Low
RD Low to Valid Data In
Data and Address Hold after RD
Data Float after RD
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address Valid to RD or WR Low
RD Low to Address Float
RD or WR High to ALE High
133
5tCK 165
0
49
326
371
228
128
108
3tCK 50
4tCK 130
0
257
19
2tCK 70
8tCK 150
9tCK 165
3tCK + 50
0
6tCK 100
tCK 40
MCLK
ALE (O)
tWHLH
PSEN (O)
tLLDV
tLLWL
RD (O)
tRLRH
tAVWL
tRLDV
tAVLL
tRHDZ
tLLAX
tRHDX
tRLAZ
PORT 0 (I/O)
A0A7 (OUT)
DATA (IN)
tAVDV
PORT 2 (O)
A16A23
A8A15
REV. 0
69
ADuC832
Parameter
Variable Clock
Min
Max
Unit
Figure
257
19
24
128
108
9
267
9
19
6tCK 100
tCK 40
tCK 35
3tCK 50
4tCK 130
tCK 50
7tCK 150
tCK 50
tCK 40
ns
ns
ns
ns
ns
ns
ns
ns
ns
72
72
72
72
72
72
72
72
72
WR Pulsewidth
Address Valid after ALE Low
Address Hold after ALE Low
ALE Low to RD or WR Low
Address Valid to RD or WR Low
Data Valid to WR Transition
Data Setup before WR
Data and Address Hold after WR
RD or WR High to ALE High
228
257
3tCK + 50
6tCK 100
MCLK
ALE (O)
tWHLH
PSEN (O)
tLLWL
tWLWH
WR (O)
tAVWL
tAVLL
tLLAX
tQVWX
A0A7
PORT 2 (O)
tWHQX
tQVWH
DATA
A16A23
A8A15
70
REV. 0
ADuC832
16.78 MHz Core Clk
Min
Typ
Max
Parameter
Min
Variable Clock
Typ
Max
Unit
Figure
s
ns
ns
ns
ns
73
73
73
73
73
715
463
252
0
22
12tCK
10tCK 133
2tCK + 133
0
2tCK 117
ALE (O)
tXLXL
TxD
(OUTPUT CLOCK)
7
SET RI
OR
SET TI
tQVXH
tXHQX
RxD
(OUTPUT DATA)
MSB
BIT6
tDVXH
RxD
(INPUT DATA)
MSB
LSB
BIT1
tXHDX
BIT6
BIT1
REV. 0
71
LSB
ADuC832
Parameter
Min
Max
Unit
Figure
s
s
s
s
s
s
s
s
74
74
74
74
74
74
74
74
ns
ns
ns
74
74
74
4.7
4.0
0.6
100
0.9
0.6
0.6
1.3
300
300
50
*Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50 ns.
tBUF
tSUP
SDATA (I/O)
LSB
MSB
tDSU
tPSU
tDSU
2-7
PS
tL
MSB
tF
tDHD
tR
tRSU
tH
1
STOP
START
CONDITION CONDITION
ACK
tDHD
tSHD
SCLK (I)
tR
tSUP
S(R)
REPEATED
START
tF
72
REV. 0
ADuC832
Parameter
Min
Typ
Max
Unit
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
75
75
75
75
75
75
75
75
75
476
476
50
100
100
10
10
10
10
25
25
25
25
SCLOCK
(CPOL = 0)
t SL
t SH
t SR
t SF
SCLOCK
(CPOL = 1)
t DAV
MSB
MOSI
MISO
t DR
t DF
MSB IN
t DSU
BIT 6 1
t DHD
REV. 0
LSB
BIT 6 1
73
LSB IN
ADuC832
Parameter
Min
Typ
Max
Unit
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
76
76
76
76
76
76
76
76
76
76
476
476
50
150
100
100
10
10
10
10
25
25
25
25
SCLOCK
(CPOL = 0)
t SL
t SH
t SF
t SR
SCLOCK
(CPOL = 1)
t DAV
t DF
t DOSU
MSB
MOSI
MISO
MSB IN
t DSU
t DR
BIT 6 1
BIT 6 1
LSB
LSB IN
t DHD
74
REV. 0
ADuC832
Parameter
Min
Typ
Max
Unit
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
77
77
77
77
77
77
77
77
77
77
77
SS to SCLOCK Edge
SCLOCK Low Pulsewidth
SCLOCK High Pulsewidth
Data Output Valid after SCLOCK Edge
Data Input Setup Time before SCLOCK Edge
Data Input Hold Time after SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
SS High after SCLOCK Edge
0
330
330
50
100
100
10
10
10
10
25
25
25
25
SS
t SFS
t SS
SCLOCK
(CPOL = 0)
t SL
t SH
t SF
t SR
SCLOCK
(CPOL = 1)
t DAV
MISO
MOSI
t DR
t DF
MSB
BIT 61
BIT 61
MSB IN
t DSU
t DHD
REV. 0
75
LSB
LSB IN
ADuC832
Parameter
Min
Typ
Max
Unit
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
78
78
78
78
78
78
78
78
78
78
78
78
SS to SCLOCK Edge
SCLOCK Low Pulsewidth
SCLOCK High Pulsewidth
Data Output Valid after SCLOCK Edge
Data Input Setup Time before SCLOCK Edge
Data Input Hold Time after SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
Data Output Valid after SS Edge
SS High after SCLOCK Edge
0
330
330
50
100
100
10
10
10
10
25
25
25
25
20
SS
t SFS
t SS
SCLOCK
(CPOL = 0)
t SH
t SL
t SR
t SF
SCLOCK
(CPOL = 1)
t DAV
t DOSS
t DF
MSB
MISO
MOSI
MSB IN
t DSU
t DR
BIT 61
BIT 61
LSB
LSB IN
t DHD
76
REV. 0
ADuC832
OUTLINE DIMENSIONS
52-Lead Plastic Quad Flatpack [MQFP]
(S-52)
Dimensions shown in millimeters
1.03
0.88
0.73
14.15
13.90 SQ
13.65
2.45
MAX
39
27
40
SEATING
PLANE
26
7.80
REF
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
VIEW A
PIN 1
52
14
1
0.23
0.11
13
0.65 BSC
0.38
0.22
2.10
2.00
1.95
7
0
0.10 MIN
COPLANARITY
VIEW A
ROTATED 90 CCW
8.00
BSC SQ
0.60 MAX
0.60 MAX
43
7.75
BSC SQ
TOP
VIEW
0.25
REF
12 MAX
29
28
15 14
6.50
REF
0.70 MAX
0.65 NOM
0.10 MAX
0.50 BSC
SEATING
PLANE
COPLANARITY
0.08
REV. 0
6.25
6.10
5.95
BOTTOM
VIEW
0.50
0.40
0.30
1.00
0.90
0.80
PIN 1
INDICATOR
56 1
42
PIN 1
INDICATOR
0.30
0.23
0.18
77
78
79
80
PRINTED IN U.S.A.
C02987011/02(0)