POSSIBLE QUESTIONS

UNIT I
PART A
1. Define Digital computer.
It is a fast electronic calculating machine that accepts digitized input
information, processes it according to a list of internally stored instructions,
and produces the resulting output information.
2. Mention the types of computers
Personal computer: schools, business offices, desktop
Portable notebook: used mainly for word processing, desktop
High performance workstations: graphics and I/O capability, higher computational power, desktop
Mainframes: business data processing in medium to large range corporations
Supercomputers: large scale numerical calculations.
3. Name the three systems used for representing both positive and Negative numbers.
a.
Sign and magnitude.
b.
1s complement
c.
2s complement
4. Define computer architecture.
Computer Architecture deals with the structure and behavior of a computer including the
information formats, the instruction sets and various techniques used for memory addressing.
5. Define Input Unit.
Computers accept coded information through input units(read data).
Example: The keyboard is wired so that whenever a key is pressed, the corresponding digit is
automatically translated to its corresponding code and sent to the memory or to the processor.
Other examples: joysticks, trackballs and mice.
6. What are the registers that communicate with the main memory?
Memory address register and memory data register are the registers that communicate with
the main memory
7. Explain Arithmetic and Logical Unit?
ALU is the heart of the machine.
All arithmetic operations such as addition, subtraction, multiplication and division is done here.
Logical operations such as AND, OR and NOT are also performed
Operands and results of ALU operation could be located in register or in memory.
8. Define IR and PC register.
IR register: holds the instruction that is currently being executed. The IR content is available
to the control circuits which generate timing signals.
PC register: register that keeps track of the execution of a program, it contains that memory
address of the next instruction to be executed.
9. What is meant by MAR and MDR?

MAR: Memory address register, hold the address of the location to or from which data are
to be transferred.
MDR: contains the data to be written into or read out of the addressed location.
10. Define Bus with its types.
Bus is defines as a group of wires that connects several devices. Buses usually carry data,
address and control signals.
Single bus: All units are connected to this bus. Only two units can use the bus at any given
instant. Low cost, can easily add new devices on the bus.
Multiple bus: Systems that contain multiple buses achieve more parallelism. It has a better
performance at an increased cost.
11.Define system software with its functions.
System software is a collection of programs that are used to perform the following
functions.
Receive and interpret user commands.
Enter and edit application program.
Store files in secondary storage.
Manage the storage and retrieval of files in secondary storage.
Run standard applications such as spreadsheets.
Control I/O units to receive input information and produce results.
Translate programs from source prepared by the user into object form (machine
instructions).
12. What is meant by operating system?
The operating system (another system software) is a collection of routines used to control
the sharing an interaction among different computer units.
13. What are the two different schemes are used to place an individual byte without a word?
Little endian: byte 0 is the rightmost byte of word 0
Big endian: byte 0 is the leftmost byte of word 0
14. Name the types of operations that a computer must perform using instruction?
A computer must have instructions capable of performing four types of operations
a.
Data transfers between the main memory and the CPU registers
b.
Arithmetic and logic operations on data
c.
Program sequencing and control
d.
I/O transfer.
15. Define Three Address Instruction
Instruction that contains three address fields, each providing the address
of one of the operands. Three address instruction can be represented
symbolically as Add A,B,C
Operands A and B are the source, operand C is the destination
Operation Source1, Source2, Destination

PART B
1. Explain the different types of addressing modes with suitable examples
2. Explain one, two, three addressing instructions with example
3. Explain in detail the different instruction types and instruction sequencing.
4. With a neat diagram explain Von Neumann computer architecture
5. What are the various types of Instruction set Architectures (ISAs) possible? Discuss.
6. Describe the functional units of the computer system.
7. Describe in detail Booths algorithm and its hardware implementation with suitable example
8. Explain restoring and non-restoring division method with own example.
9. Enumerate ALU design.
10. Explain about processing unit.

POSSIBLE QUESTIONS

UNIT II
PART A
1. What is floating point numbers?
In some cases, the binary point is variable and is automatically adjusted
as computation proceeds. In such cases, the binary point is said to be float
and the numbers are called floating point numbers.
2. What is meant by overflow?
a. When adding unsigned numbers, the carry-out cn serves as the overflow indicatorthis does not
work for adding signed numbers Example: adding +7 and +4 in 4-bit adder, the output vector S =
1011 = -5 and the carry-out signal from the MSB is 0
b. add -4 and -6 , S = +6, and the carry-out signal is 1
The addition of numbers with different signs cannot cause overflow because the absolute value of
the sum is always smaller than the absolute value of one of the two summands
`3.Define Booth Algorithm.
Booth Algorithm is a powerful algorithm for signed-number multiplication. It generates 2nbit product and treats positive and negative numbers uniformly.
4. What are the two types of Division Algorithm
a. Restoring Division
b. Non Restoring Division
5. Write the restoring division algorithm.
Shift A and Q left one binary position.
Subtract M from A, and place the answer back in A.
If the sign of A is 1, set q0 to 0 and add M back to A(ie, restore A);otherwise, set q0 to 1.
6. Write the non-restoring division algorithm.
a. Step 1: Do the following n times: If the sign of A is 0, shift A and Q left one bit position
and subtract M from A; otherwise, shift a and Q left and M to A.
Now, if the sign of A is 0, set q0 to 1; otherwise, set q0 to 0.
b. Step 2: If the sign of A is 1, add M to A.
7. Mention some of the Exceptions.
a. Invalid operation, division by 0, overflow, underflow and inexact
8. Write the rules for floating point arithmetic operations.
Add/subtract
a. choose the number with the smaller exponent and shift its mantissa right a number of
steps equal to the difference in exponents
b. set the exponent of the result equal to the larger exponent
c. perform addition/subtraction on the mantissas and determine the sign of the result
d. normalize the resulting value
Multiply
e.add the exponents and subtract 127

f. multiply the mantissas and determine the sign of the result

g. normalize the resulting value
Divide
h. subtract the exponents and add 127
i. divide the mantissas and determine the sign of the result
j. normalize the resulting value
9. Name the three truncation methods.
i. Chopping.
ii. Von Neumann rounding
iii. Rounding.
10. Define chopping.
There are several ways to truncate .The simplest way is to remove the guard bit and maker no
changes in the retained bits. This is called chopping.
11. Name the types of Adder.
a. Fast adder
b. Full adder
c. n-bit ripple carry adder
d. Carry lookahead adder.
12. What is Bit Slice processing? & what are the two types of ALU expansion?
The ALU can be easily designed for expansion to handle operands of size n=km or word size n>m.
Spatial expansion and temporal expansion.
13. What is overflow and underflow?
A floating-point operation causes overflow or underflow if the result is too large or too small to
be represented shifting the mantissa of the result and modifying its exponent correct the overflow
and underflow resulting from the mantissa operations.This is done automatically during the floating
point processing. However exponent overflow or underflow causes an error signal generation.
14. What is guard bit?
To preserve accuracy during floating point calculations one or more extra bits called guard bit
are temporarily attached to the right end of the mantissa.
15. Write the rule for addition and subtraction of floating point numbers.
Choose the number with the smaller exponent and shift its mantissa right a number of steps
equal to the difference in exponents.
Set the exponent of the result equal to the larger exponent.
Perform addition/subtraction on the mantissas and determine the sign of the result.
Normalize the resulting value, if necessary.

PART B

1.
2.
3.
4.
5.

Explain the Multiplication algorithm in detail with diagram and examples

Discuss in detail about division algorithm in detail with diagram and examples
Explain in detail about floating point addition with example
Explain in detail about floating point multiplication
Give the algorithm for multiplication of signed 2s complement
numbers and illustrate with an example
6. Multiply the following pair of signed 2s complement
numbers : A = 010111, B = 101100.
7. Add the numbers 0.510 and -0.437510using binary Floating point Addition algorithm
10
-5
8. Multiply 1.10 10X 10 and 9.200X10 using binary Floating point multiplication
9. Calculate the division of A and B A :
3
2
3.264 X 10 B: 6.52 X 10
10 .Show the IEEE 754 binary representation of the number -0.75 10in single and double
precision

POSSIBLE QUESTIONS

UNIT III
PART A
1. Define Pipelining.
Pipelining is used to overlapping the instruction execution. It reduces the overall processing time.
2. Name the steps in pipelined processor?
A pipelined processor may process each instruction in 4 steps
F: fetch, read the instruction from memory
D: decode, decode the instruction and fetch the source operands
O: operate, perform the operation
W: write, store the result in the destination location
Four instructions are in progress at any given time, each unit operates on different data and
the result is passed downstream through a storage buffer.
3. What is meant by hazards? Mention its types.
Any condition that causes the pipeline to stall is called a hazard.The different types of hazard
which would occur are Data hazard, Control hazard (instruction hazard) and Structural hazard
4. Define instruction pipeline.
The type of pipeline which works by partitioning the instruction execution is called
Instruction Pipeline
5. What is a pipeline hazard?
In a pipelined environment when the next instruction cannot be executed in the following
machine cycle, that situation is called hazard in pipeline.
6. Define data hazard.
It occurs when an instruction is waiting for adapt that is not yet available because the
previous instruction has not completed.
7. Define control hazard?
It occurs due to branch instruction since the branch condition and the branch address are not
available in time to fetch the next instruction on the next clock cycle.
8. What is instruction level parallelism?
Pipeline increases performance by overlapping execution of independent instructions. The
potential to overlap instructions is called Instruction-level parallelism since the instructions are
evaluated in parallel.
9. What is Name dependence?
Name dependence is said to occur when two instructions use the same register or memory
location and there is no flow of data between instructions that uses the same name.
10. Give some feature of superscalar processor
1) Smaller code size
2) Binary compatibility across generations of hardware
3) No hardware changes required.
11. What is data path implementation?

The design of data path involves decision at several levels of abstraction. The control signals
from the interface between the data path and the control unit, and is thus an important part of data
path design and used to implement them. This is data path implementation.
12. What are the methods used to design a control unit?
Hardwired Control Unit
Micro programmed control Unit.
13. Mention the data hazards that occur during pipeline operation.
Write after Read hazards (Anti dependences hazards)
Read after Write hazards (Flow dependence hazards)
Write after Write hazards (Output dependence hazards)
14. What are the factors to be considered while deciding number of pipeline stages in a
system?
The n-stage pipeline may get more throughputs by using more number of stages. When you
are increasing number of stages, probability of the pipeline to be stalled increases. As the number of
pipeline stages increase, the branch penalties may becomes more significant.
15. List out techniques used to overcome data hazards.
Operand forwarding
Compiler can rearrange the instructions to avoid data hazards
16. List any two conditions when a processor can stall.
Cache miss
Hazard in pipeline
17. Define stall.
Idle periods are called stalls. They are also named as bubbles in pipeline.
18. What are the problems faced in the instruction pipeline?
Resource conflicts
Data dependency
Branch difficulties
PART B
1. Explain the basic MIPS implementation of instruction set
2. Explain the basic MIPS implementation with necessary multiplexers and control lines
3. What are control hazards? Explain the methods for dealing with the control hazards.
4. Discuss the influence of pipelining in detail.
5. Explain how the instruction pipeline works. What are the various situations where an
instruction pipeline can stall? What can be its resolution?
6. What is data hazard? How do you overcome it?What are its side effects?
7. Discuss the data and control path methods in pipelining
8. Explain dynamic branch prediction
9. How exceptions are handled in MIPS
10. Explain in detail about building a datapath
11. Explain in detail about control implementation scheme
POSSIBLE QUESTIONS

UNIT IV
PART A
1. Classify the memory components of a system.
Internal processor memory
Main memory
Secondary memory
Caches
2. What is meant by cache memory?
A small and fastest memory that is constructed of very high-speed devices (flip-flops and
gates SRAM) and added to the processor to reduce its memory access time
3. What are the objectives of memory design?
to provide adequate storage capacity
to design a memory system with an acceptable level of performance
Reasonable cost
4. What are the reasons for using virtual memory?
To free the programmers from the need to carry out storage allocation
To permit efficient sharing of memory space among different users
To make programs independent of the configuration and the capacity of the memory
systems.
To achieve high access rates and low cost per bit.
5. What is block contention problem?
The problem suffered by direct mapping method in which one or more frequently used
block occupies the same block in cache memory even if unused blocks are available
6. Define EPROMS
Allows stored data to erased and new data to be loaded
Erasable reprogrammable ROM (EPROM)
Provide flexibility during the development phase of a digital system
Erasure requires the dissipating the charges trapped in the transistors
This can be done by exposing chip to ultra violet light
A disadvantage of EPROMs is that a chip must be physically removed from the circuit for
reprogramming
7. Define EEPROMS
An alternative to EPROMs, they can be programmed and erased electricallyCells in
EEPROMs can be erased selectively.
Disadvantage of EEPROMs: different voltages are needed for erasing, writing and reading stored
data
8. Differentiate temporal spatial locality.
suggests that whenever an item (instruction or data) is first needed,

this item should be brought to the cache where it hopefully remains until it is needed again
Spatial locality
suggests that instead of bringing one item from main memory, it is wise to bring several items
that reside in adjacent addresses as well
block or cache line : is used to refer to a set of contiguous addresses
9. What is meant by read miss in cache?
the addressed word is not in the cache
after the entire block is loaded into the cache, the particular word requested is forwarded to
the CPU
Alternatively, the word may be sent directly to CPU as soon as it is read from main memory :
load through or early restart
10. What is meant by replacement algorithm?
When a new block is to be brought into the cache and all the positions that is may occupy
are full, the cache controller must decide which of the old blocks to overwrite
11. What are the different types of interrupts?

Interrupts may be external or internal

Hardware and software interrupts are also raised

Interrupts are raised by power failure conditions, divide by zero etc.

Masking and enabling of these can also be done.

12. Mention the advantage and Disadvantage of Direct mapped Cache.

Advantage:
Simple to implement
Disadvantage:
Suffers from block contention problem If one or more frequently used block occupies the
same block in CM even if unused blocks are available
Not very flexible
13.
Define the technique FIFO and LRU
FIFO removes the oldest block simple - but frequently used block is removed if oldest
LRU removes the block that has not been referred for the longest period of time -better more
difficult to implement
14.

Differentiate SRAM and DRAM. [AU-Nov-2008]

SRAM

DRAM

Bits stored in flip-flop

Bits stored as charge incapacitors

No charges to leak

Charges leak in milliseconds

No refreshing needed when powered -
Need periodic refreshing even when
does not need refresh circuits, does not powered read, rewrite by CPU
waste time refreshing

Need to refresh dynamic RAM

More complex cell more transistors

Simpler construction but need refresh

per cell
circuits
Larger per bit

Smaller per bit

More expensive

Less expensive
Faster

Slower
Used for cache memory

Used for main memory

15. Define memory Latency.

Time taken to transfer a single word of data to or from memory. Definition is clear if the
memory operation involves transfer of a single word of data. In case of a block transfer, latency is
the time it takes to transfer first word of data. Time required to transfer first word in a block is
substantially larger than the time required transferring consecutive words in a block.
PART B
1. Explain in detail about memory technologies
2. Explain in detail about memory Hierarchy with neat diagram
3. Describe the basic operations of cache in detail with diagram
4. Discuss the various mapping schemes used in cache designA byte addressable computer has a
small data cache capable of holding eight 32-bit words. Each cache block contains 132-bit word.
When a given program is executed, the processor reads data from the following sequence of hex
addresses 200, 204, 208, 20C, 2F4, 2F0, 200, 204,218, 21C, 24C, 2F4. The pattern is repeated
four times. Assuming that the cache is initially empty, show the contents of the cache at the end of
each pass, and compute the hit rate for a direct mapped cache.
5. Discuss the methods used to measure and improve the performance of the cache.
6. Explain the virtual memory address translation and TLB with necessary diagram.
7. Draw the typical block diagram of a DMA controller and explain how it is used for direct
data transfer between memory and peripherals.
8. Explain in detail about interrupts with diagram
9. Describe in detail about programmed Input/output with neat diagram.
10. Explain in detail about I/O processor.

POSSIBLE QUESTIONS
UNIT V
PART A
1. State advantages of a bus.
Versatility:
New devices can be added easily
Peripherals can be moved between computer systems that use the same bus standard
Low Cost:
A single set of wires is shared in multiple ways Manage complexity by partitioning the
design
2. State disadvantages of a bus.
It creates a communication bottleneck
The bandwidth of that bus can limit the maximum I/O throughput
The maximum bus speed is largely limited by:
The length of the bus
The number of devices on the bus
The need to support a range of devices with:
Widely varying latencies
Widely varying data transfer rates
3. What is the General Organization of a bus?
Control lines:
Signal requests and acknowledgments
Indicate what type of information is on the data lines
Data lines carry information between the source and the
destination:
Data and Addresses
Complex commands
4. How can you classify buses?
Major criteria are:
Purpose (Processor-Memory Bus, I/O Bus, Backplane Bus)
Clocking (Synchronous, Asynchronous)
Data Transfer Mode (Parallel, Serial)
5. Explain where synchronous buses can be used.
Advantage: involves very little logic and can run very fast
Disadvantages:
Every device on the bus must run at the same clock rate
To avoid clock skew, they cannot be long if they are fast
Hence can be used in

 processor-memory buses
Backplane buses when the bus length is short and there are few but high-speed I/O devices.
6. Explain where asynchronous bus can be used.
It can accommodate a wide range of devices
It can be lengthened without worrying about clock skew
It requires a handshaking protocol
Hence can be used in I/O buses.
7. What is meant by Vectored Interrupts?
A device requesting and interrupt may identify itself directly to the processor
It supplies a code to the processor that may represent the starting address of the interrupt
service routine for the device
In some cases only few bits are supplied and the remaining bits are fixed
To accommodate a larger number of devices, each code can be assigned to a group of
devices
The interrupt service routine can identify the device by ling the devices in the group
This arrangement implies that the service routine must always start at the same location
8. Explain the following parameters
1. Propagation Delay: The time taken for the signal to travel from one point to another
point on the bus.
2. Bus Skew: Skew occurs when two signals simultaneously transmitted from one source
arrive at the destination at different times. This is because different lines of the bus may have
different propagation delays.
3. Maximum propagation delay: In case of synchronous circuits bus skew is accounted as
part of the maximum propagation delay.
4. Address Decode Time: Time taken to decode address and generate a device-selected
signal if selected.
5. Setup Time and Hold Time: There is a critical period around the transition of the clock
state where input data should be stable. The period before the transition is called setup time. In case
of a negative edge-triggered flip-flop, this the period before the clock goes to 0 state. The period
after the transition is called the hold time. The setup time is also the time that data should be present
at the input of a circuit to be recognized.
6. Access Time: Time taken for the target to fetch requested data from DATAIN register and
place it on the bus, from the time the gating signal (Clock or Master Ready) is received by the
target.
9. What is meant by Interrupt nesting?
I/O devices should be organized in a priority structure
An interrupt request from a high priority device should be accepted while the processor
is servicing another request from a low priority device
The priority level of the processor is the priority level of the program it is executing

The processor accepts interrupts only from devices that have higher priority than its own
The processors priority is usually encoded in a few bits of the processor status word
It can be changed by a program instruction that writes into the PS
10. What is meant by debugging?
The debugger uses exceptions to provide trace mode and breakpoints
When a processor is operating in the trace mode, an exception occurs after every
instruction
Breakpoints: the program is interrupted at specific points selected by the user
An instruction called trap or software interrupt is used to specify breakpoints
11. What are the uses of interrupt in OS?
Application programs request services from the OS using traps (also called software
interrupts)
Most processors have several different software interrupts
Each software interrupts has its own vector code
These instructions can be used to call different parts of the OS
12. Define Multitasking.
The processor executes several user program at the same time
Each program runs for a short period of time called slice
Time slicing is one implementation of multitasking
13. Name the three states in a process.
Running
Runnable: program is ready for execution but is waiting to be selected by the scheduler
Blocked: the program is not ready to resume execution
14. Name the sources for exceptions.
There are five sources for exceptions
Two are external request lines: IRQ and FIQ (Fast Interrupt Request)
One software interrupt (SWI) Two exceptions that may be caused by abnormal conditions
during program execution
Exceptions are handled according to the following priority
Reset( highest priority)
Data abort
FIQ
IRQ
Prefetch abort
Undefined instruction (lowest priority)
Reset overrides all other conditions to bring the processor to a known starting condition
15. Define Bus protocol.
A bus protocol: set of rules that govern the behavior of the devices connected to the bus and
when to place information on the bus, assert control signals, ect

PART B
1. Explain the use of vectored interrupts in processors. Why is priority handling desired in interrupt
controllers? How do the different priority schemes work?
2. Explain how DMA transfer is accomplished with neat diagram.
3. Describe the functions of SCSI with a neat diagram.
4. Explain the functions to be performed by a typical I/O interface with a typical input or output
interface
5. Discuss the operation of any two input devices
6. Explain how I/O devices can be interfaced with a block diagram.
7. Explain in detail about interrupt handling
8. Explain in details about standard I/O interfaces.
9. Describe the working principles of USB.
10. Compare the characteristics of SCSI and PCI.