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PCM Modulator
PCM Modulator
5-1: Curriculum Objectives
1.
2.
3.
1.
bandwidth will also increase due to the increasing of the capacity of data.
From figure 5-2, the encoder utilizes n output terminals;therefore, we need to convert the parallel
data to serial data, which is the way that satisfies the data format of PCM modulation.
R4
R1
1
2 R 2 R 3 C1 C2
1
2 RC
(5-3)
In this experiment, we use IC CW6694 from Conwise to implement the PCM modulator. This IC
includes the circuits of PCM modulation and demodulation, however, we only discuss the
modulation in this chapter. The analog signal will pass through R 5 and input to pin 10, which
is the inverting input terminal. Then the signal will pass through R6 and feedback to pin 9.
Therefore, the structure of these two pins is an OPA structure and the expression of the gain is
AV =
R6
R5
(5-4)
Besides the input gain control of the modulation circuit, the sampler.quantizer and encoder are built
in the IC, therefore, we just need a few components to implement the PCM modulator. Master clock
(MC1k) is the operation frequency of the system, which is 2048 kHz square wave
frequency. Figure 5-4 is the circuit diagram of 2048 kHz square wave generator. From figure 5-5, we
use 2048 kHz crystal oscillator to match with the TTL inverter, which can produce the required
signal. Sample clock (SC1k) is the sample frequency, which supplies the required operation
frequency of the internal sampler. The sample frequency is 8 kHz, i.e. the sampler will sample the
input audio signal in every 0.125 ms. The sampling frequency is obtained by using the counter to
divide the 2048 kHz square wave signal by 256.
From figure 5-3, FSO and FS1 are the data format selection of PCM encoder as shown in table 5-1.
The data format selection of PCM encoder can encode the sample to 8-bit -Law format, 8-bit ALaw format or 16-bit digital data format. Besides, the above-mentioned format, the IC CW6694 also
provides with encode and decode of the continuous variable slope delta modulation (CVSD) format.
The CVSD format can be selected by pin FSO and FS1. However, CVSD is not included in this
chapter, therefore, the FS1 will be grounded and FSO will be in "HIGH" level. At this moment, the
output encode data format of PCM is 16-bit. When FSO is in "LOW" level.the output encode of PCM
is 8-bit. Pin RST is the reset pin of this IC.
From figure 5-3, the data output terminal of pin 26 of PCM modulator will connect to a buffer
U1: B, which is used for impedance matching. The reason is the output of PCM modulator is
bipolar junction transistor type not fieId effect transistor type; therefore, in order to prevent the load
effect, we need to connect a buffer at the output terminal for impedance matching.
Table 5-1 Output data format of PCM modulation.
FS0
FS1
Data Format
8 bits -Law
8 bits A-Law
16 bits Liner
8 bits CVSD
T2
T3
OP
500 Hz
250 mV
T4 and T6
T5 and T6
Table 5-2 Measured results of PCM modulator when J1 short circuit. (Continue)
Input Signals
T1
T2
T3
OP
1 kHz
250 mV
T4 and T6
T5 and T6
T2
T3
OP
500 Hz
250 mV
T4 and T6
T5 and T6
Table 5-3 Measured results of PCM modulator when J2 short circuit. (Continue)
Input Signals
T2
T3
OP
1 kHz
250 mV
T4 and T6
T5 and T6
2. From figure 5-3, what are the objectives of the second A741?
3. From the PCM modulator circuit, how to generate the 2048 kHz and 8 MHz square wave
signal?