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Date: 24.1.2015
P RAKESH, K. Dhanunjaya
Email: potluru.rakesh@gmail.com, hod.ece@audisankara.com
AUDISHANKARA COLLEGE OF ENGINEERING AND TECHNOLOGY GUDUR
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ISBN: 978-15-076833-85
Proceedings of International Conference on Recent Innovations in Engineering & Technology
Date: 24.1.2015
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ISBN: 978-15-076833-85
Proceedings of International Conference on Recent Innovations in Engineering & Technology
Date: 24.1.2015
+ 2t
= (t
.C
LH + t
HL)/2
While tnand LH and tnand HL represent the delay of each NAND gate for low to high and high to low output commutation respectively.
When delay cell is passed to output of third element of gate it becomes post turn state and all other state become turn state. Signal propagates
from input to output of the circuit through gates. Dummy cells are used to maintain load balancing in the circuit. The NAND gate is used to
reduce the hardware of circuit. Any gate can be constructed with help of NAND gate. It is very useful for construction of digital circuits.
Power consumption for the circuit constructed using NAND gate is reduced than existing method with help of 45nm technology.
Performance of circuit is also maintained same by removing the glitches and results obtained for both circuit. In 45nm technology leakage
current is reduced. It has higher density and higher switching performance. Power consumption of NAND gate is than the power
consumption of circuit with combination of AND and INVERTER gates.
III. IMPLEMENTATION OF CIRCUIT USING NOR GATE
Circuit is also neither implemented using NOR gate to reduce the power consumption of the circuit. Power consumption of NOR gate is
less than the power consumption of NAND gate and it increases the speed of operation of given circuit. Implementation of circuit using
universal gate reduce hardware its required delay is the length of time it takes for a signal to travel to its destination. Digital circuits and
digital electronics, the propagation delay, or gate delay, is the length of time which starts when the input to a logic gate becomes stable and
valid, to the time that the output of that logic gate is stable and valid. In gate delay transistors within a gate take a finite time to switch. This
means that a change on the input of a gate takes a finite time to cause a change on the output. Reducing gate delays in digital circuits allows
them to process data at a faster rate and improve overall performance. The difference in propagation delays of logic elements is the major
contributor to glitches in asynchronous circuits as a result of race conditions. The principle of logical effort utilizes propagation delays to
compare2015:
designs
implementing
the same logical statement. www.iaetsd.in
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ISBN: 978-15-076833-85
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Propagation delay increases with operating temperature, marginal supply voltage as well as an increased output load capacitance. The
latter is the largest contributor to the increase of propagation delay. If the output of a logic gate is connected to a long trace or used to drive
many other gates (high fan-out) the propagation delay increases substantially. Logic gates can have propagation delays ranging from more
than 10 ns down to the Pico second range, depending on the technology being used. In the case of an electric signal, it is the time taken for
the signal to travel through a wire. There are other different types of delay also source delay, network delay, insertion delay, transition delay,
path delay, intrinsic delay, phase delay. A digital delay line is a discrete element in digital filter theory, which allows a signal to be delayed
by a number of samples. If the delay is an integer multiple of samples digital delay lines are often implemented as circular buffers. This
means that integer delays can be computed very efficiently. Digital delay lines are widely used building blocks in methods to simulate room
acoustics, musical instruments and digital audio effects. The DCDL are designed glitch free and it is implemented in the application for the
better performance. A necessary condition to avoid glitching is designing a DCDL which have no-glitch in presence of a delay control-code
switching. This is a major issue at the DCDL-design level. This project carries out with the glitch free NAND based delay elements which
have good resolution so that the better performances can be obtained in the digital applications. Application used in this project was delay
locked loop(DLL).This paper contribute to the glitch free DCDL with the driving circuits for the delay control bits of the glitch free DCDL
implemented in the delay locked loop(DLL).
The following figure shows the block diagram of the existing NAND based DCDL. It consists of a NAND based lattice delay units which
is cascaded for larger delay lines in application
Fig.3. Block diagram of the conventional DCDL with one control bit
This conventional DCDL was designed with NAND cell as lattice structure .In the Fig.3 the cell which is denoted by A is the fast
input of the NAND gate. Gates denoted by D is the dummy cell for the load balancing. These delay elements are controlled by one bit
control code c to propagate the delay. When the delay control code C increased by 1, multiple propagation path within the DCDL structure
generates leads to more glitching in the delay line. The control bit Si = 0 (pass state), Si = 1 (turn state). In DCDL applications, to avoid
DCDL output glitching, the switching of delay control-bits is synchronized with the switching of the input signal. Glitching is avoided if the
control bits arrival time is lower than the arrival time of the input signal of the first DE which switches from or to the turn-state.
The structure proposed in this Fig.4 has control bits to control the delay elements .In thatAdenotes the fast input of the NAND gate,
D denotes the dummy cell for the load balancing. Two control bits Ti and Si are used to synchronize the arrival of the input and the arrival
of the control bits. It has three possible states.
Fig.4. Block diagram of the Glitch free DCDL with two control bit
Table 2
Logic states of each DE in proposed DCDLs
The DEs i<c with are in pass-state (Si =0, Ti =1). In this state the NAND 3 output is equal to 1 and the NAND 4 allows the signal
propagation in the lower NAND gates chain. The DE with i=c is in turn-state (Si=Ti=0). In this state the upper input of the DE is passed to
the output of NAND 3. The next DE (i=C+1) is in post-turn-state .In this DE the output of the NAND 4 is stuck-at 1, by allowing the
propagation, in the previous DE (which is in turn-state), of the output of NAND 3 through NAND 4. All remaining DEs (for i>C+1)
are again in turn-state .The three possible DE states of proposed DCDL and the corresponding Si and Ti values are summarized in Table 2.
The simulation results shows that the proposed NAND based DCDL confirms the glitch free propagation in the delay elements.
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IV. RESULTS
Conventional DCDL
Fig.6. Block diagram of the Glitch free DCDL with two control bit
The above Fig.6 the DEs i<c with are in pass-state (Si =0, Ti =1). In this state the NAND 3 output is equal to 1 and the NAND 4 allows
the signal propagation in the lower NAND gates chain. The DE with i=c is in turn-state (Si=Ti=0). In this state the upper input of the DE is
passed to the output of NAND 3. The next DE (i=C+1) is in post-turn-state .In this DE the output of the NAND 4 is stuck-at 1, by allowing
the propagation, in the previous DE (which is in turn-state), of the output of NAND 3 through NAND 4. All remaining DEs (for i>C+1) are
again in turn-state .The three possible DE states of proposed DCDL and the corresponding Si and Ti values are summarized in Table I. The
simulation results shows that the proposed NAND based DCDL confirms the glitch free propagation in the delay elements.
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Proposed
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Future scope
Circuit is can also be neither implemented using NOR gate to reduce the power consumption of the circuit. Power consumption of NOR
gate is less than the power consumption of NAND gate and it increases the speed of operation of given circuit. Implementation of circuit
using universal gate reduce hardware its requirement.
VI. REFERENCES
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Koh, S. John, I. Y. Deng, V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman, O. E. Eliezer, E. de-Obaldia, and P. T. Balsara,
All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS, IEEE J. Solid-State Circuits, vol. 39,
no. 12, pp. 22782291, Dec. 2004.
[3] R. B. Staszewski and P. T. Balsara, All Digital Frequency Synthesizer in Deep Submicron CMOS. New York: Wiley, 2006.
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[5] P. L. Chen, C. C. Chung, and C.Y. Lee, A portable digitally controlled oscillator using novel varactors, IEEE Trans. Circuits Syst. II,
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[6] P. L. Chen, C. C. Chung, J. N. Yang, and C. Y. Lee, A clock generator with cascaded dynamic frequency counting loops for wide
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[7] B. M. Moon, Y. J. Park, and D. K. Jeong, Monotonic wide-range digitally controlled oscillator compensated for supply voltage
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[8] J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65
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[9] K. H. Choi, J. B. Shin, J. Y. Sim, and H. J. Park, An interpolating digitally controlled oscillator for a wide range all digital
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