A THOUGHT EXPERIMENT

CMOS Inverter

5. COMPLEMENTARY MOS INVERTER

5.1. PMOS transistor as a LOAD
ID

+
vin
-

VGSL1
VGSD4
VGSL2

Io

VGSL3

VGSL4

vout

VGSD3
VGSD2
VGSD1
VDS

The 3-terminal PMOS pull-up device provides a family of non-linear load lines

5.2. CMOS Inverter

-

VDD

ViN - VDD
+ G
+
ViN
-

NMOS

IDD = IDL
NMOS DEVICE
VGSD = VIN
VDSD = VOUT

VOUT - V DD
D PMOS
D
S

+
+
VOUT
-

PMOS DEVICE
VGSL = VIN - VDD
VDSL = VOUT -VDD
CMOS Inverter

IMPACT ON INVERTER
VOLTAGE TRANSFER CHARACTERISTICS

Vin0

Vin5

VDD

Vin0

Vin1

Vin2
B

Vin1

Vin4

Vin2

Vin3

Vin3
Vin4

Vout

B
Vout

A Vin2
Vin1
VDD

CMOS Inverter

Vin3
D
0

Vtn

VDD/2

Vin

Vin4
E
VDD+Vtp

Vin5
VDD

CMOS Inverter

5.3. CMOS DC ANALYSIS

-

VDD

ViN - VDD
+ G
+
ViN
-

NMOS

Vin

GND

VOUT - V DD
D PMOS
D
S

+
+
VOUT
-

VDD

Vout
n+

n+

p+

p+

n+

ViN 0

Vin VGSD 0 VGSD VTD Driver Off

VGSL Vin VDD VDD VGSL VTL Load on
But TD OFF I DD 0 I DL 0
TL LIN/OFF
VGSL VTL VDSL 0

v out VDD VDSL VDD

VOH VDD

Notice that as with the depletion load inverter CMOS enables VOH to reach VDD
CMOS Inverter

CMOS: A Ratioless Logic

ViN VDD

VGSD Vin VTD TD ON

VDD

ViN - VDD
+ G
+
ViN
-

NMOS

VOUT - V DD
D PMOS
D
S

VGSL 0

TL OFF

I DL 0

I DD 0

I DD 0
VDSD v out 0
TD ON

+
+

TD LIN/OFF

VOUT
-

VOL 0

Note that unlike previous inverter types

CMOS inverter enables VOL to reach GROUND level.

CMOS is called RATIOLESS because the logic swing does not depend on
r VOL is independent of r .

For either ViN 0 or ViN VDD => ID= 0 => SPD=0

CMOS Inverter

TD SAT -TL LINEAR

-

VDD

ViN - VDD
+
+ G
ViN
-

NMOS

VOUT - V DD
D PMOS
D
S

+
+

I DD I DL

kD
2
V

V
in TD
2
2

vout VDD

k L Vin VDD VTL vout VDD

VOUT
-

v out VDD 2 2v out VDD Vin VDD VTL R Vin VTD 2 0

4Vin VDD VTL 4 r Vin VTD
2

**
Square root argument > 0 => TL LIN --> SAT transition occurs for Vin

satisfying

**
r Vin

VTD

**
Vin

CMOS Inverter

VDD VTL

TD SAT, TL SAT

kD
Vin VTD
2

k
L Vin VDD VTL
2

As in the case of depletion mode inverter the output voltage is undefined for this input
Vin* is given by
*
Vin

VDD VTL VTD r

1 r

Therefore, around Vin the transfer characteristic has infinite slope.

-

VDD

ViN - VDD
+ G
+
ViN
-

NMOS

VOUT - V DD
D PMOS
D
S

+
+
VOUT
CMOS Inverter

TD LIN - TL SAT
-

VDD

ViN - VDD
+ G
+
ViN
-

NMOS

Vout 2 k L
2
k D Vin VTD Vout

Vin VDD VTL

2
2

VOUT - V DD
D PMOS

+
+

**

1
Vin VDD VTL 2 0
r

Vin VTD 1 Vin VDD VTL 2

VOUT
-

2
Vout
2Vout Vin VTD

1
Vin*** VDD VTL

***

Vin*** VTD

Note that Vin = Vin =Vin

Therefore both load and driver device mode transitions occur for

CMOS Inverter

CMOS TRANSFER CHARACTERISTICS

Vout

Vout

VDD

V DD

NON-SYMMETRIC

SYMMETRIC

CURRENT

VDD
2

VTD

VDD -VTL V DD
Vin*

Vi
n

VT

TD OFF

V DD-VT VDD
VDD
2
SAT LIN
LIN/OFF

TL LIN/OFF LIN

SAT

V in

OFF

V in* = Vinv =(VDD / 2)

Symmetric CMOS inverter

VTL VTD

Under the following conditions the CMOS

VTC will be symmetrical

kL
Vin*

CMOS Inverter

kD
VDD

ASSYMETRIC OR SKEWED CMOS INVERTER

If =kp/kn 1, switching point will move from VDD/2
Called skewed gate
VDD
p
10
n

Vout

2
1
0.5

p
0.1
n

0
Vin

CMOS Inverter

VDD

Noise Margins

How much noise can a gate input see before it does

not recognize the input?

Output Characteristics
Logical High
Output Range

VDD

Input Characteristics
Logical High
Input Range

VOH
NMH
VIH
VIL

Indeterminate
Region

NML
Logical Low
Output Range

VOL
GND

CMOS Inverter

Logical Low
Input Range

CMOS NOISE MARGINS

TD SAT, TL LIN

Vin VDD VTL 2 r Vin VTD 2

r 1Vin VTL rVTD VDD
1
2
2
Vin VDD VTL r Vin VTD

Vout Vin VTL

dVout
1
dVin

*
Find ViL* VOH
numericall y

Note that for Vin Vin*

dVout

dVin

CMOS Inverter

5.4. CMOS TIME RESPONSE

DC analysis tells us Vout if Vin is constant

Transient analysis tells us Vout(t) if Vin(t) changes
Requires solving differential equations

Input is usually considered to be a step or ramp

From 0 to VDD or vice versa

Vin(t)

Vout(t)
Cload
Idsn(t)

CMOS Inverter

DELAY DEFINITIONS

tpdr: rising propagation delay

From input to rising output
crossing VDD/2
tpdf: falling propagation delay
From input to falling output
crossing VDD/2
tpd: average propagation delay
tpd = (tpdr + tpdf)/2
tr: rise time
From output crossing 0.2
VDD to 0.8 VDD
tf: fall time
From output crossing 0.8
VDD to 0.2 VDD
CMOS Inverter

INVERTER DELAY CALCULATION

Solving differential equations by hand is too hard

SPICE simulator solves the equations numerically
Uses more accurate I-V models too!

But simulations take time to write, may hide insight

We will use simple equations that are inaccurate but
provide insight
2.0

1.5

1.0
(V)

Vin

tpdf = 66ps

tpdr = 83ps

Vout

0.5

0.0

0.0

200p

400p

600p

800p

1n

t(s)

CMOS Inverter

Simple Case Example:

Resistive Pull-Up Inverter
Transient Response

CMOS Inverter

INVERTER CAPACITANCES
Example: Resistive load inverter
Poly Load
Output

Vss=Vs=0

VG

n
p

VDD

CGS

n
CGB

Ci
CDS

Field
Oxide

List of Parasistic MOS Inverter Capacitances

1. Drain Junction Capacitance of driver CDS Cod
2. Interconnect Capacitance Ci
3. Capacitance Associated with load Col
4. Load Inverter Capacitance F=Fan Out FCin
The inverter must therefore drive a capacitance CL Cod Col Ci FCin
CMOS Inverter

INPUT CAPACITANCE
Poly Load
Output

Vss=Vs=0

VG

n
p

V DD

VDD

CGS

n
CGB

Ci
CDS

Field
Oxide

C in

The input capacitance Cin of the MOS inverter is the gate capacitance of the driver

Cin CGS CGB CGD WL

ox
tox

Capacitance at the output of a Resistive load MOS inverter

CL Cod Col Ci FCin

CMOS Inverter

RISE AND FALL TIMES

Rise (toff or tr) and Fall Time (ton or tf)
Rise time (Turn-off Time ) is approximately the time
that the output voltage of the inverter
takes to increase from VOL to VOH

The Fall time (Turn-on -time ) is approximately the

time that the output voltage
takes to settle down from VOH to VOL
These transient times are governed by the capacitances and resistances in the circuit and
by the currents charging and discharging them to the desired voltage levels.

t = C(V)/<I>
where < I > denotes average current

CMOS Inverter

CMOS Inverter

RISE TIME OF RESISTIVE PULL-UP

INVERTER

I coff

MOSFET OFF

VDD

v DD

1 v
VDD
2R
0
2
out

VDD

v out
dv out
R

v DD
2R

Then,
tr

In general the rise time is given by

C L VDD
2RC L
VDD /2R

t r 2RC L

tr = 2.3 RC
tr is essentially governed by the pull-up conductance and by the load capacitance CL

CMOS Inverter

FALL TIME OF A
RESISTIVE LOAD INVERTER
Fall Time
Fall time is affected by all 3 devices including the pull-down
The non linear behavior of the MOSFET requires piecewise linear
calculation of the solution by solving the relevant differential
equation with appropriate boundary conditions.
Instead Shockley model uses average current and plugs it into

t = C(V)/<I>
2 2

Icon k VDD VT

VT VDD

6VDD
2R
1

tf

6CLVDD
kD

2 VT
V V 2 3VDD
DD
T

DD

CMOS Inverter

CMOS INVERTER INPUT AND OUTPUT

CAPACITANCES
Vin
GND

CGSn

CGSp

Vout
n+

p+

n+

CGBn

CDSn

CDSp

n
Cin.n CGSn CGBn CGDn Wn L

ox

Cin. p CGSp CGBp CGDp W p L

tox

ox

VDD
p+

CGBp

But Wp~2Wn

Cin.CMOS Cin. p Cin.n 3Wn L

tox

ox
tox

CL 3CDS . NMOS Ci 3FCin. NMOS

Input and output capacitance of a CMOS inverter
CMOS Inverter

n+

Fall time
VDD

Rise time
VDD

VinL=0
CMOS Inverter

CMOS FALL TIME

In CMOS the turn-off time is totally governed by the load, whereas the turn-on time is
totally governed by the driver. Using Shockleys approach
V DD V TD

c(on)

V TD

k V
2
D

V TD
DD

dV O

V DD V TD

k D 2 V DD V TD V O dVo

dV

k V
V
D

DD

VDD

t = C(V)/Icon
resulting in
2

on

3CV
k V V 2V
DD

DD

TD

CMOS Inverter

DD

V TD

DD

V TD 2V DD V TD
3

CMOS RISE TIME

VDD VT L

k
2 V -V dV
2

DD

c(r)

TL

VDD

VDD VT L
VDD

k L V DD-V TL (V -V DD )
O

dV

k V -V 2V
3
V
2

DD

TL

DD

VDD

+ V TL

3CV
k V -V 2V
DD

VinL=0

DD

DD

TL

DD

-V TL

One obtains an identical equation

form for toff by replacing kD by kL and
VTD by VTL

CMOS Inverter

dV

IMPORTANT SIMPLIFICATIONS

Note that when VDD>>VT than

ton = toff= C/kVDD
If kL = kD (symmetric inverter) then ton = toff and the time
response of CMOS inverter will be symmetric as well
The inverter propagation delay is than
tp= (ton+toff)/2= C/kVDD

CMOS Inverter

CMOS FANOUT and CMOS LOGIC GATE RESPONSE

CMOS FANOUT
limited by maximum propagation delay tpmax that is allowed

tpmax= Cmax/kVDD

Cmax= tpmax kVDD

If input capacitance of load inverter is Cin than

Fmax=Cmax/Cin =

tpmax kVDD / Cin

CMOS LOGIC GATE DYNAMIC RESPONSE

2

3CV
nk V -V 2V

DD

DD

DD

TD

3CV
t
mk V -V 2V

DD

-V TD

DD

TL

DD

-V TL

Where nkD and mkL are the effective transconductance parameters

of the NMOS path and PMOS paths.
The capacitance C must include the effective Drain capacitances of NMOS and PMOS
transistors
CMOS Inverter

5.5. POWER DISSIPATION SOURCES

Ptotal = Pdynamic + Pstatic

Dynamic power: Pdynamic = Pswitching + Pshortcircuit

Switching load capacitances
Short-circuit current

Static power: Pstatic = (Isub + Igate + Ijunct )VDD

Subthreshold leakage
Gate leakage
Junction leakage
[Contention current (two terminal pull-ups)]

CMOS Inverter

POWER IN CIRCUIT ELEMENTS

PVDD t I DD t VDD

VR2 t
PR t
I R2 t R
R

dV
EC I t V t dt C V t dt
dt
0
0
VC

C V t dV 12 CVC2
0

CMOS Inverter

CHARGING A CAPACITOR

When the gate output rises

Energy stored in capacitor is
2
EC 12 CLVDD

But energy drawn from the supply is

EVDD I t VDD dt CL

dV
VDD dt
dt

VDD

dV C V
Half the energy from VDD is dissipated in the pMOS transistor
as heat, other half stored in capacitor
When the gate output falls
Energy in capacitor is dumped to GND
Dissipated as heat in the nMOS transistor
CLVDD

2
L DD

CMOS Inverter

SWITCHING POWER & ACTIVITY

FACTOR

Suppose the system clock frequency = f

Let fsw = af, where a = activity factor
If the signal is a clock, a = 1
If the signal switches once per cycle, a =

Dynamic power:

Pswitching a CVDD 2 f
VDD
iDD(t)

fsw

CMOS Inverter

Short Circuit Current

When transistors switch, both nMOS and pMOS

networks may be momentarily ON at once
Leads to a blip of short circuit current.
< 10% of dynamic power if rise/fall times are
comparable for input and output
Edp=VDD (Ipeak.ton)/2+ VDD (Ipeak.toff)/2=> Pdp= VDD Ipeak f tp

CMOS Inverter

POWER DISSIPATION
STATIC POWER :
Due to Leakage:

Ps VDD.ILeakage

DYNAMIC POWER DISSIPATION:

Due to load capacitance
Each half cycle the energy stored on the C is with f = frequency
2
CVDD
E
1
2
Ec
; P
and
Pc CVDD
f
2

2f

Due to Direct path transition currents

Edp=VDD (Ipeak.ton)/2+ VDD (Ipeak.toff)/2=> Pdp= VDD Ipeak f tp

CMOS Inverter

LATCHUP
Latchup results from parasitic bipolar transistors that when turned on
can short VDD to ground via the substrate. When one of the two BJTs
gets forward biased it feeds the base of the other BJT increasing the
current until the circuit burns out.To minimize risk of latch-up the
resistances Rnwell and Rpsubs must be minimized. This can be achieved
by placing many contacts (guard rings) around large current handling
devices.
-

VD D
VDD
p+

n+

n+

p+

p+

n-well

Rnwell

n+

p-sourceViN

Rpsubs

n-source
p-substrate
(a) Origin of latchup

- VDD
+ G
+

Rnwell
Rpsubs

(b) Equivalent circuit

CMOS Inverter

ViN
-

VDD
S

VOUT - V DD
D PMOS
D
C

NMOS

+
+

VOUT
-

CMOS WITH LEAKY GATES

We represent the leaky gate with a resistor For Vin =0 PMOS Linear NMOS off
ViN - VDD

vout VDD 2 vout

k L Vin VDD VDTL vout VDD

2
X

+
+ G
ViN
-

Therefore Vout is not VDD

For Vin= VDD PMOS OFF, NMOS LIN OFF
Therefore VoutL = 0V

CMOS Inverter

VOUT - V DD
D PMOS

+
+

D
C

NMOS

VDD

VOUT
-