quiz3 FIFOs and paths: SP15: EE-287 Sec 02 - ASIC CMOS Design

2/16/15, 10:34 PM

quiz3 FIFOs and paths

Due Feb 18 at 10pm

Points 10

Questions 10

Available until Feb 18 at 10:30pm

Time Limit 30 Minutes

Allowed Attempts 2

Take the Quiz Again

Attempt History
LATEST

Attempt

Time

Score

Attempt 1

10 minutes

8.27 out of 10

Score for this attempt: 8.27 out of 10

Submitted Feb 16 at 10:33pm
This attempt took 10 minutes.

Question 1

0.67 / 1 pts

Which of the following are important to ASIC product success? Select all that apply.

Correct!

Customer documentation

Correct!

performance

Correct!

Marketing definition
Package color

Correct Answer

debug

Correct!

power

Correct!

factory yield
simulation time

Correct!

schedule

Correct Answer

Internal documentation

Correct Answer

Test patterns

Question 2

1 / 1 pts

Which terms are part of the long path equation?

IH
Correct!

Skew

Correct!

LD

https://sjsu.instructure.com/courses/1137028/quizzes/1060926

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quiz3 FIFOs and paths: SP15: EE-287 Sec 02 - ASIC CMOS Design

Correct!

C->Q

Correct!

IS

Question 3

2/16/15, 10:34 PM

1 / 1 pts

Which terms are part of the race equation?

Correct!

Skew

Correct!

IH
IS

Correct!

LD

Correct!

C->Q

Question 4

1 / 1 pts

Which edge of the clock is the best to use?

Correct!

The one everyone else is using

The one with the best flip-flops
Falling
Rising
Falling to construct ripple counters

Question 5

1 / 1 pts

A FIFO is typically constructed using a memory with how many ports?

5
Correct!

2
3
1
4

https://sjsu.instructure.com/courses/1137028/quizzes/1060926

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quiz3 FIFOs and paths: SP15: EE-287 Sec 02 - ASIC CMOS Design

2/16/15, 10:34 PM

0 / 1 pts

Question 6
A long path fails with only one clock pulse

False
You Answered

True

0.6 / 1 pts

Question 7
Pick the best match for the list below:

You Answered

1/2 Flip Flop

Mono-stable multi-vibrator

Correct Answer

Latch Correct Answer

Correct!

Flip Flop

Master-Slave Correct Answer

Correct!

Reset

Asynchronous Correct Answer

Correct!

Slave delay

C->Q Correct Answer

Glitch Memory

Latch Correct Answer

You Answered

Correct Answer

J-K Flip Flop Correct Answer

Other Incorrect Match Options:

Mono-stable multi-vibrator
slave-slave
master-master

Question 8

1 / 1 pts

A FIFO is a synchronizer.

False
Correct!

True

https://sjsu.instructure.com/courses/1137028/quizzes/1060926

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quiz3 FIFOs and paths: SP15: EE-287 Sec 02 - ASIC CMOS Design

Question 9

2/16/15, 10:34 PM

1 / 1 pts

If all the transistors are the same sizes, which gate is faster?

MUX
XOR
NOR
Correct!

NAND

Question 10

1 / 1 pts

In a CMOS NAND gate, the N transistors are arranged:

Congruence
In mirror image
Binary weighted
Correct!

Series
Parallel

Quiz Score: 8.27 out of 10

https://sjsu.instructure.com/courses/1137028/quizzes/1060926

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