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Abstract
A simplified space-vector pulse width modulation
(SVPWM) scheme for a 3-level inverter is presented. The
method involves the mapping of reference vector in the
space vector diagram of 3-level inverter to a 2-level inverter.
60 coordinate system is used to represent space vectors instead of using cartesian coordinate system. In 60 coordinate system only integer coordinates are involved. So the
computational complexity is reduced. The proposed scheme
is simulated and verified using Xilinx system generator software.
1. Introduction
Multilevel inverters are widely used in industrial drive
applications due to their ability to produce waveforms with
improved harmonic spectrum [1, 2]. Multi level inverters
can produce variable voltages and frequencies from discrete
voltage levels using pulse width modulation (PWM) strategies. Several techniques have been developed for the implementation of PWM [3, 4]. The two main methods are Sine
triangle Pulse width Modulation (SPWM) and Space Vector Pulse Width Modulation (SVPWM) [5, 6]. SPWM is
the simple and widely used scheme which generates PWM
signals by comparison of level shifted triangular carrier signals with a sinusoidal reference waveform [7, 8]. SVPWM
involves synthesising of reference sinusoidal voltage by
switching amoung the nearest three voltage spacevectors.
SVPWM is the best technique to implement PWM due to
following advantages. 1) higher o/p voltage for the same
dc-bus voltage 2) lower switching losses and 3) Better harmonic performance.
Implementation of SVPWM scheme involves 1.sector
identification 2.determination of nearest voltage space vectors to be switched 3.determination of duration of each
switching voltage space vectors 4.determination of an op-
2. Proposed Scheme
SVPWM involves synthesising of reference sinusoidal
voltage(Vref ) by switching amoung the nearest three voltage space vectors. In the proposed work 60 coordinate
system is used to represent the space vectors. Suppose
Va , Vb and Vc represents the instantaneous amplitudes of
three phase reference sinusoid, 60 coordinates (m, n) of
Vref can be found using the equations given below,
Vm = Va Vb
(1)
Vn = Vb Vc
(2)
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14th National Conference on Technological Trends | 30 - 31, August 2013 | College of Engineering Trivandrum
Sector
1
2
3
4
5
6
Vmm 0
1
0
0
0
1
1
Vnm 0
1
1
1
0
0
0
|Vmm | |Vnm |
0
1
0
1
Vmm = Vm 0
(4)
Vnm = Vn 1
(5)
The sector to which the Vref m belongs can be found using Table. 1
Once the sector of operation is identified phase voltage switching timings of switching vectors can be found
as in Table. 2. It should be ensured the selected vectors are
switched in an optimum sequence so that only one switching occurs when the inverter changes its state.
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14th National Conference on Technological Trends | 30 - 31, August 2013 | College of Engineering Trivandrum
Sector
1
2
3
4
5
6
T1
Ts Vmm
Ts (Vmm + Vnm )
Ts Vnm
Ts Vmm
Ts (Vmm + Vnm )
Ts Vnm
T2
Ts Vnm
Ts Vmm
Ts (Vmm + Vnm )
Ts Vnm
Ts Vmm
Ts (Vmm + Vnm )
Simulink provides a powerful high level modeling environment for DSP systems, and consequently is idely used
for algorithm development and verification. System Generator maintains an abstraction level very much in keeping
with the traditional Simulink block sets, but at the same time
automatically translates designs into hardware implementations that are faithful, synthesizable, and efficient [18].
The implementation is faithful in that the system model
and hardware implementation are bit-identical and cycleidentical at ample times defined in Simulink. The implementation is made efficient through the instantiation of intellectual property (IP) blocks that provide a range of functionality from arithmetic operations to complex DSP functions [18]. These IP blocks have been carefully designed
to run at high speed and to be area efficient. In System
Generator, the capabilities of IP blocks have been extended
transparently and automatically to fit gracefully into a system level framework. For example, although the underlying IP blocks operate on unsigned integers, System Generator allows signed and unsigned fixed point numbers to be
used, including saturation arithmetic and rounding. Userdefined IP blocks can be incorporated into a System Generator model as black boxes which will be embedded by the
tool into the HDL implementation of the design.
3. FPGA Implementation
Field-Programmable Gate Arrays (FPGAs) have become
key components in implementing high performance digital
signal processing (DSP) systems [17]. The memory bandwidth of a modern FPGA far exceeds that of a microprocessor or DSP running at clock rates two to ten times that of the
Before developing the hardware circuit for power, control and isolation circuit based on the FPGA, the entire
system is generated with the aid of simulation package
simulink/system generator for FPGA in order to verify the
pulses and the patterns of the output pulses. The creation of
a DSP design begins with a mathematical description of the
operations needed and concludes with a hardware realization of the algorithm [18]. The hardware implementation is
rarely faithful to the original functional description instead
it is faithful enough. The challenge is to make the hardware
area and speed efficient while still producing acceptable re-
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14th National Conference on Technological Trends | 30 - 31, August 2013 | College of Engineering Trivandrum
Inverter-1
OFF
OFF
ON
Inverter-2
OFF
ON
ON
VA0 O
0
Vdc /2
Vdc
Figure 7. Switching signals generated for 2-level operation: Top 3traces for Inverter-1 & Lower 3-traces for Inverter-2 (Modulation
index 0.25)
Figure 8. Switching signals generated for 3-level operation: Top 3traces for Inverter-1 & Lower 3-traces for Inverter-2 (Modulation
index 0.75)
6. Conclusion
This paper proposes a method for the implementation of
SVPWM in FPGA. Since the SVPWM method is based on
the 60 coordinate system instead of cartesian coordinate
system computational complexity is greatly reduced. The
scheme is simulated for a 3-level inverter. 3-level inverter is
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14th National Conference on Technological Trends | 30 - 31, August 2013 | College of Engineering Trivandrum
References
[1] A. Nabae, I.Takahashi, and H. Akagi, A new neutral
point clamped pwm inverter, IEEE Transactions on Industry Applications, vol. 1A-17, no. 5, pp. 518523, September/October 1981.
[2] Heinz Willi Van Der Broeck, Hans-Christoph Skudelny,
and Georg Viktor Stanke, Analysis and realization of a
pulsewidth modulator based on voltage space vectors, IEEE
Transactions on Industry Applications, vol. 24, no. 1, pp.
142150, January/February 1988.
[3] J. Holtz, Pulse width modulationa survey, IEEE Trans.
Ind. Electron., vol. 39, no. 5, pp. 410420, Dec. 1992.
[4] W. Yao, H. Hu, and Z. Lu, Comparisons of space-vector
modulation and carrier based modulation of multilevel inverter, IEEE Trans. Power Electron., vol. 23, no. 1, pp.
4551, Jan. 2008.
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