K. N.

Toosi University of Technology

Digital Electronics
Chapter 10. BiCMOS Logic
By:
B
y: FFARHAD
ARHAD FARADJI,
FARA
ADJI, Ph.D.
Ph.D.
Assistant Professor,,
Electrical and Computer Engineering,
Engineering
K. N. Toosi University of Technology
http://wp.kntu.ac.ir/faradji/DigitalElectronics.htm
Reference:
DIGITAL INTEGRATED CIRCUITS: ANALYSIS and DESIGN, 2005,
John E. Ayers
1

10.1. Introduction

KNTU

CMOS is preferred for most applications because of:

its low standby dissipation,
high packing density,
rail-to-rail voltage swing,
and excellent speed.
Bipolar circuitry
try outperforms CMOS in terms
terrms of off-chip
offf-cchip data
d rates.
Bipolar-CMOSS (BiCMOS)
of
(BiCMOS) logic
logic was
was developed
developed to achieve
achievve advantages
a
both types of logic
lo
ogic gates.
gaates.
High-performance
based on Si and
ance BiCMOS circuits have been developed b
SiGe technology.

Digital Electronics

Chapter 10. BiCMOS Logic

10.1. Introduction

KNTU

A number of different versions of BiCMOS logic

gates are available.
They all share salient features of inverter shown.
2 important design features of this circuit are:
1. CMOS-type
ype logic circuitry and
2. a totem-pole
pole output
ou
utput usingg 2 npn
npn BJTs.
BJTTs.
CMOS logic circuitry
rcu
uitry provides
provides low
low standby
stand
dby
atio
on.
power dissipation.
BJTs at output provide
with
d superior
i performance
f
h
highly capacitive loads.
Packing density of BiCMOS can be excellent because relatively large BJTs
are only needed to drive output connections.
BiCMOS ICs are really just CMOS on inside.

Digital Electronics

Chapter 10. BiCMOS Logic

10.2. Voltage Transfer Characteristic

KNTU

With logic zero (0 V) at input:

MN1 and MN3 are cut off.
MP1 is linear.
VB of QP is equal to VDD.
MN2 is linear.
ear.
QO is cut off.
QP is forward
warrd active.
acttive.

Digital Electronics

Chapter 10. BiCMOS Logic

10.2. Voltage Transfer Characteristic

KNTU

9 With logic one (VDD V) at input:

MN1 and MN3 are linear.
MP1 is cut off.
VB of QP is equal to 0.
QP is cut off
MN2 is cutt off.
QO is forward
warrd active.
active.

Digital Electronics

Chapter 10. BiCMOS Logic

10.2. Voltage Transfer Characteristic

KNTU

Logic swing of conventional BiCMOS circuits

is about 1.4 V less than supply voltage:

Drive to lower supply

makes
l voltages
lt
k
this 1.4-V degradation increasingly important.
With a VDD = 1.8 V, logic swing of BiCMOS is a mere 0.4 V.
Conventional BiCMOS circuits are undesirable for VDD < 2.5 V.

Digital Electronics

Chapter 10. BiCMOS Logic

10.3. Rail-to-Rail BiCMOS

KNTU

A limitation of BiCMOS is reduced

logic swing compared to CMOS.
Simplest way to achieve rail-to-rail
operation is to use a parallel CMOS
output driver.
Dynamic rail-to-rail
performance
to-rail p
erformancce
becomes limited
ted
d by
by MOSFETs.
MOSFETs.
VOOUT
V
VDDDD :
For VDD -VBEA V
UT V
QP is cut off
off.
QP provides no benefit to dynamic performance.
For  VOUT VBEA :
QO is cut off.
QO provides no benefit to dynamic performance.

Digital Electronics

Chapter 10. BiCMOS Logic

10.3. Rail-to-Rail BiCMOS

KNTU

With a VDD = 1.8 V, BJTs conduct only

for 0.7 V VOUT 1.1 V.
This version offers no real advantage
over CMOS for VDD < 2.5 V.

Digital Electronics

Chapter 10. BiCMOS Logic

10.3. Rail-to-Rail BiCMOS

KNTU

9 Another strategy to achieve rail-to-rail

BiCMOS is to use passive shunts.
9 2 passive (resistive) shunts are placed
across BE junctions of BJTs.
9 Shunt resistorr R1 allows VOUT to swing
all way to VDDD while QP is cut off.
offf.
9 Dynamically, this
thiis means
means that
that load
load capacitance
capaccitance
or VOOUT
thrrough R1 ffor
must charge through
U T > VD
DD
D - VB
BEA
E A.
9 R2 allows output to swing allll way to 0.

Digital Electronics

Chapter 10. BiCMOS Logic

10.3. Rail-to-Rail BiCMOS

KNTU

Other versions of rail-to-rail BiCMOS exist.

They all suffer from this same basic limitation.
It appears that shunting BJT is not answer!
BJTs cannot boost dynamic performance of gate
unless they are
re conducting.
Idea behind shunting
hu
untting is
is that
that it
it allows
allo
ows BJTs
BJTs
hille shu
unt elements
elemen
nts allow
allow VBE to
to turn off, while
shunt
approach 0.
A limitation of BiCMOS is its use in
low-voltage circuits.

Digital Electronics

Chapter 10. BiCMOS Logic

10

10.3. Rail-to-Rail BiCMOS

KNTU

BiCMOS has been used in dual voltage

applications.
Dual voltage is:
using a low voltage supply for CMOS core
to minimize
nimize power dissipation,
using a higher
ghe
er voltage
voltaage supply
su
upply ffor
or
BiCMOS output
outtput drivers
driverrs
for greater
eaater logic
logic swing
swing and
and
improved
d off-chip
ff hi bit rates.
t
This practical solution has been
implemented in commercial products
such as microprocessors.

Digital Electronics

Chapter 10. BiCMOS Logic

11

10.4. Logic Design

KNTU

NAND function is formed by

paralleling p-channel MOSFETs and
forming series combinations
of n-channel MOSFETs.
If either input goes low:
associated
d MP1 conducts.
MN2 conducts.
ucts..
associated
d MNN11 iss ccut
ut o
off.
ff.
associated
d MNN33 is
is ccut
ut off.
off.
QP conducts.
cts
QO is cut off.
Output will go high.

Digital Electronics

Chapter 10. BiCMOS Logic

12

10.4. Logic Design

KNTU

9 If both inputs are logic one:

Both MP1 are cut off.
Both MN1 conduct.
Both MN3 conduct.
MN2 is cut off.
QP is cut off.
QO conducts.
ctss.
output will
ill go
go low.
low
w.

Digital Electronics

Chapter 10. BiCMOS Logic

13

10.4. Logic Design

KNTU

M-input BiCMOS NAND gate

requires:
M p-MOSFETs in parallel,
2 series combinations
of M n-MOSFETs,
2 BJTs,
discharge MOSFE
MOSFET
ET MNN22.
M-input BiCMOS
MO
OS NAND
NAND gate
gate
requires (3M+1)
+1)) MOSFETs
MOSFETs and
and
2 BJTs.

Digital Electronics

Chapter 10. BiCMOS Logic

14

10.4. Logic Design

KNTU

2-input BiCMOS NOR gate is implemented by

placing p-MOSFETs in series and
forming parallel combinations
of n-MOSFETs.
If either input goes high:
associated
d MP1 is turn off.
MN2 is cutt off..
associated
d MNN11 conducts.
conducts.
associated
d MNN33 conducts.
conducts.
QP is cut off.
off
QO conducts.
Output will go low.

Digital Electronics

Chapter 10. BiCMOS Logic

15

10.4. Logic Design

KNTU

If both inputs are logic zero:

Both MP1 conduct.
Both MN1 are cut off.
Both MN3 are cut off.
MN2 conducts.
QP conducts.
cts.
QO is cut off.
offf.
output will
ill go
go high.
higgh.
MOS NOR gate requires
M-input BiCMOS
(3M+1) MOSFETs and 2 BJTs,
like M-input NAND gate.
More complex ANDORINVERT functions
may be implemented in BiCMOS by
forming more complex pull-up and
pull-down networks.
Digital Electronics

Chapter 10. BiCMOS Logic

16