AKG Int Journal Tech Vol 6 No 1

AKGEC
INTERNATIONAL JOURNAL
OF TECHNOLOGY
January-June 2015
Vol. 6, No. 1
Design of a Digital Clock Using Very High Speed IC Hardware

Description Language
Usman Sammani Sani and Ibrahim Haruna Shanono
Application of Queuing Model: With Special Reference to Construction

and Business Bank Adama Branch Ethiopia
Dr. Kamlesh Kumar Shukla and Dr. Girish Kumar Painoli
Hybrid Method For Automatically Filling of the Chemical Liquid

into Bottles Using PLC & SCADA
Jagat Dhiman and Er. Dileep Kumar
10
Friction Stir Welding: Tool Material and Geometry

A. Chandrashekar, B.S. Ajay Kumar and H.N. Reddappa
16
Determination of Natural Frequency of a Turning Specimen

Subjected to Random Excitation
M.Z. Hussain, Dr. A.A. Khan and Dr. M. Suhaib
21
Circuit Architecture for Photon Counting Pixel Detector

with Threshold Correction
Dr. Amit K. Jain
26
Public Sector Comparator: A Useful Decision Making Tool in Infrastructure

Akhil Damodaran
31
Variation of the Capacitance of Supercapacitors with Current and Frequency

36
An Efficient Carry Select AdderA Review

Rishabh Rai and Rajni Parashar
39
FPGA Implementation of Digital Modulators

Pronnati and Dr. K.K. Tripathi
46
Design and Implementation of Inset feed Square Patch Micro strip Antenna
Array for WLAN Application Using Dielectric Substrate
Priya Upadhyay, Dr. Ranjit Singh and Arundhati Tiwari
50
A Novel Method of Extracting Mark-Hauwink-Sakurada

Parameters from Viscosity Data
Dr. Aniruddh Singh and Mohammad Asad
55
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January - June 2015
Vol. 6, No. 1
ISSN 0975-9514
AKGEC International Journal of Technology

CONTENTS
Design of a Digital Clock Using Very High Speed IC Hardware
Description Language
Application of Queuing Model: With Special Reference to

Construction and Business Bank Adama Branch Ethiopia
Hybrid Method For Automatically Filling of the Chemical Liquid

into Bottles Using PLC & SCADA
10

A. Chandrashekar, B.S. Ajaykumar and H.N. Reddappa
16
Determination of Natural Frequency of a Turning Specimen

Subjected to Random Excitation
M.Z. Hussain, Dr. A.A. Khan and Dr. M. Suhaib
21
Circuit Architecture for Photon Counting Pixel Detector

with Threshold Correction
Dr. Amit K. Jain
26
Public Sector Comparator: A Useful Decision Making

Tool in Infrastructure
Akhil Damodaran
31
Variation of the Capacitance of Supercapacitors with

Current and Frequency
36

39

46
50
Dr. R.K. Agarwal
Design and Implementation of Inset feed Square Patch Micro

strip Antenna Array for WLAN Application Using Dielectric Substrate
Editor-in-Chief
Dr. Ranjit Singh

55
Patron-in-Chief

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ii
DESIGN OF A DIGITAL CLOCK
Design of a Digital Clock Using Very High Speed IC

Hardware Description Language
Usman Sammani Sani1 and Ibrahim Haruna Shanono2
Bayero University, Kano, P.M.B. 3011, Nigeria
1
usmanssani@live.com, 2ihshanono.ele@buk.edu.ng
clock and other components. The seconds count after each

clock pulse till it reaches 59 and on the next system clock pulse
it resets back to 0 and then continues. At the time it resets to 0,
it triggers the minute. Each time the seconds reset to 0, the
minute is being triggered and when it reaches 59, it triggers the
hour, the next time it is triggered by the seconds.
Abstract -- Very High Speed IC Hardware Description Language

(VHDL) is one of the modern languages used in designing digital
circuits. It can be used in programming Field Programmable
gate arrays (FPGAs) and Application Specific Integrated Circuits
(ASICs).This paper presents the design of a digital clock using
Very High Speed Hardware Description Language in a Xilinx
ISE 10.1 environment. The designed clock has the functionalities
time, alarm, stopwatch and date. The clock format can be changed
from 24 hours to 12 hours and vice versa. After the design, testing
was done on a Spartan-3- FPGA and all units were found to be
performing the desired functions.
Five switches stop, settime, sethr, setmin and inct

are used for resetting time. To achieve this, the clock has to be
stopped by first setting the stop switch to logic 1 followed
by the settime switch. Then either sethr or setmin can
be set high to reset the hour and minute respectively. If sethr is
set high, it means that the hour will be changed. The next thing
to do is to press the inct button (increment button). User
can continue incrementing it up to the value of 23 after which
it resets to 0 and the incrementing process can be continued.
Keywords: VHDL, Programmable Logic Devices, FPGA
I. INTRODUCTION
THERE are different digital logic integrated circuits available
in the market. These can be used in designing circuits by circuit
designers. But as systems become complex, there may be some
functions that cannot be performed by these readily available
ICs. Hence the use of VHDL for circuit design comes in handy
[1]. VHDL is a high level programming language which is
powerful in programming Programmable Logic devices such
as field programmable gate arrays, generic array logic (GAL)
and Programmable array logic [2],[3]. For the programmable
logic devices to be programmed the codes must pass through
stages such as synthesis, timing simulations, place and route
and bit file generation [4]. This work will be based on design
on an FPGA. The advantage of designing digital circuits used
for instrumentation and control using it is that the circuits can
be modified even after reaching the market due to the
reprogrammability of FPGAs thereby enhancing rapid
prototyping [5]. There are many manufacturers of FPGA such
as Xilinx; Inc, Altera Corporation, Perfect Parts Corporation,
Achronix Semiconductor Corporation, Atmel Corporation [6],
[7] etc. FPGAs contain programmable logic elements called
Logic elements LEs and a hierarchy of reconfigurable
interconnects that allow Les to be connected physically [5].
In this work, a Spartan-3 FPGA development board is used.
The designed circuit has the following features:
The same principle is used to reset minutes using setmin.

But in this case it reaches a maximum of 59 before resetting.
Time format can be changed by setting the format switch to
either logic 1 or 0. When set to logic 1, the digital clock will
be in 24 hours mode while when set to 0, it will be in 12 hours
mode, which can reach a maximum of 11 hours.
Option switches are used for selecting the variable either time,
date, alarm and stopwatch to be displayed by the seven
segments display unit of the Spartan-3 FPGA. The options are
four in number with each enabling one of the mentioned
variables. Only one of them has to be high at a time so as to
enable the variable assigned to be displayed.
The minutes are displayed by two seven segment display LEDs
of the Spartan-3 FPGA [8] and hour by the other two. Seconds
are displayed by six LEDs which presents it in a binary form
with off state represented by a 0 and on state by a 1.
The Stopwatch: This is activated by setting a strtstop slide
switch to logic level 1 and stopped by setting it to logic 0.
The stop watch can be run for 60 minutes only. When it reaches
59 it resets to 0 seconds and zero minutes on the next clock
cycle. Before activating the stopwatch, the correct option
The Clock: This is designed to display time in the format hr:

min: sec. System clock is scaled down to 1Hz to trigger the
1
AKGEC INTERNATIONAL JOURNAL OF TECHNOLOGY, Vol. 6, No. 1
button has to be activated for it to be displayed on the seven

segments display unit. The first two seven segment LEDS gives
the seconds count and others give the minutes count.
The Alarm: The alarm has a switch setalm. When the button
is set, user can set and adjust the alarm setting using sethr,
setmin and inct. At the time when the alarm set time
becomes equal to the clock time, an output pulse is sent out.
This is dependant on whether a 24 hours or 12 hours format is
selected. User adjusts it by taking into consideration which
time format is used at a particular moment.
The top level consists of 7 segment display decoders for

displaying the signals from all components in the system on a
seven segment display. It receives a six bit input data and
converts it to a form that represents the binary number on a
common anode seven segment display. The seven segment
display of each of the variables time, alarm, stop watch and
date were generated separately.
The Date: This has a value of 0 to 31 which increments at the

end of each 24 hours. It can be adjusted using an Adate
switch provided. When the Adate switch is set high, user
can use the Inct button to increment it. Before adjusting, the
stop button has to be set high and the option button
representing date display most also be high. The maximum it
can reach is 31 which then resets to 0.
Codes for interchanging between one display mode and the

other were included in the top level.
A new project was created using Xilinx ISE 8.2i with name
mydigitalclock. The eight source files mentioned earlier were
added. Relationship between the files was established through
portmaps and signals in the top level. Each file was saved and
synthesis was carried out. Some minor errors were debugged
and the synthesis stage was passed. The register transfer logic
was generated, pins were assigned using [8] as reference and
finally the bit file was generated. The bit file was programmed
onto the Spartan-3 FPGA and testing was performed which
proved that the design is well done.
II. METHODOLOGY
The codes for the functionalities mentioned earlier were written
in eight different files and were assigned names listed below:
1.
Tb_toplevel.vhd
2.
Toplevel.vhd
3.
Clockdivider.vhd
4.
Clock.vhd
5.
Alarm.vhd
6.
Stop.vhd
7.
Date.vhd
8.
Scan4digit.vhd
signal from the various components and determine the

Spartan-3 seven segment display on which to display
each digit.
III. RESULTS
Tb_tplevel.vhd is a test bench file for the entire digital

clock design.
Toplevel.vhd is the top level of the design and it includes
six components.
Clock Divider.vhd is a file that provides the clock pulse
needed by all components in this work. The Spartan-3
FPGA is set to operate at a frequency of 50MHz. This
frequency cannot be used for setting the timings in the
digital clock, and so there is the need to reduce it to 1Hz.
To do this, the board oscillator frequency is divided by
50 x 106 to obtain a frequency of 1Hz. This is done by
setting a variable count and then increments its value
up to 50000000, covering 50 x 106 cycles. At the end of
the 50 million cycles, it sends a pulse to the remaining
component parts. The variable count resets to 0 and the
process continues.
Clock.vhd contains the codes describing the
functionalities of the clock.
Alarm.vhd describes the components of the alarm.
Date.vhd describes the function of the date.
Stop.vhd is for the stopwatch.
Scan4digit.vhd acts as a decoder that receives an input
Figure 1. Register Transfer Level of the digital clock.
DESIGN OF A DIGITAL CLOCK
The table below shows how the resources in the Spartan- 3

FPGA were utilized:
V. REFERENCES
[1].
TABLE 1: SPARTAN-3 FPGA RESOURCES UTILIZATION

Logic Utilization
Used Available
Total Number Slice Registers
124
Number Used as Flip flops
98
3,840
[2].
Utilization
[3].
3%
[4].
Number Used as Latches
26
Number of 4 Input LUTS
444
3,840
Number of Occupied Slices
259
1,920
13%
Number of Slices Containing

Only Related Logic
259
259
100%
Number of Slices Containing

Unrelated Logic
259
0%
3,840
12%
[5].
[6].
11%
Logic Distribution
Total Number of 4 Input LUTS 485

Number Used as Logic
444
Number Used as route-thru
41
Number of Bonded IOBs
35
173
20%
Number of BUFGMUXs
37%
[7].
[8].
M. Balch, Complete Digital Design; A Comprehensive Guide

to Digital Electronics and Computer Systems Architecture, Mc
Graw Hill, 2003, pp 221-222.
B. Holdsworth and C. Woods, Digital Logic Design (fourth
edition), Newnes, 2002, pp 295-324.
J.F. Wakerly, Digital Design Principles and Practices, Prentice
Hall, 2005, pp 15-16.
Enoch O.H., Digital Logic and Microprocessor Design with
VHDL, Lasiera University, 2006, pp 23-26.
http://www.altera.com/products/fpga, accessed 15th July, 2014.
http://www.globalspec.com/local/3127/CA, accessed 15th July,
2014.
http://www.xilinx.com/index.htm, accessed 15th July, 2014.
Nexys Reference Manual.
Usman Sammani Sani graduated from

Bayero University, Kano in 2008, where he
obtained a bachelor degree of electrical
engineering. He then furthered his studies, in
which he obtained an MSc in Electronic
Communications and Computer Engineering
from The University of Nottingham Malaysia
Campus in 2011.
Usman is presently a lecturer in the
Department of Electrical Engineering, Bayero
University Kano. His research interests include
digital communications, digital circuits design and testing of fabricated
electronic components.
IV. CONCLUSION
The Digital Clock was designed by first creating VHDL codes
and synthesizing them using Xilinx ISE 8.2i software. The codes
passed synthesis and a bit file was generated. The bit file was
programmed onto a Spartan-3 development kit and tested for
functionality. The circuit performed the desired functions.
Design statistics also showed that the FPGA resources were
highly utilized and therefore the design is economical. This
proves how FPGAs are desirable when dealing with complex
systems.
Ibrahim Haruna Shanono received his

B.Eng and MSc. degree from Bayero University
Kano and Nottingham University in 2008 and
2012 respectively. He is currently working with
the Department of Electrical Engineering,
Bayero University Kano, Nigeria. His research
interests are in the areas of Renewable Energy,
Power Electronics and Automatic Control
systems.
Application of Queuing Model: With Special Reference to

Construction and Business Bank Adama Branch Ethiopia
Dr. Kamlesh Kumar Shukla1 and Dr. Girish Kumar Painoli2
Department of Management, School of Business and Economics,
Adama Science and Technology University, Adama, Ethiopia
2
Department of Accounting and Finance, School of Business and Economics,
Adama Science and Technology University, Adama, Ethiopia
1
kkshukla22@yahoo.com , 2gkpainoli@gmail.com
1
Abstract -- In this paper, queuing model is applied to the data

collected on construction bank, Adama branch, Ethiopia. The
endless customers waiting for service delivery in construction
and business bank is a phenomenon that bothers both the
management of banking institutions and the customers alike.
Thus, the need to optimize total operating cost by determining
the optimal balance between the cost of making customers to
wait for service and the cost of providing additional service, some
studies have claimed that service improvement can be achieved
by increasing the number of servers, but to what extent this can
be done to minimize overall cost? This study examines the
validity of multi-server queuing models for achieving reduction
in waiting time and minimization of cost and characteristics of
customers. After adding one/two servers, further characteristics
of customer were analyzed with help of multiple server model.
The average waiting time per customer in a system as well as in
the queue were found about 32 minutes and about 29 minutes
respectively. It reveals a preference for a multi-server system
that determines its usage and suggestions for improvement in
service delivery are highlighted.
The three basic components of a queuing process are arrivals,

service rate, and the actual waiting line.
As the word turns to a global village characterized by intense
and ever increasing demand, operation bank managers
continue to experience wrenching changes, which they must
keep up for their survival. Bank customers have also become
increasingly demanding. Today, they require high quality, low
price and immediate service delivery and tomorrow, they want
additional components of value from their chosen banker. Since
service delivery in banks is personal, customers are either
served immediately or join a queue (waiting line) if the serving
system is busy.
Waiting line is what one experience everywhere in daily life i.e.
while shopping, checking into hotels, at hospitals and clinics
etc. In situations where facilities are limited and cannot satisfy
the demand made upon them, bottlenecks occur which manifest
as queue but customers are not interested in waiting in queues.
When customers wait in queue, there is the threat that excessive
waiting time will lead to the loss of some customers to
competitors. But allowing them to serve themselves so easily
is a key factor in both keeping and attracting customers
(Michael, 2001).
Keywords: Queuing Model, Multi-server System, Service Delivery
I. INTRODUCTION
QUEUING theory had its beginning in the research work of a
Danish engineer named A. K. Erlang. In 1909 Erlang
experimented with fluctuating demand in telephone traffic.
Eight years later, he published a report addressing the delays
in automatic dialing equipment. At the end of World War II,
Erlangs early work was extended to more general problems
and to business applications of waiting lines.
Statement of the problem: One of the goals of queuing analysis

is finding the best level of service for an organization. When
Construction and business bank does have control, its
objective is usually to find a high spirits, medium between two
extremes. On the one hand, a bank can retain a large number of
customers and provide many service facilities. This, however,
can become expensive. The other extreme is to have the
minimum possible number of teller windows open. This keeps
the service cost down but may result in customer
dissatisfaction. When the average length of the queue
increases then the poor services will result in the loss of
customers and goodwill.
The study of waiting lines, called queuing theory, is one of the

oldest and most widely used quantitative analysis techniques.
Waiting lines are an everyday occurrence, affecting people
shopping for groceries buying gasoline, making a bank deposit,
or waiting on the telephone for the first available airline
reservationists to answer. Queues, another term for waiting
lines, may also take the form of machines waiting to be repaired,
trucks in line to be unloaded, or airplanes lined up on a runway
waiting for permission to take off and restaurant study taken
in Indonesia (Dharmawirya and Adi, 2011; Sharma et al., 2013).
When services improve in speed, then the time spent in waiting

will decrease. This waiting cost may reflect loss of productivity
4
APPLICATION OF QUEUING MODEL
of workers while their tools or machines are awaiting repairs or

may simply be an estimate of the cost of customers lost because
of poor service and long queues.
Methods of Data Analysis: To make the data suitable for further

analysis, classification and editing was made. The raw data
were organized into groups. The data which were collected
from the primary and secondary sources were analyzed by
using statistical tools and techniques, such as tables,
percentages and graphs etc. A single and multiple servers were
applied in the simplest form of queuing system.
This assessment is going to address the following questions:1.

Do the customers satisfied with service rate provided by
the bank?
2.
What are the factors that cause the customers to leave
the bank?
3.
Does the organization have enough servers to serve the
expected customers?
4.
How the waiting time will be reduced if there are
alterations in the server?
Definitions of queuing system variables:
= the arrival rate (average number of arrivals per time

period)
= the service rate (average number served per time

period)
= mean arrival rate;
= mean service rate
And that < (customers are served at a faster rate than

they arrive), we can state the following formulas for the
operating characteristics of a single-server model.
(Bernard W. Taylor III 2006, 9th edition)
Customers must be served faster than they arrive, or an

infinitely large queue will build up.
Lq = average queue length (average number of

customers in queue)
L = average system length (average number of customers

in system, including those being served)
Wq = average waiting time in queue (average time a

customer spends in queue)
W = average time in system (average time a customer

spends in queue plus service)
Lq =Wq (Littles Law)=2/(-)
L =W (Littles Law)=/-
L = Lq +/
W = Wq +1/=L/
U= /
I=1-u=1-/
P0= (1-/)
Pn= (/) n.p0== [(/)n](1-/)
Significance of the Study: The significance of the study is to

find the best level of service and provide information
concerning queue analysis for Construction and business bank
for better customer services at minimum cost.
Objectives :The general objective of this study is to know the
characteristic of the customers in Construction and business
bank at Adama branch. The main objectives of the study are
To determine the waiting time of customers is likely to

experience in a system
To determine how the waiting time is affected If there is

increase in the number of servers
To offer necessary suggestion if any to the bank based

on the analysis of the study
II. DATA AND METHODOLOGY
Method of data collection and Sample size: The study was
conducted at Construction and business bank, Adama branch,
Ethiopia where the information about the characteristics of
customers was collected. It was carried out on the basis of
data collection during the period of one week, (i.e. 6 working
days from December 24, 2013 to January 6, 2014) through
observation, interview and questionnaire methods and the
Variables were analyzed by using the Queuing Models.
The parameters of the multiple-server model are as follows:
=the arrival rate (average number of arrivals per time

period)
=the service rate (average number of customers served

per time period) per server (channel)
C=the number of servers
C=the mean effective service rate for the system, which

must exceed the arrival rate
C>= : the total number of servers must be able to serve

customers faster than they arrive
The probability that there are no customers in the system

(all servers are idle)
The variables measured include arrival rate ( ) and service

rate (). They were analyzed for simultaneous efficiency in
customer satisfaction and cost minimization through the use
of multi-channel queuing models. These are compared for a
number of queue performances such as; the average time spent
by each customer in the queue as well as in the system, average
number of customers in the queue as well as in the system and
the probability of the system being idle.
Primary data in respect of customer arrival rate and service rate
were obtained through observations while customer attitude
survey was carried out through a questionnaire distributed
among 50 customers by using simple random sampling method.
Secondary data were collected from the bank, related books
and other relevant, and published research journal.
III. RESULTS AND DISCUSSION

Data Analysis And Interpretation: According to Table 1, 56%
of the respondents were served in more than 52 minutes, 10%
of the respondents were served within 21-36 minutes, 10% of

the respondents were served within 5-20 minutes respectively.
This indicates that most of the customer served for more than
52 minutes. It is due large number of customers and traditional
methods adopted by the bank in serving the customers.
TABLE 4 NUMBER OF CUSTOMERS SERVED WITHIN A

WEEK FROM DECEMBER 24, 2013 TO JANUARY 6, 2014
Month
TABLE 1 DISTRIBUTION OF THE NUMBER OF

RESPONDENTS WITH RESPECT TO THEIR TIME
SPENT IN THE BANK
Time spent
No of customers
served per a day
December 24, 2013
1618
December 28, 2013
1306
January 1, 2014
2103
No. of respondents
Percentage
January 3, 2014
1295
5-20 minutes
10%
January 5, 2014
1388
21-36 minutes
10%
January 6, 2014
1134
37-52 minutes
12
24%
Total
8844
TABLE 2 -- DISTRIBUTION OF RESPONDENTS AND THEIR

OPINION ABOUT SATISFACTION WITH TIME OF SERVICE
Opinion
No of respondents
Percentage
Yes
16
32%
No
34
68%
Total
50
100%
Average numbers of customers served

= Total numbers of customers served in a week
Total numbers of days in a week
=8844/6 = 1474
Mean service rate ( )
(mean service rate per hour)
= average numbers of customers served
Working hours per day
Table 2 shows that 68% of the respondents were not satisfied

with the time of service and 32% were satisfied with time of
service. It is observed that the most of the customers were not
satisfied with the service provided by the bank. It may be due
to lack of ethical and moral behavior among the bank employees
towards their customers.
1474/9.5 hr. = 155/ hr

(service rate per server)
= average numbers of customers served
Total No servers=7
TABLE 3 -- DISTRIBUTION OF RESPONDENTS AND THEIR

ATTITUDE TOWARDS LONG QUEUE
Opinion
Computation of mean service rate and arrival rate
Customers served per server within a day

= 1474/7 =210.57 or 211
No of respondents
Percentage
Yes
15
30%
No
35
70%
TABLE 5 -- DISTRIBUTION OF ARRIVALS OF CUSTOMER

AT THE BANK FOR A WEEK
Total
50
100%
Selected day
Arrival per hour
December 24
157
Table 3 reveals that, 30% of the respondents were return back

after finding the long queue, 70% of the respondents were
served after their arrival at the bank as usual. Therefore it can
be observed that bank loses many customers because of the
long queue.
December 28
153
January 1
167
January 3
144
January 5
156
Quantitative analysis: Operating characteristics computation

for seven servers
January 6
141
Total
918
Mean arrival rate ()
The average arrival rate
Wq= the average time a customer spends in the queue, waiting

to be served is:-
(mean arrival rate per hour) 153/hr
PW = the probability that a customer arriving the system must

wait for the service (i.e. the probability that all the severs are
busy
155/hr 155/7hr = 22.14 customers served in each window/

hr. or mean service rate for each server per
C= 7
Po= the probability of No customers in the service department
It was observed that, customers were frustrated by the relatively

long waiting time of 32.28 minutes and the 0.9859 probability
of waiting.
Operating characteristics of customers when one/two
server(s) are added
Operating characteristics computation for eight server/
windows:
When the servers increase from 7 to 8, the service rate also
increases from 155 to 177 per hour
L= the average number of customers in the queuing system

is:-
(mean service rate per hour) = 1474 + 211 = 1685 = 177/ hr.
9.5
9 .5
=177/8= 22.14 customers served in each window /hr. or mean
service rate for each server per hour
=22.14 Customers served per hour in each window
=153 Average customers arrive at the service station in an
hour
C= 8 Number of servers
W= the average time a customer spends in the queue system

(waiting and being served) is:W=L/
=82.32/153 =0.53804hrs (32.2824 minutes)
Lq= the average number of customers in the queue is:-
The probability that there is No customer in the service

department is 0.00064
= 75.41 customers on average waiting to be served on the line

7
L= 42.9 customers, on average in the service department
customers waiting in the queue for service while an 8-servers

system and seven servers system has 35.99 and 75.41 customers
respectively on the queue. In an 8 and 7 servers system, a
customer spends 17 minutes and 32.28 minutes in the system
respectively and customer spends 14.4minutes and
29.52minutes on the queue respectively. However, in 9 servers
system customer waits in the system for about 3.18 and waits
in the queue for 0.4896 minutes.
The average time that the customer spends in the queue system
is 0.2804 hr. or 17 minute.
Lq= 35.99 customers on average waiting to be served on the

line
The probability of being busy for seven -servers system is

very high (98.59%) than either of 8 or 9 servers system. Mean
numbers of arrivals was 153 customers per hour. The arrival
process follow queue discipline and it was first-come-firstserved and queue population was infinite. From the above
study it was observed that the adoption of 9 servers is better
than both 7 and 8 servers in all circumstances.
Wq= 0.24 hrs. or 14.11minute on average a customer spends in

the queue to get the service
IV. SUGGESTIONS
Suggestions: Based on the analysis of the study, the following
suggestions are given for improvement of efficiency and quality
of service to customers of the bank.
Addition of two service channels will reduce loss of

customers.
Providing TV in the waiting hall, comfortable seats, and

toilet facilities for increasing the satisfaction of the
customers.
The bank should educate their front line employee in the

application of queuing models for efficient solving of
operational problems.
Bank should enrich employees job by making them multiskilled, through continuous training so as to enable them
to eliminate unnecessary counter-check handoffs.
The queue characteristics should be viewed from the

customers point of view i.e. whether the waiting time is
reasonable and acceptable or not.
Reengineering the banking operations through IT

solutions e.g. ATM, and online banking etc., to harmonize
queuing model.
PW= 0.6026 so the probability of all the servers are busy is

0.6026
Operating characteristics computation for nine servers/
windows
C=9 severs
(service rate per hour) =1474+422 =1896 =197 /hr
9.5
9.5
=22.14 Customers served in each window /hr.
=153 Customers
Po= 0.0008854
L= 8.16 customers on average in the service department
W=0.053hrs or 3.29 minutes. The average time customers
spends in the queue system
Lq=1.25 customers on average in the queue. Waiting to be
served on the line
Wq=0.00816hr or 0.49 minutes will the customers to be served
on a line
PW= 0.38(38%) so the probability that all severs are busy is
0.38 or 38%.
V. CONCLUSION
Based up on the above discussion it can be concluded that,
for rendering better services to the bank customers modern
models should be adopted. The average waiting time per
customer in a system as well as in the queue were found about
32 minutes and about 29 minutes respectively, however 2
servers added in the bank, the average waiting time per
customer in the system and queue were found about
3.18minutes and 0.4896 minutes respectively. Customer
satisfaction is the significant factor for any industry and more
to service industry to which all banks belong. Therefore the
application of queuing analysis has proved that the adoption
of it in the day to day operational activities of the bank will
satisfy the customers. Satisfied customers will result in desired
growth for the bank and for economy of the country.
TABLE 6 -- OPERATING CHARACTERISTICS FOR

ALTERNATIVES SERVERS
No. of servers
Lq
Wq
PW
82.32
75.41
32.28m
29.52m
0.9859
42.9
35.99
17m
14.4m
0.6026
8.16
1.25
3.18m
0.4896m
0.38
Above table indicates that using of 9-server in system is better

than both 8 servers and seven servers system in all
circumstance. For instance a 9 servers system has 1.25
VI. REFERENCES
[1].
[2].
[3].
[4].
[5].
[6].
[7].
Dr. Kamlesh Kumar Shukla is presently

working as Assistant Professor in ASTU,
Ethiopia since September 2013. Obtained PhD
in Statistics from Banaras Hindu University,
Varansi, India and Masters degree in Statistics
(Gold medallist) in 1997.
Selected as Secretary, Governing Council of
Forum for Interdisciplinary Mathematics for
the term 2015 2017. Possesses over 12 years
of teaching experience.
Authored a book for BCA students, namely,
Elements of Statistics published by Thakur Publishers, Lucknow. Worked
on six projects with organisations such as IIPS, WHO, DST, New
Delhi. Published over 12 papers and presented six papers at conferences.
W. Bernard Taylor III Introduction To Management Science

9th, Virginia Polytechnic Institute and State University, 2006,
Prentice Hall.
www.http//safe-associate/2000
T.L. Saaty, Elements of Queuing Theory 1961, New York:
McGraw-Hill Safe Associates (2002)
R.B. Cooper, Introduction to Queuing Theory, 2le, Elsevier,
North Holland, 1980
A.M. Lee, Applied Queuing Theory, St Marints press, New
York, 1966.
Mathias Dharmawirya, and Erwin Adi, Case Study for
Restaurant Queuing Model IPEDR Vol.6 (2011) (2011)
IACSIT Press, Bali, Indonesia
Ajay Kumar Sharma, Queuing theory approach with queuing
model: a study, International Journal of Engineering Science
Invention ISSN (Online): 2319 6734, ISSN (Print): 2319
6726 Volume 2 Issue 2 February. 2013 PP.01-11.
Dr. Girish Kumar Painoli received the

M.Com degree, from Osmania University,
Hyderabad, in 1995, M.Phil degree from SGB
Amaravathi University in 1999 and Ph.D.
degree in management Science, from Swami
Ramanand Teerth Marathwada University
Nanded in 2012. He also qualified UGC-NET.
Worked as Professor in Department of
Accounting and Finance at Adama Science and
Techonology University, Adama, Ethiopia.
Currently, he is a Faculty in Accounting in
Department of Business Studies at Shinas College of Technology, Al
AQR, Shinas, Sultanat of Oman. His teaching and research areas include
Accounting and Finance authored/co-authored approximately twenty
five research papers and attended nearly 25 conferences.
Hybrid Method for Automatically Filling of the Chemical

Liquid into Bottles Using PLC & SCADA
Eternal University, Baru Sahib Road, Baru Sahib, Himachal Pradesh 173001 India
jatin.dhiman15@gmail.com
Abstract -- In todays fast-moving, highly competitive industrial
world, a company must be flexible, cost effective and efficient if
it wishes to survive. In the process and manufacturing industries,
this has resulted in a great demand for industrial control systems/
automation in order to streamline operations in terms of speed,
reliability and product output. Automation plays an increasingly
important role in the world economy and in daily experience. A
prototype of commercial Hybrid method of automatically filling
the bottles using PLC&SCADA and show its visualization on
SCADA screen, controlled using programmable logic controller
(PLC) is proposed and the whole process is monitored using
supervisory control and data acquisition. This system provides
the provision of mixing any number of liquids in any proportion.
Its remote control and monitoring makes the system easily
accessible and warns the operator in the event of any fault. One
of the important applications of automation is in the soft drink
and other beverage industries, where a particular liquid has to
be filled continuously. The objective of this paper is to design,
develop and testing of the Real time implementation of PLC,
SCADA system for ratio control based bottle filling plant. This
work will provide low operational cost, low power consumption,
accuracy and flexibility to the system and at the same time it will
provide accurate volume of liquid in bottle by saving operational
time.
We can operate & control automatically filling of bottles sitting

far away from the plant (for example 500km distance from plant)
and we can change all the parameters of the process using
SCADA technology because SCADA system is used as
supervisor to monitor the process. The purpose of this to
research is to apply filling 2 type of chemical liquid into bottles
randomly by using PLC as a controller. This is a batch operation
where a set amount of inputs to be process is received as a
group, and an operation produces the finish product. In many
automation processes it is necessary to achieve a desired
demand in some specified time. If the production rate is 35
bottles per minute and the demand increases to 65 bottles per
minute, the operating speed needs to be increased, whereas if
the demand drops abruptly the production rate needs to be
decreased. Thus the research deals with overcoming the problems
of speed control in order to have improved operational parameters.
II. PLC AS SYSTEM CONTROLLER
Programmable logic controller or programmable controller is a
digital computer used for automation of industrial process,
such as control of machinery on factory assembly lines. Unlike
general-purpose computers, the PLC is designed for multiple
inputs and output unlike general purpose computers, the PLC
is designed for multiple inputs and output. Arrangements,
extended temperature ranges, immunity to electrical noise, and
resistance to vibration and impact. Programs to controlled
machine operations are typically stored in the battery backed
or non volatile memory.
Keywords: PLC, SCADA, Sensors, Automation,VFD, Conveyor
I. INTRODUCTION
THIS research is to design and develop the Hybrid method
of automatically filling the chemical liquid into bottles using
PLC&SCADA and show its visualization on SCADA screen.
Figure 1: Basic PLC operation process.
10
AUTOMATICALLY FILLING OF THE CHEMICAL LIQUID
Unlike a personal computer though the PLC is designed to

survive in a rugged industrial atmosphere and to be very flexible
in how it interfaces with inputs and outputs to the real world.
a programmable logic controller is simply used in many
industries such as oil refineries, manufacturing lines, conveyor
systems and so on. Wherever there is a need in control devices
the PLC provides a flexible way to soft wire the components
together.
The digital computer is used as an interface between PLC and

SCADA. The PLC is a micro processor based system controller
used to sense, activate and control industrial equipments and
thus incorporate a number of input output/modules which
allows electrical system to be interfaced. SCADA is a centralized
system used to supervise a complete plant and basically
consists of data accessing features and controlling processes
remotely. The communication protocol used is Ethernet. The
Variable Frequency Drive connected to the PLC receives AC
power and converts it to an adjustable frequency adjustable
voltage output for controlling the motor operation. The analog
module converts analog input signals to digital output signals
which can be manipulated by the processor.
III. FUNDAMENTAL PRINCIPLES

SCADA refers to the combination of telemetry and data
acquisition. SCADA encompasses the collecting of the
information, transferring it back to the central site, carrying
out any necessary analysis and control and then displaying
that information on a number of operator screens or displays.
The required control actions are then conveyed back to the
process. The PLC or Programmable Logic Controller is still one
of the most widely used control systems in industry. As needs
grew to monitor and control more devices in the plant, the
PLCs were distributed and the systems became more intelligent
and smaller in size. PLCs and DCS or (Distributed Control
Systems) are used as
The output of the VFD is given to the 3-phase induction motor

which in turn with the help of a pulley mechanism is used to
vary the speed of the conveyor belt. An inductive sensor is an
electronic proximity sensors used to detect metallic objects
without touching them. The solenoid valve is a normally closed
direct acting valve used to pour the liquid in the bottle whenever
it gets a signal from the proximity sensor
V. PLC AND RELATED SOFTWARES
The PLC used is Micro Logix 1200 as it has 10 inputs and 6
outputs and has an interface for Ethernet. The Micro Logix
1400 system offers higher I/O count, faster high-speed counter/
PTO, and enhanced network capabilities The programming
software used is RSLOGIX 500 and the communication software
used is RS LINX 500.
The advantages of the PLC / DCS SCADA system are:
The computer can record and store a very large amount

of data.
The data can be displayed in any way the user requires.
Thousands of sensors over a wide area can be connected

to the system.
The operator can incorporate real data simulations into

the system.
Many types of data can be collected from the RTUs.
The data can be viewed from anywhere, not just on site.
Features of MicroLogix 1200:

Ethernet port provides Web server capability, email capability
and protocol support Built-in LCD with backlight lets you
view controller and I/O status Built-in LCD provides simple
interface for messages, bit/integer monitoring and manipulation
Expands application capabilities through support for as many
as seven 1762 Micro Logix Expansion I/O modules with 256
discrete I/O . As many as six embedded 100 kHz high-speed
counters (only on controllers with DC inputs) Two serial ports
IV. BLOCK DIAGRAM

This deals with the key components used in settling up the
complete plant and thus explains the use and working of each
component. The block diagram of the experimental set up is
illustrated. The following configurations can be obtained.
Figure 2. Block Diagram.
11
that have a safety factor. This often leads to energy inefficiency

in systems that operate for extended periods at reduced load.
The ability to adjust motor speed enables closer matching of
motor output to load and often results in energy savings
with DF1, DH-485, Modbus RTU, DNP3 and ASCII protocol

support.
Proximity Sensors: Proximity Sensors are available in two types
namely;
1)
Inductive sensors
2)
Capacitive Sensors.
The components of the drive system are broken into four major
categories: source power, rectifier, dc bus, and inverter. Other
components exits such as resolver and encoder feedback
devices, tachometers, sensors, relays and help supplement
the system.
Inductive Sensors are cheaper and allow detection of metal

objects whereas capacitive sensors are costly and allow
detection of metal, plastic and glass objects as well.
First, the source power must be converted from alternating

current to direct current. This conversion is accomplished by
means of a rectifier; a diode is used for more intelligent
rectification. The power source that was 460volts ac, 60 Hertz
now converted to 650 volts dc. This AC to DC conversion is
necessary before the power can be changed back to AC at a
variable frequency.
VI. VARIABLE FREQUENCY DRIVE

When an induction motor starts, it will draw very high inrush
current due to the absence of the back EMF at start. This
results in higher power loss in the transmission line and also in
the rotor, which will eventually heat up and may fail due to
insulation failure. The high inrush current may cause the
voltage to dip in the supply line, which may affect the
performance of other utility equipment connected on the same
supply line.
The diode bridge converter that converts AC-to-DC is

sometimes just referred to as a converter. The converter that
converts the dc back to ac is also a converter, but to distinguish
it from the diode converter, it is usually referred to as an
inverter. It has become common in the industry to refer to
any DC-to-AC converter as an inverter.
Adding a variable frequency drive (VFD) to a motor-driven

system can offer potential energy savings in a system in which
the loads vary with time. VFDs belong to a group of equipment
called adjustable speed drives or variable speed drives.
Figure 3. Block diagram of VFD ac to dc converter.
(Variable speed drives can be electrical or mechanical, whereas

VFDs are electrical.) The operating speed of a motor connected
to a VFD is varied by changing the frequency of the motor
supply voltage. This allows continuous process speed control.
Motor-driven systems are often designed to handle peak loads
VII. METHODOLOGY
This department of the plant works on distribution of any kind
of chemical liquid into different tank to a main two buffer
storage tank. This distribution takes place automatically using
the Programmable Logic Controller (PLC).
12
Figure 4. Screen shot of SCADA software of manufacturing department of the chemical liquid.
It commonly applied application of PLC where five different

chemical liquids are mixed in required proportion to form a
batch .Rate of the flow is already fixed. We only control the
time of the flow. Level of the liquids in the tank is sensed by
the level sensor switches. The ratio of five different liquids
will decided as per the required mixed liquid that we needed in
the bottle. There is a stirrer motor is also fitted to mix these two
liquids of definite amount in the main tank.
operation takes place. If the particular bottle is not present

then the valve in that position is switched off, thereby avoiding
wastage of the liquid. The filling process is done based on
timing. Depending on the preset value of the timer the valve is
switched on for that particular period of time and the filling is
done.
Figure 5. Screen shot of the SCADA software of the automatically filling of the chemical liquid into the bottles.
Bottles are kept in position in a carton over conveyor belt;

they are sensed to detect their presence. Capacitive sensors
are used for sensing the bottles. Depending on the output of
the sensor the corresponding valve switch on and filling
The motor continues to run even when the bottle moves away
from the first sensors range, i.e. the output of the motor is
latched as explained in the ladder logic section of PLC. When
sensor 2 senses the bottle, it also gives a high output to the
13
PLC. The PLC instructs the inverter to stop the motor. The
high output bit of sensor 2 is also given to the timer for the
solenoid valve. The timer used is TON. It counts for a predefined
value of time (18 sec). It gives two outputs, Enable output and
done output. The Enable output remains high while the timer
is counting and the output goes high after the timer has finished
counting. The Enable output of TON is given to the solenoid
valve, and so the solenoid valve is open for the predefined
value of time (18 sec). The Done output bit is used to turn ON
the motor again in the running . And this all the process are
repeat again and half the bottles fill again to in front of the
second chemical tank and the bottles full filled and the done
output bit is used to turn on the induction motor again. All
this are described in this ladder programming of the PLC.
IX. CONCLUSION
This paper presents a automated liquid filling to bottles of
using PLC and SCADA. A total control is made in a filling is
achieved. The present system will provides a great deal of
applications in the field of automation, especially in mass
production industries where there are large number of
components to be processed and handled in a short period of
time and theres need for increased production. The
programming to this system developed is flexible, quickly and
easily. This will increase the total production output; this
increase in production can yield significant financial benefits
and savings. This concept can be used in beverage and food
industries, milk industries, medicine industries, mineral water,
chemical product industries and manufacturing industries. The
VIII. PLC LADDER PROGRAM
Figure 6. PLC ladder program for filling of the chemical liquid into the bottles.
14
present work is motivated to develop an online scheme to

monitor and control a hybrid method of automatically filling of
the chemical liquid into the bottles using PLC and SCADA.
[8].
X. REFERENCES
[1].
[2].
[3].
[4].
[5].
[6].
[7].
Sager P. Jain, Dr.Sanjay l.Haridas ,energy efficient atomized

bottling plant using plc and SCADA with speed variable
conveyor assembly (Iosr Journal Of Electronic And
Communication Engineering, e-ISSN:2278-2834, p- ISSN8735.
Mrs. Jignesha, Air design and Development of PLC and
SCADA Based Control Panel For Continuous Monitoring Of
3-Phase Induction Motor.
K.Gowri Shankar Control of Boiler Operation Using PLCSCADA International Multiconference of Engineers and
Computers Scientists 2008 Volume 2 imecs 2008, 19-21 March,
2008, Hong Kong.
N. Shaukat, PLC Based Automatic Liquid Filling Process,
Multitopic Conference, 2002, IEEE publication.
T. Kalasiselvi and R. Praveena PLC Based Automatic Bottle
Filling and Capping System with user Defined Volume
Selection, International Journal of Emerging Technology And
Advanced Engineering, Volume 2, Issue 8, August 2012).
Arvind N. Nakiya, Mahesh A. Makwana An Overview of a
Continuous Monitoring and Control System for 3-Phase
Induction Motor Based on Programming Logic Controller and
SCADA Technology. (IJEET volume 4 , issue 4, July August
(2013).
V. Mathavi & Dhivya Static Application Panels (SAP)
Controlled by PLC(International Journal of Applied
[9].
[10].
[11].
[12].
[13].
15
Information Systems (IJAIS)-ISSN: 2249-0868 Foundation

of Computer Science FCS, New York, USA Volume 5No 6,
April 2013.
Hemant Ahuja and Arika Singh Automatic Filling Management
System For Industries, International Journal of Emerging
Technology and Advanced Engineering,Volume-4, special issue,
February 2014.
Mahesh Nandaniya( Automatic Canal Gate Control of 3-
Induction Motor with PLC and VFD, Powered by Solar System
and Monitoring International Journal of Emerging Trends in
Electrical and Electronics (IJETEE) , Vol. 1, Issue 1, March
2013.
Sujith John Mathew and B.Hemalatha, Fault Identification
and Protection of Induction Motor using PLC and SCADA
international journal of advanced research in electrical, electronic
and instrumention engineering vol3, issue 4, April 2014.
Pampashree and Md. Fakhruddin Ansari Design and
Implementation of Scada Based Induction Motor Control.
Journal of Engineering Research and Applications
www.ijera.com ISSN : 2248-9622, Vol. 4, Issue 3 Version 5,
March 2014, pp.05-1.
Ahmed Ullah Abu Saeed & Md. Al-Mamun Industrial
Application of PLCs in Bangladesh, International Journal of
Scientific & Engineering Research, Volume 3, Issue 6, June2012, ISSN 2229-5518.
V. Vikash and H.J. Amarendra, PLC Based Sensor Operated
Obstacle Detection Carriage Vehicle, International Journal of
Applied Engineering Research ISSN 0973-4562 Volume 9,
Number 7 (2014) pp. 847-851.
Friction Stir Welding: Tool Material

and Geometry
A. Chandrashekar, B. S. Ajay Kumar and H. N. Reddappa
Department of Mechanical Engineering, Bangalore Institute of Technology, Bangalore, India.
acsmech@gmail.com
Abstract -- The Friction stir welding is a dynamically developing

version of pressure welding processes by which High-quality welds
can be created. The mixing the material flow conditions
specifically affect the quality of the weld, so the Tool geometry is
very important. Tool design and selection of process variables
are critical issues in the usage of FSW process. The Development
of cost effective and durable tools, which lead to structurally
sound welds, is still awaited. Material selection and design
intensely affect the performance of the tools. Here we reviewed
several important aspects of FSW tools such as tool material
selection & its importance, geometry and load bearing ability
and process economics for applications in this article.
Figure 1. Schematic drawing of friction stir welding.
Keywords: Friction Stir Welding; Tool Material; Tool Geometry;

Rotational Speed.
II. INFLUENCE OF TOOL MATERIAL

AND GEOMETRY ON WELD QUALITY
The tool of FSW is composed of two parts: a tool body and a
probe. The tool technology is the heart of friction stir welding
process. The tool shape determines the heating, plastic flow
and forging pattern of the plastic weld metal. The tool shape
determines the weld size, welding speed and tool strength.
The tool material determines the rate of friction heating, tool
strength and working temperature, the latter ultimately
determines which materials can be friction stir welded [3]. Two
different tool pin geometries (square and hexagonal) and three
different process variables, i.e. rotational speeds and welding
speeds were selected for the experimental investigation of
AA6101-T6 alloy. It was observed that square pin profile gave
better weld quality than the other profile. Besides, the electrical
conductivity of the material was maintained up to 95% of the
base metal after welding. Arora et al [4] proposed and tested a
criterion for the design of a tool shoulder diameter (considered
three Shoulder diameters 15, 18, & 21mm) based on the principle
of maximum utilization of supplied torque for traction.
I. INTRODUCTION
FRICTION stir welding is a solid state joining process using a
rotating tool moving along the joint interface, generating heat
and resulting in a re-circulating plasticized material flow near
the tool surface. This plasticized material is subjected to
extrusion by the tool probe rotational and linear movements
leading to the formation of stir zone. This stir zone formation is
affected by the material flow behavior under the action of
rotating tool. It was developed in England by The Welding
Institute (TWI) in 1991 [1]. The friction stirring tool consists of
a pin, or probe, and a shoulder as shown in Fig.1. Contact of
the pin with the workpiece creates frictional and deformational
heating and softens the workpiece material; contacting the
shoulder to the workpiece increases the workpiece heating,
expands the zone of softened material, and constrains the
deformed material. Naturally, there are important effects to the
tool during welding: abrasive wear, high temperature and
dynamic effects. Therefore, the good tool materials have the
following properties: good wear resistance, high temperature
strength, temper resistance, and good toughness.
The optimum tool shoulder diameter computed from this

principle using a numerical heat transfer and material flow model
resulted in best weld metal strength in independent tests and
peak temperatures that are well within the commonly
encountered range. The optimum shoulder diameter of 18 mm
at 1200 rpm has resulted in superior tensile properties in
independent tests. Elangovan and Balasubramanian [5] have
also reported that the tool with an 18 mm shoulder diameter
So there are two important aspects of friction stir welding tool

design: tool material and geometry [2]. Most important
Challenges of Friction Stir Welding are application of high
temperature materials, Tool material selection, Development of
Tool Materials, Tool design and Complex geometries and
dissimilar materials.
16
FRICTION STIR WELDING
material and shape of the pin reduces number of trials and

tooling cost. In addition this study also highlights the wear
effect due to friction between sliding surfaces. The effect of
Friction Stir Welding process parameters on the mechanical
properties of the AA 2014-T6 alloy joints produced by friction
stir welding have been discussed by Vagh and Pandya [8].
Effects of tool design, tool rotation speed & tool travels speed
on mechanical properties have been analysed using Taguchi
orthogonal array design of experiments technique. There are
three different tool rotation speeds (1000, 1400 & 2000 rpm)
and three different tool traverse speeds (14, 20, 28 mm/min).
For each combination of tool rotation speeds and tool traverse
speeds three different types of tool pin profiles (threaded
cylindrical pin, Stepped pin and Threaded cone pin) have been
used. The study indicates that Tool design is the main process
parameter that has the highest statistical influence on
mechanical properties.
provided the best weld joint strength at a rotational speed of

1200 rpm, as shown in Table 1.
TABLE I- THE MECHANICAL PROPERTIES OF WELDS
MADE USING A CYLINDRICAL PIN PROFILE [4]
TABLE II - WELDING TEMPERATURE RANGE

OF VARIOUS ALLOYS [5]
TABLE III - TOOL MATERIALS USED IN

FSW FOR SOFT ALLOYS [5]
Figure 2. Different FSW tool geometries used in the experiment [8].
Prasanna et al [10] studied the effect of four different tool pin

profiles on mechanical properties of AA 6061 aluminum alloy.
Four different profiles have been used to fabricate the butt
joints by keeping constant process parameters of tool rotational
speed 1200rpm, welding speed 14mm/min and an axial force
7kN. Different heat treatment methods like annealing,
normalizing and quenching have been applied on the joints
and evaluation of the mechanical properties like tensile
strength, percentage of elongation, hardness and
microstructure in the friction stirring formation zone are
evaluated. Of the four tool profiles, the maximum tensile strength
and % of elongation of 210 MPa and 20.9 respectively was
observed on Hexagonal pin profile tool with annealing process.
The tensile strength and percent of elongation of the hexagonal
tool profile with annealing process has reached about 90 %
and 80 % respectively of the parent metal. Lee et al [11] welded
AlMg alloy with low carbon steel in lap joint configuration
using tool steel as tool material without its excessive wear by
placing the softer AlMg alloy on top of the steel plate and
avoiding direct contact of the tool with the steel plate. Tungsten
based alloys have also been used for the welding of both low
and high melting point alloys [12]. For example, Edwards and
Materials such as aluminium or magnesium alloys, and

aluminium matrix composites (AMCs) are commonly welded
using steel tools. Steel tools have also been used for the joining
of dissimilar materials in both lap and butt configurations. Tool
wear during welding of metal matrix composites is greater when
compared with welding of soft alloys due to the presence of
hard, abrasive phases in the composites. Total wear was found
to increase with rotational speed and decrease at lower traverse
speed, which suggests that process parameters can be adjusted
to increase tool life [6]. Lakshman Rao et al [7] highlight the
role of tool geometry in their investigation, because tool
geometry plays a major role in FSW. Proper selection of a tool
17
over which the torque is applied increases with shoulder

diameter. As a result, the product of these two components
shows the trend indicated in the Fig.3. The sliding torque,
increases continuously with increasing shoulder diameter due
Ramulu [13] used a WLa alloy tool to study FSW of Ti6Al

4V alloy. Tools made of a tungsten alloy Densimet (composition
not reported) were used by Yadava et al [14] to weld AA 6111T4 aluminium alloy. Table 4 shows properties of tool materials.
TABLE 4 - PROPERTIES OF COMMON TOOL MATERIALS [11]
Tool geometry
Tool geometry affects the heat generation rate, traverse force,
torque and the thermo-mechanical environment experienced
by the tool. The flow of plasticised material in the workpiece is
affected by the tool geometry as well as the linear and rotational
motion of the tool. Important factors are shoulder diameter,
shoulder surface angle, pin geometry including its shape and
size, and the nature of tool surfaces [12]. It was also observed
from the previous data that the friction stir weld tool geometry
has a significant effect on the weldment reinforcement, micro
hardness, and weld strength.
to the larger contact area. With the increase in shoulder diameter

the total torque increases continuously even when the sticking
torque decreases for large shoulder diameters.
Shoulder diameter
In order to determine the optimum tool geometry, the two
components of the torque are plotted in Fig. 4 for various
shoulder diameters. As the shoulder diameter increases, the
sticking torque, increases, reaches a maximum and then
decreases [4]. This behavior, which shows that two main factors
affect the value of the sticking torque. First, the strength of the
material, shear stress decreases with increasing temperature
due to an increase in the shoulder diameter. Second, the area
Figure 3. Total torque required during FSW of AA6061 as a function

of the tool shoulder diameter for rotational speeds
of 900, 1200 & 1500 rpm [3].
18
FRICTION STIR WELDING
wear compared with super abrasives due to their relatively

lower high temperature strength and hardness [12]. Mohanty
et al [9] investigated the effects of different friction stir welding
tool geometries on mechanical strength and the microstructure
properties of aluminum alloy welds. Three distinct tool
geometries with different types of shoulder and tool probe
profiles were used in the investigation according to the design
matrix.
Pin (probe) geometry

Friction stirring pins produce deformational and frictional
heating to the joint surfaces. The pin is designed to disrupt
the faying, or contacting surfaces of the work piece, shear
material in front of the tool, and move material behind the tool.
In addition, the depth of deformation and tool travel speed are
governed by the pin design [3].
The effects of each tool shoulder and probe geometry on the

weld was evaluated.
Figure 4. The computed values of sticking, sliding and

total torque for various shoulder diameters at 1200rpm [3].
Figure 5. Micro hardness profile for various tool geometry [8].
Tool cost
While the energy cost for the FSW of aluminium alloys is
significantly lower than that for the fusion welding processes
[25] the process is not cost effective for the FSW of hard
alloys. Tools made of pcBN are often used for the welding of
hard materials. However, pcBN is expensive due to high
temperatures and pressures required in its manufacture [12].
Santella et al [22] did an approximate cost benefit analysis for
FSW with a pcBN tool versus resistance spot welding (RSW)
of DP 780 steel. The equipment and utility costs for FSSW
were assumed to be 90 and 30% respectively of the costs in
RSW; however, they did not report the dollar amounts of these
costs. They further assumed that a typical RSW tool tip lasts
5000 welds and costs $0.65 per tip [12]. Considering the costs
involved with equipment, utility and the tool, they estimated
that in order for the FSSW to be cost competitive with respect
to RSW, each FSSW tool, costing ~$100, needs to make 26 000
spot welds. Since the cost of each pcBN tool was significantly
greater than $100 and typical tool life was between 500 and
1000 welds, they suggested lowering tool costs as an important
need. Feng et al [24] produced over 100 friction stir spot welds
on dual phase steel (ultimate tensile strength 600 MPa) and
martensitic steel (ultimate tensile strength 1310 MPa) without
noticeable degradation of the pcBN tool. The costs of Si3N4
and TiB2 tools were less than 25% of the cost of pcBN tools
[22]. Tools of WRe or WLa alloys are relatively less
expensive than that of pcBN tool but suffer considerably more
The micro hardness of weld nugget TMAZ obtained with

different tool profiles is shown in Fig. 5. It is observed that the
weld nugget exhibits a higher micro hardness compared to the
thermo-mechanically affected zone (TMAZ) and the base metal
[9].
III. CONCLUDING REMARKS
The joints of different tool pin profiles like straight cylindrical,
Taper cylindrical, triangular, square, trepezoidal and hexagonal
tool etc., with different rotational speeds, weld speeds and
axial force were reviewed in this paper. The following important
conclusions were made: Based on the literature survey, Tool
shoulder-to-pin diameter ratios play an important role in stir
zone development. The diameter of the pin is equal to the
thickness of the parts to be welded and its length is slightly
shorter than the thickness of the part. Tool material properties
such as strength, fracture toughness, hardness, thermal
conductivity and thermal expansion coefficient affect the weld
quality, tool wear and performance. Heat generation rate and
plastic flow in the workpiece are affected by the shape and size
of the tool shoulder and pin. Although the tool design affects
weld properties, defects and the forces on the tool. The pin
cross-sectional geometry and surface features such as threads
influence the heat generation rates, axial forces on the tool and
material flow. Tool wear, deformation and failure are also much
more prominent in the tool pin compared with the tool shoulder.
There is a need for concerted research efforts towards
19
development of cost effective durable tools for commercial

application of FSW to hard engineering alloys.
References
[12]. R. Rai, A. De, H. Bhadeshia and T. Deb Roy, Review: friction

stir welding tools, Institute of Materials, Minerals and Mining,
Science and Technology of Welding and Joining, Vol.16, No.4,
2011, Pp- 325-342.
[13]. P. Edwards and M. Ramulu, Effect of process conditions on
super plastic forming behaviour in Ti6Al4V friction stir
welds, Sci. Technol. Weld. Join.,14, (7), 2009, Pp.669680.
[14]. M. K. Yadava, R. S. Mishra, Y. L. Chen, B. Carlson and G. J.
Grant, Study of friction stir joining of thin aluminium sheets
in lap joint configuration, Sci. Technol. Weld. Join., 15, (1),
2010, Pp. 7075.
[15]. C. Meran, V. Kovan and A. Alptekin, Friction stir welding of
AISI 304 austenitic stainless steel, Materialwiss.
Werkstofftech., 38, 2007, Pp.829835.
[16]. W. Gan, Z. T. Li and S. Khurana, Tool materials selection for
friction stir welding of L80 steel, Sci. Technol. Weld. Join., 12,
(7), 2007, Pp.610613.
[17]. B. K. Jasthi, W. J. Arbegast and S. M. Howard, Thermal
expansion coefficient and mechanical properties of friction
stir welded invar (Fe36%Ni), J. Mater. Eng. Perform, 18,
(7), 2009, Pp. 925934.
[18]. E. A. Brandes and G. B. Brook, Smithells metals reference
book, 1992, Oxford, Butterworth Heinemann.
[19]. J. F. Shackelford and W. Alexander, CRC materials science and
engineering handbook, Boca Raton, Florida, 2001, CRC Press.
[20]. A. de Pablos, M. I. Osendi and P. Miranzo, Effect of
microstructure on the thermal conductivity of hot-pressed
silicon nitride materials, J. Am. Ceram. Soc., 85, (1), 2002,
Pp. 200 206.
[21]. J. Z. Jiang, H. Lindelov, L. Gerward, K. Stahl, J. M. Recio, P.
Mori-Sanchez, S. Carlson, M. Mezouar, E. Dooryhee, A. Fitch
and D. J. Frost, Compressibility and thermal expansion of
cubic silicon nitride, Phys. Rev. B, 2002, 65B, 161202.
[22]. M. Santella, Y. Hovanski, A. Frederick, G. Grant and M. Dahl,
Friction stir spot welding of DP780 carbon steel, Sci. Technol.
Weld. Join., 2010, 15, (4), 271278.
[23]. G. Grant, Y. Hovanski and M. Santella, Friction stir spot
welding of advanced high strength steels, Oral presentation,
Proc. DOE Hydrogen Program and Vehicle Technologies
Program Annual Merit Review and Peer Evaluation Meeting,
Arlington, VA, May 2009, DOE.
[24]. Z. Feng, M. L. Santella, S. A. David, R. J. Steel, S. M. Packer,
T. Pan, M. Kuo and R. S.Bhatnagar, Friction stir spot welding
of advanced high-strength steels a feasibility study, SAE
technical paper 2005-01-1248, SAE International, Warrendale,
PA, USA, 2005.
[25]. R. Hancock, Friction welding of aluminum cuts energy cost
by 99%, Weld. J., 2004, 83, 40.
[1].
L.V. Kamble, S.N. Soman, P.K. Brahmankar, Effect of Tool

Design and Process Variables on Mechanical Properties and
Microstructure of AA6101-T6 Alloy Welded by Friction Stir
Welding, IOSR Journal of Mechanical and Civil Engineering
(IOSR-JMCE) ISSN(e) : 2278-1684, ISSN(p) : 2320334X,
Pp.30-35.
[2]. Akos meilinger and imre torok, The importance of friction stir
welding Tool, Production Processes and Systems, vol. 6, 2013,
no. 1, Pp. 25-34.
[3]. H. K. Mohanty, M. M. Mahapatra, P. Kumar, P. Biswas and
N. R. Mandal, Effect of Tool Shoulder and Pin Probe Profiles
on Friction Stirred Aluminum Welds a Comparative Study,
J. Marine Sci. Appl., 11: 200-207, DOI: 10.1007/s11804-0121123-4, 2012, Pp. 200-207.
[4]. A. Arora, A. De and T. Deb Roy, Toward optimum friction
stir welding tool shoulder diameter, Acta Materialia Inc.
Elsevier, doi:10.1016/j.scriptamat.2010.08.052, 2010, Pp-912.
[5]. K. Elangovan and V. Balasubramanian, Mater. Des. 29, 2008,
Pp.362.
[6]. S.K. Selvam and T. Parameshwaran Pillai, Analysis of Heavy
Alloy Tool in Friction Stir Welding, International Journal of
ChemTech Research CODEN (USA): IJCRGG ISSN: 09744290, Vol.5, No.3, 2013, p 1346-1358.
[7]. M. Lakshman Rao, P. Suresh Babu, T. Rammohan And Y.
Seenaaiah, Study of Tool Geometry In Friction Stir Welding
Applications, AKGEC International Journal Of Technology,
Vol. 3, No. 2, Pp.15-18.
[8]. A.S Vagh and S. N. Pandya, Influence Of Process Parameters
On The Mechanical Properties Of Friction Stir Welded AA
2014-T6 Alloy Using Taguchi Orthogonal Array, International
Journal of Engineering Sciences & Emerging Technologies,
ISSN: 2231 6604 Volume 2, Issue 1, 2012, Pp. 51-58.
[9]. H. K. Mohanty, M. M. Mahapatra, P. Kumar, P. Biswas and
N. R. Mandal, Effect of Tool Shoulder and Pin Probe Profiles
on Friction Stirred Aluminum Welds a Comparative Study,
J. Marine Sci. Appl., 11: 200-207, DOI: 10.1007/s11804-0121123-4, 2012, Pp. 200-207.
[10]. P. Prasanna, Ch. Penchalayya and D. Anandamohana Rao,
Effect Of Tool Pin Profiles And Heat Treatment Process In
The Friction Stir Welding Of AA 6061 Aluminium Alloy,
American Journal of Engineering Research (AJER) e-ISSN:
2320-0847 p-ISSN : 2320-0936 Volume-02, Issue-01, 2013,
Pp.07-15.
[11]. Y. Lee, D. H. Choi, Y. M. Yeon and S. B. Jung, Dissimilar
friction stir spot welding of low carbon steel and AlMg alloy
by formation of IMCs, Sci. Technol. Weld. Join., 14, (3), 2009,
Pp.216220.
20
DETERMINATION OF NATURAL FREQUENCY
Determination of Natural Frequency of a Turning

Specimen Subjected to Random Excitation
M.Z. Hussain1, Dr. A. A. Khan2 and Dr. M. Suhaib3
1,3
Department of Mechanical Engineering, Jamia Millia Islamia, New Delhi 110025 India
Department of Mechanical Engineering, Aligarh Muslim University, Aligarh 202002 India
1
zafer.amu@gmail.com, 2aalikhan.me@amu.ac.in, 3msuhaib@jmi.ac.in
Abstract -- This paper deals with determination of natural

frequency of a turning specimen subjected to random cutting
and thrust force. In this paper, a machine tool system is modeled
as a cross-coupled linear system. The natural frequency of a
turning specimen subjected to random excitation can be
determined by using Volterra series. The Volterra series
represents the response of a system in a functional form, through
a series of first and higher order convolution integrals, involving
explicit operations on the input to the system. Exploring the
input identification procedure for the estimation of excitation
forces from the knowledge of system parameters and response of
linear cross-coupled system having cross-coupling in stiffness as
well as damping. Modeling is done for a machine turning tool
system which is being excited by random forces. The turning
specimen can be modeled as a two-degree-of freedom system
with both direct as well as cross coupling effect has to be
considered in linear stiffness and damping terms. The equation
of motion has been written in a non-dimensional form.
Illustration of procedure is done through numerical simulation.
The assumption involved and the approximations are also
discussed. The procedure for identification of response and
consecutively natural frequency is illustrated through numerical
simulation using FORTRAN language.
Chatter in turning or cutting is usually assumed to be a

regenerative process (there exist also other explanations like
thermoplastic changes in the material). Because of external
disturbance, work piece starts an oscillation relative to the
tool, producing a wavy surface. Therefore, the chip thickness
that has to be cut in the next round will also vary randomly.
Since random cutting force depends on chip thickness
fluctuation. In processes like cutting and turning the vibrations
that produce the random cutting force are orthogonal to the
rotation. But there would be a random input force in the
direction of rotation to generate chatter. In this work the input
random force is assumed to have white noise type of power
spectral density. Such white noise analysis is considered to be
an effective tool for gaining a maximum of information with a
minimum number of assumptions about the system.
In the present, analysis a two-degree of freedom turning tool
system has been modeled having cross-coupled linear damping
and stiffness parameters. The equations of motion have been
derived from the configuration of the system. These equations
are then non-dimensionalised. Laplace transforms are
employed to derive expressions for the first order direct and
cross-Kernel transforms from the non-dimensionalised
equation of motion. These first order direct and cross-Kernels
are obtained in the frequency domain, from the knowledge of
the system parameters, which are then used to estimate the
excitation force.
Keywords: Turning Specimen, Machine Tool System, Random Excitation,

Volterra Series, Cross Coupling Effect.
I. INTRODUCTION
THE AIM of this paper is to develop an algorithm that can be
used to determine the natural frequency by knowing the
response and the system parameter using Volterra series. Such
analysis have attracted considerable attention in the recent
past, partly due to growing awareness of the significance of
the Random nature of forces produced by during operation.
Indirect estimation of excitation force using model co-ordinate
transformation has been carried out by De Sanghere et.al. [1],
classification of different force identification problem has been
carried out by Stevens [2]. A study for finding inverse method
for estimation of impulsive loads has been conducted by Ma
et.al. [3]. A non-linear vibration problem of estimating the
external forces for a single degree of freedom system using
conjugate gradient method has been developed by Huang [45].
II. LITERATURE REVIEW

The forward analysis of response generation of a multi degree
of freedom system subjected to random excitation force has
been the major thrust area in the recent past. The complete
inverse analysis of determination of the forcing function is a
complex phenomenon and requires specialized techniques
particularly when the excitation is random in nature.
The methods that are being used nowadays either involves a
detailed knowledge of the material characteristics of the test
structures (finite element model approach) Dobling & Farrar
[7] or make very restrictive assumption about the excitation
Randall & Swevers [8]. Recently, a novel approach was
presented for the normalization of operational mode shapes
21
on a basis of in operational model models only Parloo &

Guillaume [9]. In this method it is shown that the operational
mode shapes can be normalized by means of the measured
shift in natural frequencies between the original and mass
loaded condition just by adding or removing, for instance one
(or more) masses (with well known weights) to the test
structures. A complete modal model can be reconstructed by
normalizing the operational mode shapes. Using this model,
an inverse problem can be formulated for the identification of
the unknown forces that gives rise to the measured responses.
In reference Guillaume, Verboven & Sitter [10] the forced
identification problem was addressed and an inverse solver
was proposed and is then compared to classical approach (e.g.
pseudo-inverse). For force identification on the basis of output
only data an experimental work has been carried out by E Parloo
et al. [13].
complex if the excitation is random in nature. The Volterra [6]

series provides a basis for these requirements. The basic theory
of Volterra series involves modeling the relationship between
the system response and input in terms of a series of first and
higher order convolution integrals. It employs multidimensional kernels, which upon convolution with the applied
excitation express the response in the form of a power series.
The kernels of the system are considered as multi-dimensional
unit impulse response functions.
In this paper the inverse problem of input identification is based

on the Volterra approaches, and is discussed in the context of
machine tool system. Problem involving vibration arises quite
frequently in turning process, especially those involving
random vibration of sliding contact element of machine tool
system due to varying chip thickness. Modeling of turning
process has been done by Wang and Su [17] and they
developed the relationship between the cutting force and chip
thickness fluctuation will be treated as a hysteresis model.
Wang and Su [17] have modeled the turning process as a two
degree of freedom system.
The equations of motion in the vertical and horizontal direction

relating the displacement to the forces applied to it is given by
IV. GOVERNING EQUATION OF MOTION

A cutting tool used for plain turning operation can be
represented as shown in Fig.4.1, where the flexibility is
represented by eight springs & damping coefficients is
discussed earlier. The excitation forces are denoted as the
thrust and main cutting forces exciting the structure.
Figure 1. A plain turning tool system with cross-couplings.
The Volterra kernels extraction is proposed for the estimation

of fourteen-linearised machine tool parameter subjected to
random cutting force by Khan and Khan [12]. The procedure
developed gives very good engineering estimates of the
machine tool parameters. It can be shown that the large sample
size is preferable for obtaining sharp peaks which gives more
accurate results. It has been also found that the procedure
developed is robust to the measurement noise and can be
successfully employed for modeling of the setup.
mx&&+ cxx x&+ cxy y&+ k xx x + k xy y = F1 (t )
(1)
my&&+ c yx x&+ c yy y&+ k yx x + k yy y = F2 (t )
(2)
where m is the mass, cxx , c yy are direct linear damping terms;

are cross-coupled linear damping coefficients and
are the direct linear stiffness terms, while
are
the cross-coupled linear stiffness term.
, represents
the excitation forces given to the system in x and y direction in
the above equation
In order to write the equation of motion in a non-dimensional
form, let us define
III. MACHINE TOOL SYSTEM

Problems involving vibration arise quite frequently in machine
tool application, especially those involving random vibrations
of cutting tools and tool chatter, excited by random cutting
force. In some cases, deterministic models prove to be
inadequate or at least extremely complex and the phenomenon
can be adequately described only within the framework of
statistical models. Statistical dynamics concerned with the
study of various random phenomena in dynamic systems
enriches the classical basic theory of oscillations and extends
the possibilities for its applications to the description and
analysis of real response processes in dynamic systems.
Inverse problems in vibration analysis require techniques with
rigorous theoretical base, which provide valid routes to input
identification. Further the estimation procedure becomes more
22
cross-coupled first order kernels are obtained from the

knowledge of the system parameters. Typical sample of
excitation force used for simulation is shown in Fig. 2. Volterra
kernel transforms exhibit the two fundamental frequencies of
the system, as it is a two-degree of freedom system. The
excitation force has been estimated using these kernels and
response. Figure 3 shows the Power spectrum of input force.
Figure 4 shows the FFT of the simulated excitation force
averaged over the ensemble of 2000 samples and is used for
both x and y directions for the case. The corresponding
estimated force can be seen in Fig 4.11 and can be compared
with the simulated force as shown in Fig. 4. The error in the
estimate that is the difference between the Fig.4 (simulated
force) and Fig. 7 (estimated force) can be seen in Fig. 8.
V. COMPUTER SIMULATION
The input identification procedure is illustrated through
numerical simulation of the response for the non-dimensional
coupled equation (3) and (4). The forcing functions chosen for
response simulation are normalized zero mean random forces,
and
. The excitation forces are simulated through
random number generating subroutines and are normalized
with respect to their maximum values. The governing equations
are then numerically solved using a fourth order Runge-Kutta
method, to obtain the responses in and directions (
and )
from equations (3) and (4). Using FFT the power spectrum of
the response averaged over the ensemble of 2000 samples is
determined.
F211i(=
())0.094358
))
(yxf
Owing to the statistical nature of the problem, the procedure is
illustrated for various sets of direct and coupled stiffness and
damping parameters. The case studied for a particular set of
stiffness as well as damping parameter have been designed to
find the natural frequency of the system using the algorithm
developed.
Figure 2. Typical sample of normalized input force.
VI. RESULTS AND DISCUSSION

Case I:
Figure 3. Power spectrum of input force.
For the above set of values of the parameters, the response is

computationally simulated using equations (3) and (4). The
governing equations are then numerically solved using a fourth
order Runge-Kutta method, to obtain the responses in and
directions (
and ). Their corresponding power spectrums
averaged over 2000 samples are shown in Fig. 5 and 6. From
the power spectrum of the responses the fundamental
frequencies of the system are found to be as
per
unit of non-dimensional frequency 2 =0.256031 and per unit
of non-dimensional frequency these responses are fed as inputs
to the input identification algorithm. The various direct and
Figure 4. Fast Fourier Transform of the simulated input
23
VII. CONCLUSION AND SCOPE FOR FUTURE WORK

The present work is primarily concerned with the determination
of two fundamental frequencies of cross-coupled turning tool
systems. Volterra theories have been employed for the analysis
of the problem. A frequency domain approach has been adopted
in order to reduce the computation time. The coupled systems
considered are machine tool system. The work piece mounted
on chuck with cross coupling in damping and stiffness has
been considered.
Figure 5. Power spectrum of the response
Figure 6. Power spectrum of the response
The input identification procedure in cross-coupled system is

developed in steps. This serves to illustrate general nature of
the procedures adopted for identification of excitation force,
which are random in nature. Few case studies have been carried
out with different sets of non-dimensional parameters in order
to check the accuracy of estimated forcing function. The
accuracy of the estimates with various other non-dimensional
parameters and level of excitation can be expected to follow
the same trends as discussed. The response of the system is
expressed through first order direct and cross Volterra kernels.
These Volterra kernels are then processed to estimate the
excitation force. Reasonably good estimates are found for
different sets of both linear damping and stiffness parameters.
: Case 1.
The excitation force are found to be estimated with a good

degree of accuracy in given case, if the programme run for
other cases also however the accuracy of the estimates are
found to vary with the values of non-dimensional parameter
chosen for simulation. The present study can be used to design
experiments to choose appropriate set of excitation levels for
the expected sets of parameters. This work can be extended to
include the kernels of higher order to increase the accuracy of
estimates. Further we are considering stiffness and damping
to be linear in order to keep the algebra simple, however an
extension to the present work can be made by considering
non-linearity in damping and stiffness.
: Case 1.
In the present work we have considered the tool to be rigid.

Future work needs to be carried out by taking into consideration
the flexibility of the tool. The effect of ensemble size is also
studied. It has been found that accuracy of the estimates
increases with the ensemble size. In the present study the
ensemble size of the force and the response is kept 2000, to
limit the computation time. Future work can be carried out by
increasing the ensemble size in order to increase the accuracy
as well as frequency range of force identification.
Figure 7. Estimate of the input force F1(): Case I.
The analytical development in the present work needs to be

validated through experiments in laboratory as a future work.
Further experimental work needs to be carried out on turning
tool system, milling cutters, drilling tool as well as broaching
tool.
Figure 8. Estimate of the input force : Case I.
24

[13]. E. Parloo P. Verboven P. Guillaume and M. Van Overmeire
Sensitivity-based damage assessment technique for outputonly data, Proc. Third International Workshop on Structural
Health Monitoring, Sanford, CA, 2001.
VIII. REFERENCES
[1].
G. Desanghere and R. Snoeys, Indirect Identification of

excitation of Excitation force by Modal Co-Ordinate
Transformation Proceedings of the international modal
analysis conference, Orlando, FL, 1985 , pp. 685-690.
[2]. K.K. Stevens, Force Identification Problems-an Overview,
Proc. SEM Spring Conference on Experimental Mechanics,
Houston. 1987, pp.838-844.
[3]. C.K. Ma, P.C. Tuan, D.C. Lin and C.S. Liu, A study of an
inverse method for impulsive load estimation, International
Journal of System Science, Vol. 29, 1985, pp. 663-672.
[4]. C.H. Huang, An inverse non linear force vibration problem
of estimating the external forces in a damped system in time
dependent system parameters,Journal of Sound and Vibration
242, 2001, pp 749-756.
[5]. C.H. Huang, A Nonlinear Inverse problem of estimating the
external forces for a system with displacement dependent
parameters, Journal of Sound and Vibration, 248, No. 5,
2001, pp. 789-807.
[6]. V. Volterra, Theory of functional and of Integral and Integro
Differential Equations, Dover publications, Inc., New York,
1959.
[7]. S.W. Docbling. C.R. Farrar, Computational of structural
flexibility for bridge health monitoring using ambient modal
data Proc. 11th
ASCE engineering mechanics
conference.1996. pp. 1114-1117.
[8]. R.B. Randall, Y. Gao, J. Swevers, Updating modal models
from response measurements, Proc. 33rd International
Conference on Noise and Vibration Engineering (ISMA23)
1998, pp. 1153-1160.
[9]. E. Parloo, P. Verboven, P. Guillaume, M. Van Overmeire
Sensitivity-based mass- normalization of mode shape
estimates from output-only data, Proc. International
Conference On Structural System Identification, Kassel,
Germany, 2001, pp. 627-636.
[10]. P.Guillaume, E.Parloo, P.Verboven and G.DeSitter, An inverse
method for the identification of localized excitation sources,
Proc. 20th International Modal Analysis Conference (IMAC20),
2002.
[11]. Jian Wang and Chun-Yi Su, Two Degree-of-Freedom Modeling
and Robust Chatter Control in Metal Cutting by
Piezoelectricity, Proc. 42nd IEEE Conference on Decision and
Control Maui, Hawaii USA, December 2003.
[12]. A.A Khan and A.H. Khan, Identification of machine tool
parameters under random cutting force, Proc. AIME-2006,
Jamia, New Delhi pp75-85.
Md. Zafer Hussain received the B. Tech.

degree in Mechanical Engineering from Aligarh
Muslim University (AMU) Aligarh, Aligarh,
Uttar Pradesh in 2004, and the M. Tech. degree
in Mechanical Engineering with specialization
in Machine Design from AMU Aligarh, Aligarh,
Uttar Pradesh in 2007, and Pursuing Ph.D. in
Mechanical Engineering from Jamia Millia
Islamia (A Central University), New Delhi,
respectively. Currently, he is a research scholar
of Mechanical Engineering at Jamia Millia
Islamia, New Delhi. His teaching and research areas include Vibration,
Robotics, Mechatronics, Mechanism & Automation, Nonlinear
Dynamics, System Identification, etc. He is currently writing a Textbook
and authored many research papers.
Dr. Ahmad Ali Khan received the B.S. degree

in Mechanical Engineering from Aligarh
Muslim University, Aligarh, Uttar Pradesh in
1987, the M.S. degree in Mechanical
Engineering from AMU Aligarh, Aligarh, Uttar
Pradesh in 1992, and the Ph.D. degree in
Mechanical Engineering from Indian Institute
the Technology, Kanpur UP in 2000
respectively.
Currently, he is Professor of Mechanical
Engineering at AMU Aligarh. His teaching and
research areas include Nonlinear Dynamics, System Identification, Smart
Structures, etc. He has authored/co-authored many research papers.
Dr. M. Suhaib received the B.Sc. Engg degree

in Mechanical Engineering from the Aligarh
Muslim University, Aligarh, U.P, in 1990, the
M.Sc. Engineering degree in Machine Design
from the Aligarh Muslim University, Aligarh,
U.P, in 1993, and the Ph.D. degree in
Mechanical Engineering from the Jamia Millia
Islamia, New Delhi, 2004, respectively.
Currently, he is a Professor of Mechanical
Engineering at Jamia Millia Islamia. His
teaching and research areas include Robotics,
Mechatronics, Mechanism and Automation. He has authored/coauthored two textbooks & approximately fifty research papers.
25
Circuit Architecture for Photon Counting Pixel

Detector with Threshold Correction
Dr. Amit Kr. Jain
Vidya college of Engineering, Vidya Knowledge Park, Baghpat Road, Meerut 250005 UP India
dean.academics@vidya.edu.in
Abstract -- In the hybrid pixel detectors, the detector and the

readout circuit are constructed separately and then connected
electrically by flip-chip bonding. This concept allows the same
readout chip to operate using different sensor materials. In photon
counting readout, it takes into account the noise around the
signal, and other effects such as the variation of amplifier gain
and the signal offset. To have a good efficiency for the signals
charge, the comparator threshold setting is needed to be low
enough. In this paper, a photon counting pixel detector readout
with threshold correction is implemented as a solution for the
missing counting of the signal due to the offset problem. The
additional circuits needed for this architecture, lead to an increase
in power consumption and only a marginal increase in circuit
area. It is implemented in a 120-nm CMOS process and the
presented results are based on simulations.
readout with the threshold correction is shown in Figure 1.

The circuit contains an analog signal processing and digital
circuitry. The analog parts consists of a charge sensitive
amplifier; a shaping filter, four discriminators and include pileup rejecters, as the design of this circuit involved a 120nm
CMOS process using a power supply voltage of 1.2 V. In this
case a current mode circuit was used which means that the
signals are represented by a current. The current mode circuits
could be a better choice as the power supply voltages are
lowered, since the signal swing is indirectly limited by a
reduction of the available supply voltage range [2]. The digital
part consists of (AND gate), Sum circuit, All Digital Window
Discriminator (ADWD) and an event counter.
Keywords: Threshold, Photon-Counting, Pixel, Noise, Discriminator.
I. INTRODUCTION
READOUT circuits for photon counting image sensors are
based on analog and digital circuits, such as the Medipix 2 [1].
Photon-counting pixels contain complex circuitry, which means
that the pixel design is mainly driven by area, power
consumption and mixed mode design constraints. In photon
counting pixel readout of X-rays if a pixel does not have
excellent X-ray sensitivity, a low energy threshold and a low
noise contribution, then attempts to correct intensity
measurements may fail because small changes in threshold
can lead to significant alteration in detection efficiency.
Because small variations in threshold make it very difficult to
avoid missing counts. To solve this problem four discriminators
per pixel instead of double discriminators are used. For low
discriminator level, the circuit consists of sum circuit and two
comparators, one of the comparator work as a threshold
correction. For high discriminator level, the circuit consists of
two comparators and (AND gate). For improving threshold
uniformity, the circuit is equipped with two 5-bits analog to
digital converters DACs. One of the DAC is used to bias the
feedback transistors of the preamplifier and the shaper. The
second DAC set the threshold voltages ThLL, ThLH, ThHL, and
ThHH in the comparators see (Figure 1).
Figure 1. Simplified block diagram of the photon

counting pixel readout.
Charge Sensitive Pre-Amplifier: The charge sensitive amplifier

(CSA) is widely used at the front-end electronics in radiation
detectors as its conversion gain is independent of anode
capacitance variation because the charge released by the
detector is directly integrated on the feedback capacitor [3].
Then its gain is not sensitive to a charge in detector capacitance.
The CSA is a cascade structure as shown in Figure 2 has a
peaking time of 20ns and a bandwidth of 2.8 MHz at 3-dB and
a gain of 25. In terms of power consumption the CSA uses 840
nW in the active mode. The input transistor M1 is nMOS
transistor with minimum channel length, in order to minimize
series white noise the width of transistor is selected to give
minimum noise [4]. The bias input current is fed at the gate of
transistor M1 falls within the range of 100 nA. Transistor M2
constitutes the cascade. Current is supplied to the M1 node
II. METHODOLOGY
A block diagram of the circuit architecture of Photon counting
26
PHOTON COUNTING PIXEL DETECTOR
via a cascade current source (M4 and M3), which sets M1 in

the region of operation [5]. Transistors M2, M3 and M4 are
externally biased. In order to drive a low-impedance load, double
source followers, transistors (M5 - M8) are used in this design
to provide a low-impedance output to drive the following pulse
shaper stage. The main noise contribution to the total noise of
the preamplifier comes from the M1 input, although the noise
contribution from the cascade current source is not negligible
due to the low power supply and the limited voltage available
to degenerate them [6]. The discharging feedback resistor is
formed by the drain-source resistance (Rds) of transistor Mf,
which is biased by the current DAC to operate in the saturation
in quiescent conditions and it enters in strong inversion when
a charge signal is detected [7].
The selected pulse shaper must remove low and high

frequencies to control signal pile-up and limit the band width.
However, while improving the output noise level by limiting
the bandwidth, pulse shaping without gain will result in loss
of signal and may possibly not provide any real improvement
to the output SNR. The amplifier used in the pulse shaper is
the same as the one used in the CSA. It is a cascade structure
as shown in Fig. 3.
The pulse shaper amplifier has a shaping time of less than
250ns and a bandwidth of 2.4MHz. The simulated noise figure
is 42 dB less than CSA as expected; the noise figure is greatly
reduced by the pulse shaper. The input transistor M2 receives
the signal from CSA via transistor Mi. Current is supplied to
the M2 node via a cascade current source (M4 and M9). The
second stage of the pulse shaper (not discussed in this paper)
consists of a push-pull cascade current source amplifier. In
figure 3, the output signal OUT of the pulse shaper is fed to a
push-pull cascade current source amplifier. In term of power
consumption the first stage of pulse shaper uses 246nW in the
active mode whereas the second stage increases the power
consumption. The shaping time is controlled by the drainsource resistance Rds of the PMOS transistor Mi which is
biased by the signal STC that comes from external current
mirror. Bias voltages (B1, B2, and B3) come from a bias network,
which is common to preamplifier, shaper and comparators. Mf
is controlled by the current DAC that allows adjustment of the
current simultaneously by the external current.
The frequency behavior of the CSA is determined by the

feedback capacitor Cf and the total parasitic capacitance on
the high input impedance node. This capacitance consists of
the parallel combination of drain capacitances of transistors
M3 and M4, input capacitance and gate capacitance of the
subsequent stages.
Comparator: In photon counting X-ray imaging the signals

appear randomly in time and independently in each pixel. After
receiving a charge signal from the detector, and having been
integrated and shaped, there is a requirement to implement a
threshold discriminator in each pixel. In X-ray imaging
techniques it is sufficient to measure the spatial distributions
of the X-rays of energies above a given threshold (integral
discriminator type) or within a given energy window (window
discriminator).
Figure 2. Circuit diagram for pre-amplifier.
Pulse Shaper: The signal detected by the CSA in photon

counting readout electronics will generally not be used directly,
but will be amplified and shaped. The aim of these procedures
is to optimize the signal to noise ratio [8].
Figure 3. Circuit diagram of pulse shaper.
Figure 4. Schematic diagram of comparator.
27
In the integral discriminator, a comparator outputs a logical

signal every time the amplitude exceeds a preset threshold.
This is the main feature characterizing the single photon
counting in comparison to an integrating pixel. This is because
the signal amplitude at the shaper output contains information
about the charge generated in the detector [3]. In the window
discriminator type, two comparators are used to output
appropriate pulses when the input exceeds a lower threshold
and is below an upper threshold.
The comparator is implemented as a cascade current differential
amplifier, see Fig. 4. The circuit, made up of the transistors M1
M8, consists of low voltage cascade current mirrors with the
output current of the first subtracting from the input of the
second. The current in point A equal (Iin - Ith). Where Iin is the
input current from pulse shaper and Ith is the threshold current
setting by the current DAC. The value of the subtracting current
is fed to the push-pull cascade current source, transistors (M9
-M14) to generate a voltage output pulse.
Figure 6. Block diagram of the thresholds setting.
D/A Converter: In the mode of D/A converter, voltage, current

and charge, the current mode conversion in conversion rate
has the advantage that voltage swings in the circuit are
minimized, which ultimately reduces the sensitivity for parasitic
capacitance. In our design, we chose current mode conversion
for R-2R ladder D/A converter. The basic structure of digitalto-analog converter is R-2R configuration. Since CMOS switch
is not ideal, the resistance of switch affects the accuracy of R2R network, we adopt CMOS transistors to replace R-2R
resistors. CMOS R-2R ladder is based on a linear current
division principle [11].
Sum circuit: The schematic of the Sum current circuit is based

on the current-mode CMOS multiple valued logic circuits [10],
is shown in Figure 5. The circuit received two clock signals
from comparators it form lower threshold discriminators LL
and LH that drive PMOS switch transistors M6 and M7. The
sum of signals is the threshold value. NMOS transistors M4,
M5 each provide current to PMOS switches M6 and M7 that
are controlled by signal LL and LH respectively. These two
low-level currents thresholds are summed at the drain of PMOS
transistor M17. This current is fed to the double push-pull
cascade current source, transistors (M8 -M15) in order to
generate a voltage output pulse.
Figure 7. Block schematic of the 5-bit current DAC.
The input current supplies a current source for R-2R network,

which is similar to the classical R-2R resistor ladder which
normally requires a large area and bigger power consumption.
We use CMOS transistors instead of polysilicon resistors to
reduce the area and power consumption. The linking Iout and
Iout- ports not only act as resistors, but also as switches, so
that this structure solves the problem of additional resistance
of switch. Figure 7 shows 5-bit DAC schematic of R-2R
transistor ladder, which is biased by a reference current source.
Vb is the voltage which equals the output voltage of signal
data (D0 - D4), and the low voltage of data is below the
threshold voltage of CMOS transistors. Iout is the output
current of ladder. Iout- is the dump current of ladder.
Figure 5. Schematic diagram of sum circuit.
Figure 6 shows a simplified block diagram of the 4 comparators

threshold setting. The signals ThLL and ThHL are the threshold
setting at the normal state (no offset), and the signals with
dotted lines ThLH and ThHH are the threshold setting at the
offset state.
28
PHOTON COUNTING PIXEL DETECTOR
III. SIMULATION RESULTS

The complete circuit was simulated in a 120 nm CMOS process.
Both analog and digital circuitry have been designed to operate
with 1.2 V power supply.
Figure 8. Simulation of 5-bit DAC.
In the DAC we used current mirror as the output stage. The

DAC supply their output currents directly to the current mirrors
M1, M2, M3 (Figure 7). Due to the channel modulation effects,
the effective ratio of the drain current in M1 and M2 depends
on drain-source voltages of both transistors, which are
functions of the current fed into transistor M1 and the load
transistor M3. Figure 8 shows the output current of the DAC
with differential nonlinearity and integral nonlinearity error in
Figure 9.
Figure 10. Simulation result of the circuit without

offset input signal.
Figure 9. Differential and integral nonlinearity errors.
Figure 11. Simulation result of the circuit with offset input signal.
29
Simulation result of the sum circuit at the lowers discriminator

setting, when the shaper signals without offset as shown in
Figure 10. The discriminator generates two clock signals LL
and LH that are input to the sum circuit, the output from the
sum circuit is almost less than LL signal and bigger than LH.
Figure 11 shows the clock signal when shaper signal include
offset.
[6].
[7].
[1]
IV. CONCLUSION
In this paper we have introduced architecture for a photon
counting pixel detector readout with threshold correction for
the comparators is implemented as a solution for the missing
counting of the signal due to the offset problem. The additional
circuits needed for this architecture, leads to an increase in
power consumption and in circuit area. It is implemented in a
120nm CMOS process and the presented results are based on
simulations.
[2]
[3]
[4]
V. REFERENCES
[1].
[2].
[3].
[4].
[5].
P. OConnor and G. De Geronimo, Prospects for charge

sensitive amplifiers in scaled CMOS, in IEEE Nuclear Science
Symp. Conf. Record, Vol. 1, Oct. 1999, pp. 8993
M. Pedrali, et al., PETRIC- A Positron Emission Tomography
Readout Integrated Circuit, IEEE Transactions on Nuclear
Science, Vol. 48, No. 3, June 2001
Larry T, Wurtz and W. Perry Wheless, Pulse Shaping for
Low-Noise, Charge Preamplifiers, IEEE Transaction and
Measurement. Vol. 42, No. 5, October 1993
B. Oelmann, et al., Robust Window Discriminator for PhotonCounting Pixel Detectors, IEE Proceedings of Optoelectronics,
Vol. 149, No. 2. April 2002.
K. Wayne Current, Current-Mode CMOS Multiple-Valued
Logic Circuits, in IEEE Journal of Solid-State Circuits. Vol.
29, No. 2. February 1994.
Klaas Bult, and Govert Geelen, An Inherently Linear and
Compact MOST-Only Current-Division Technique, IEEE
JSSC, Vol. 27, No.12, pp. 1730-1735, Dec. 1992.
Dr. Amit Kr. Jain is Director / Professor /

Advisor as well as Founder Director of various
Centres /Institutions.
Obtained Ph.D, M.Tech & B.Tech in
Electronics & Communication Engineering.
Also, had a Ph. D (Management) from Amity
University, Noida & MBA (IMT Ghaziabad).
Published over 81 research papers. Authored
eight books, co-authored four books and coedited 15 conference proceedings.
Delivered Invited lectures in over 30 Technical
and Management Workshop / Conference programs. Organized over
45 Conferences, Workshops, Faculty Development Programs and
attended over 18 advance courses.
He is a member of board of governance, advisory council, academic
executive member, board of studies and special member of many Indian
and foreign universities as well as industry. He is Editor-in-Chief,
Technical Committee Member, Advisory Board Member for over 15
technical journals.
X. Llopart, M. Campbell, R. Dinapoli, D. san Segundo and E.

Pernigotti, Medipix2, a 64k pixel readout chip with 55 m
square elements working in single photon counting mode,
IEEE Transactions on Nuclear Science, Vol. 49, pp. 22792283, October 2002.
Bengt E. Jonsson Switched-Current Signal Processing and
A/D Conversion Circuits- Design and Implementation, ISBN
0-7923-7871-7.
Suliman Abdalla, Bengt Oelmann, Mattias ONils, Jan
Lundgren, Architecture and Circuit Design for Colour X-ray
Pixel Array Detector Read-out Electronics, Proceedings of
the IEEE Norchip Conference, pp. 271-276, 2006.
P. OConnor et al., Readout Electronics for a High-Rate CSC
Detector, Fifth Workshop on Electronics for LHC
Experiments, Snowmass Colorado, September 1999.
M. A. Abdalla, C. Frjdh, C.S. Petersson, A New Biasing
Method for CMOS Preamplifier-Shaper, Proc. Of the 7th
IEEE Intl. Conf. on Electronics Circuits and Systems, pp. 1518, 2000.
30
PUBLIC SECTOR COMPARATOR
Public Sector Comparator: A Useful Decision Making

Tool in Infrastructure Development
Akhil Damodaran
College of Management and Economic Studies, University of Petroleum and Energy Studies,
Kandoli Campus Knowledge Acres, Vill. kandoli, PO Bidholi via Premnagar, Dehradun, 248007
Uttarakhand, India
such enterprises cannot take the challenge by adopting modern
techniques, new management and marketing skills and
practices. Hence, inevitably private participation is allowed in
large scale in all infrastructure service provisions. However,
private monopoly will be equally bad and this has necessitated
the regulation of infrastructure facilities and provisions in the
country. Hence even today, the Public sector is seen as essential
to produce a competitive market where both private sector and
public sector should compete each other in the same market.
Abstract -- The public sector comparator (PSC) is an estimate of

the net present cost to government if it has to deliver the project
under a more traditional procurement method. The PSC contains
forecast lifetime cash flows delivered from a reference project
based on the infrastructure and services based on the
specifications provided to bidders, i.e. on a like-for-like basis to
the PPP.
This paper focuses on exploring value for money concept and
whether Public Sector Comparator is a right tool to measure it.
The overall paper is an exploratory analysis. For this purpose,
literature from World Bank data bases, Department of Treasury
Western Australia and other relevant sources were explored.
It is expected that the Public Sector Comparator would develop
as a useful and effective tool in the decision-making process for
choosing partners in infrastructure projects.
As per second report of the high level committee financing of

infrastructure India's average investment in infrastructure was
4.7 percent of GDP during 1992-2010 compared to an average
of 7.3 percent across China, Indonesia and Vietnam. India ranks
85 out of 144 countries, as per the World Economic Forum
Global Competitiveness Report 2014, in terms of infrastructure
quality with 'inadequate supply of infrastructure' listed as the
most problematic factor in doing business. Its important for
policymakers to focus more on infrastructure growth by
creating conducive environment for growth. In this regard it is
more important to note that public utility infrastructure plays a
significant role in the infrastructure growth of a country. One
of the most important aspect is to consider whether financing
an infrastructure fully through government or fully private or
going for PPP is the best option particularly in terms of value
for money estimation and how to estimate it.
Keywords: Public Sector Comparator, Public-Private Partnership,

Infrastructure Projects..
I. INTRODUCTION
THE fast growth of the economy in the past 10 years has
placed increasing importance on physical infrastructure such
as electricity, railways, roads, ports, airports, irrigation, water
supply and sanitation.They are important for economy as far
as growth is concerned. The current target growth rate of
economy can only be sustained if this infrastructure deficit is
overcome and adequate investment takes place in support of
higher growth for an improved quality of life, both for urban as
well as rural communities. A competitive market alone cannot
assure the required infrastructure facilities and services. This
often justifies for government involvement by directly
providing infrastructure services through Public Sector
Undertakings.
One of the important tools to estimate value for money is public

sector comparator. The following paragraph will explain the
importance of Public Sector Comparator in the evaluation of
Public sector performance. As per government of Western
Australia (Department of Treasury) Assessment of a PPP offers
value of money is an essential part of a PPP procurement
process. This entails comparing the PPP proposals with the
cost of the public sector undertaking on the project. The public
sector comparator (PSC) is an estimate of the net present cost
to government if it has to deliver the project under a more
traditional procurement method. The PSC contains forecast
lifetime cash flows delivered from a reference project based on
the infrastructure and services based on the specifications
provided to bidders, i.e. on a like-for-like basis to the PPP.
However, this approach has failed miserably in many countries

including in India because of many reasons. Creating
Government monopoly could not provide the efficiency and
performance and quality of service. This led to government
thinking in terms of moving away from the Government control
to Private participation in the infrastructure service provision
in the country. State owned public sector undertakings by
virtue of their ownership have been shielded from competition.
Government ownership arbitrarily brings with it a bureaucratic
style of decision making . In a competitive business scenario
As per the World Bank "The PSC estimates the hypothetical
31
risk-adjusted cost if a project were to be financed, owned and

implemented by government. PSC provides a benchmark for
estimating value for money from alternative bids. Once final
bids are received from the private sector, the whole of life cost
of these bids are compared with the PSC to determine whether
the bids submitted provides a better value for money to the
taxpayer.
public (government) authority and a private (non-government)

entity by which services that are the obligation of or which
have traditionally been provided by the public authority would
now be provided by the private entity under a contractual
arrangement containing well-defined terms and conditions.
Under this arrangement, the obligation to provide such services
and consequent accountability to users would continue to
vest with the public authority; though it chooses to deliver
them through an entity best suited for this purpose.
According to the Treasury Task Force (TTF, 1998):
It is expressed in net present value (NPV) and/or net

present cost (NPC) terms.
It is based on recent actual public sector methods of

providing defined output (including any reasonably
foreseeable efficiency the public sector could make).
It takes full account of the risks which would be

encountered by that Method of procurement.
As per United Nations foundation true public-private

partnerships begin by identifying the central problem, then
asking who should help to solve it. They may be initiated from
the private, government or civil society sector, but they are
not about the narrow plan of any one partner. Public-private
partnerships are around shared programs and mutual
resources, risks, rewards, and linkages that can magnify scale.
II. KEY ATTRIBUTES

Key attributes of a PSC include
It is forecast based on the reference project reflecting

the cost to government of delivering the project
Infrastructure and services to the same standards as

being procured from the private
Sector under the most likely traditional procurement

model if not a PPP;
It is expressed in net present cost (NPC) terms;
It is based on life-cycle costing i.e. the whole life cost

of providing the services and
Maintaining the infrastructure to standard prescribed for

the PPP; and
It is risk-adjusted valuation
It is also important to understand the concept of PPP to

appreciate the significance of Value for money concept
and Public sector Comparator.
True public-private partnerships:
Are voluntary and build on the respective strengths of

each partner;
Optimize the allocation of resources; the partnership,

governance, as well as exit arrangements.
IV. PUBLIC SECTOR COMPARATOR
It is always important for policy makers to understand the
viability of doing a public private partnership and to understand
whether it is important to go for a PPP mode or not. One of the
important tool which is used for choosing the private player
for PPP investment is Public Sector Comparator.
Components of PSC: A PSC comprises cash flows associated
with:
The raw PSC;
An adjustment for competitive neutrality; and
An adjustment for project specific risks (retained and

transferred).
Public-private partnership (PPP) in infrastructure is a relatively

new experience in most developing countries of the Asian and
Pacific region. Although many governments have considered
various steps to promote PPPs in their countries, lack of
capacity in the public sector remains to be one of the major
problems in implementing PPP projects. So far, only few
countries have established institutional arrangements and
developed manuals and resource materials in support of PPP
development and for the capacity-building of their public
officials. The question still arises whether PPP is the right value
model. This paper focuses on exploring value for money
concept and whether Public Sector Comparator is a right tool
to measure it. The overall paper is an exploratory analysis. For
this purpose different literature from World Bank data bases,
Department of Treasury Western Australia and other relevant
literature were explored to understand PSC.
All future project cash flows are converted to a net present

cost by applying the appropriate discount rate
The raw PSC includes the expected capital and operating costs
to government of delivering the reference project over its full
term before any risks are taken into account.
Competitive neutrality adds to the PSC the net competitive
advantage that accrues to Government by virtue of its
government status. This ensures a like for like comparison
with bids received.
Project Specific Risk: The risk is possibility of outcome as
better or worse than expected. In terms of PPP, project specific
risk is the risk that the actual cost of delivering the project
III. DEFINITION OF PPP

Public private partnership (PPP) is an arrangement between a
32
which will be different to that of forecast based on the

information available at the time of the forecast. It is important
to note that in PSC calculation the risk is included because the
transfer of risk is one of the key objectives of PPP procurement
and the price to government of transferring risks is included in
private sector bids.
c.
d.
e.
It provide a means for testing value for money

It provides a consistent benchmark and evaluation tool
It encourages competition by generating confidence in
the market that financial rigors and probity principle are
being applied.
The figure explains how public and private services are

compared . When the private sector expected cost is lower
than public , then the value for money is higher and the project
can be better run by private concessionaires.
Steps used in the process of using Public sector comparator
Before a VFM assessment can be directed, the following steps

must be undertaken in order to protect the correctness of the
model proposed:
Identify the variable, parameter and methodologies to

be used to assess VFM.
Select appropriate modeling software to outline key

weakness.
Identify the output or input specification, performance

standards and payment mechanism for the project.
Identify the contracts base costs, program and network

of activities (Value-based inputs).
Identify and insert risks linking them to specific activities

(risk-based inputs).
Adjust for competitive neutrality (hypothetical costbased inputs).
Carry out tests and simulations of the model.
Analyze simulated outputs normally in terms of economic

parameters
PSC can perform the following roles

a.
It promotes full costing at an early stage in project
development.
b.
It provides a key management tool in the procurement
process by focusing attention on the output
specification, risk allocation, and comprehensive costing.
It is important to note that Public Sector Comparator (PSC)

has its own defects which need to be minimized throughout
Value for money for PSC is explained in the following diagram
Source : World Bank
33
its lifecycle and that can be done through sensitivity analysis.

The diagram briefly explains how sensitivity analysis is done.
the underlying calculations and erroneous interpretation of

the results.
Tne important parameter to increase the robustness of PSC is

to perform a sensitivity analysis as explained in the following
table.
There are likely to be qualitative and non-financial differences

between the options that cannot simply be subsumed in a
difference in forecast cost.
(source:http://www.treasury.wa.gov.au/)
V. CONCLUSION
Public Sector Comparator (PSC) calculation is one of the most
useful tools used to perform value for money calculation for
making the decision between the PPP procurement route or
conventional procurement options. However due to its
hypothetical nature of valuation throughout the life cycle of
the project, the merit of PSC is still a debated issue. Much
work still needs to be done in all the areas such as to reduce
the gap in the valuation of projects by understanding the risks
in the project, closing the gap between hypothetical
assumption of vfm and to assess how close the value of vfm
can be with real value of the project. The public sector
comparator should be used with other similar tools to provide
better results. This is due to the fact that some of the factors
which are used for value for money comparison are more
qualitative than quantitative for which data is used based on
certain assumptions.
Merit of PSC as a tool for value for money: As per U.K. Audit
Commission report (2003 p. 37) the PSC has lost the confidence
of many people, and risks being seen more as a hoop to jump
through on the way to government funding than a valuable
exercise that can help ensure better VFM.
Value for money test is sometimes problematic. In particular,
it is difficult to factor in the cost of things going wrong over
the total life of the project. More generally, the public sector
comparator is necessarily hypothetical, so its credibility is
difficult to test.
As per report from Public Accounts Committee Publications
(UK):
The use of public sector comparators has been the subject of
considerable debate about their reliability, accuracy and
relevance in the contexts in which they have come to be used.
They have observed many cases where the public sector
comparator has been incorrectly used as a pass or fail test. In
these cases the desire to show that the PFI deal is "cheaper"
than the public sector comparator has led to manipulation of
A thorough review is required by policymakers, researchers

and academicians as to how best PSC can be utilized for
infrastructure development evaluating the various options with
34
guaranteed outcomes. Further research is also required to

understand PSC as a tool whether it needs improvement and
what best can be done to modify its methodology to improve
its efficiency in determining accurate values of project with
less information asymmetry.
[5].
[6].
[7].
[8].
It is expected that the Public Sector Comparator would develop

as a useful and effective tool in the decision making process
for choosing partners in infrastructure project and will be handy
for Policy makers and planners in future and surely it will
safeguard the larger Public interest.
Akhil Damodaran (b. 1986) is currently an

Assistant Professor (Senior Scale) College of
Management and Economic Studies,
University of Petroleum and Energy Studies,
Dehradun. Received MBA (Technology
management) majoring in strategy and finance
from Indian Institute of Technology, New
Delhi in 2014. He has experience in IT service
industry in diverse disciplines ranging from
service operation, ISO-27K auditing, and six
sigma project management. He holds a bachelor
of engineering in Electronics and Instrumentation from Rajeev Gandhi
Technical University, Bhopal.
VI. REFERENCES
[1].
[2].
[3].
[4].
Public, finance and management of public private partnership

edited by AkintolaAkintoye and Matthias Beck
www.treasury.wa.gov.au
http://www.tehelka.com/psus-need-more-autonomy-freedomfrom-bureaucratic-controlpm/
http://www.treasury.wa.gov.au/cms/uploadedFiles/_Treasury/
Infrastructure_Strategy/ppps_public_sector_ comparators.
pdf?n=9348
http://www.eib.org/epec/g2g/i-project-identification/12/124/
index.htm
The Value for Money Analysis:A Guide for More Effective
PSC and PPP Evaluation: by Dawn Bidne, Amber Kirby,
Lucombo J. Luvela, Benjamin Shattuck, Sean Standley, and
Stephen Welker
http://www.unescap.org/resources/guidebook-public-privatepartnership-infrastructure
http://www.ncppp.org/wp-content/uploads/2013/03/PS051012ValueForMoney-paper.pdf
35
Variation of the Capacitance of Supercapacitors

with Current and Frequency
Usman Sammani Sani1 and Ibrahim Haruna Shanono2
Bayero University, Kano, P.M.B. 3011, Nigeria
1
usmanssani@live.com, 2ihshanono.ele@buk.edu.ng
charge/discharge testing [4], [5]. In this work, impedance
spectroscopy and galvanostatic charge/discharge cycling were
employed to see the frequency as well current behaviour of
supercapacitors.
Abstract -- In this work, the charge and discharge cycle of a

supercapacitor was examined from which it was observed that
the capacitance of the supercapacitor changes while charging
and discharging. So also, the capacitance was observed to vary
with frequency when frequency response analysis was performed
on it.
II. METHODOLOGY
Step I: Galvanostatic Charge/ Discharge cycling was performed
on a capacitor, using an Arbin BT2000 multi channel battery
testing instrument along with its Arbin MITS Pro Software.
The galvanostatic current was set at 50mA. The results below
were obtained from the experiment.
Keywords: Supercapacitors, Energy-Density, Charge-Discharge

Testing.
I. INTRODUCTION
AS A result of the rapid development in technology and the
availability of portable devices, researches on energy storage
devices are under process in order to obtain storage devices
that have higher energy density as well as higher power
density. Batteries have higher energy density but with lower
power density. In the case of supercapacitors, the reverse is
the case [1]. Thus present researches are on how to improve
the energy density of supercapacitors so that it can replace
batteries in some applications [2]. The Ragone Plot below shows
the various forms of energy storage devices, their energy
density and power density.
The charts above were obtained by exporting the results of

the experiment to Microsoft Excel and subsequently plotting
the charts. Amongst the columns from the excel file there is
(1)
The current of a capacitor is [6]
(2)
Thus,
(3)
The value of C was then computed from equation (3) and
plotted against the testing time.
Step 2: Impedance spectroscopy was performed on another
supercapacitor using a VERSASTAT 3 device for a frequency
range of 10 mHz to 10 KHz. The plot of capacitance was
obtained.
III. DISCUSSION OF RESULTS
The results from the galvanostatic charge/ discharge showed
how the current and voltage in a capacitor are. When one of
them rose, the other one also rises and vice versa as shown in
figure 2. The charge energy also depended on them as shown
in figure 3. The capacitance of the supercapacitor was observed
to also change during the charging and discharging periods. It
increased while charging and decreased while discharging.
This is not in conformity with equation 3 in which the
capacitance is considered to be constant.
Figure1: Ragone plot of energy storage devices [3].
In order to improve the energy density of supercapacitors,

various materials have been developed and some are still in
the process. The storage capability of these new materials can
only be examined by experimentation. Such experiments could
either be cyclic voltammetry, impedance spectroscopy or
36
VARIATION OF THE CAPACITANCE OF SUPERCAPACITORS
Figure 2. Plot of current and voltage vs testing time.
Figure 3. Plot of Charging Energy vs Testing time(s).
Figure 4. Plot of Capacitance vs Testing time(s).
37
Figure 5. Plot showing the variation of capacitance with frequency.
So also the result from impedance spectroscopy showed how

the capacitance varied with frequency. This implies that the
capacitance value is not constant but it varies with any of the
parameters voltage, current and frequency. As such
manufacturers of such kinds of capacitors now include plots
in their datasheets so that users can be able to make proper
choices.
[5].
[6].
Usman Sammani Sani graduated from

Bayero University, Kano in 2008, where he
obtained a bachelor degree of electrical
engineering. He then furthered his studies, in
which he obtained an MSc in Electronic
Communications and Computer Engineering
from The University of Nottingham Malaysia
Campus in 2011.
Usman is presently a lecturer in the
Department of Electrical Engineering, Bayero
University Kano. His research interests include
digital communications, digital circuits design and testing of fabricated
electronic components.
IV. CONCLUSION
In this paper it has been shown that current, voltage and
frequency affect the value of the capacitance of a
supercapacitor. In order for users of such products to make
proper choices, manufacturers of supercapacitors include more
information in their datasheets regarding this issue.
V. REFERENCES
[1].
[2].
[3].
[4].
U. S. Sani, I. H. Shanono, An Equivalent Circuit of Carbon

Electrode Supercapacitors, Proc. 2014 Nigeria Engineering
Conference, pp. 631-639.
P.K. Rajan, A. Sekar, Linear Circuit Analysis, in W.K. Chen(ed),
Lingling Du, Study on Supercapacitor Equivalent Circuit

Model for Power Electronics Applications, Proc. 2009 2nd
International Conference on Power Electronics and Intelligent
Transportation System, 2009, pp. 51-54.
Xiaolai Liu & Jin Li, Study on the Electrode Materials of
Electrochemical Capacitor, International Journal of Chemistry,
Vol. 3, No. 2, June 2011, pp.198-200.
Patrik Johansson, Bjrn Andersson, Comparison of Simulation
Programs for Supercapacitor Modelling: Model Creation and
Verification, unpublished thesis, Chalmers University of
Technology, 2008, p. 3.
U. S. Sani, I. H. Shanono, A Study on Carbon Electrode
Supercapacitors, International Journal of Engineering Research
and Technology, Vol. 2, Issue 6, June 2013, pp. 2957-2964.
Ibrahim Haruna Shanono received his

B.Eng and MSc. degree from Bayero University
Kano and Nottingham University in 2008 and
2012 respectively. He is currently working with
the Department of Electrical Engineering,
Bayero University Kano, Nigeria. His research
interests are in the areas of Renewable Energy,
Power Electronics and Automatic Control
systems.
38
AN EFFICIENT CARRY SELECT ADDER

Rishabh Rai1 and Rajni Parashar2
Department of Electronics & Communication Engineering, Ajay Kumar Garg Engineering College, Ghaziabad 201 009 UP, India.
1
rishabh.rahul001@gmail.com , 22401.rajni@gmail.com
microprocessors, one can perform millions of instructions per

second. So, the speed of operation is most important factor to
be considered while designing multipliers. Even in servers and
personal computers (PC), power dissipation is an important
design parameter. In todays era, the designs of area-efficient
and power-efficient high-speed logic systems are one of the
crucial areas of research in VLSI design. In digital adders and
circuit design, the speed of addition is limited by the time
required by carry to propagate through the adder. The present
scenario signifies the field where computations need to be
performed using low-power and an area-efficient circuit that
must operate at greater speed which is achievable with lesser
delay; efficient adder implementation becomes a most important
factor as well as the necessity. The example of thedevices like
mobile, laptops etc. require more battery usage. So, one who
working in the field of VLSI has to optimize these three
parameters in a design. These controlling parameters are very
difficult to achieve so depending on demand or application
some compromise between constraints has to be made.
Abstract -- Adders are one of the widely used digital components

in digital integrated circuit design. Generally,addition is the
basic operation which isused in almost all calculation and
computational systems. So, the efficient implementation and
design of arithmetic units requires the binary adder structures
to be implemented efficiently. A ripple carry adder has smaller
area in design while it has less speed. A carry look ahead adder is
faster in operation as its area requirements are high. Carry
select adders lie in between the spectrum. Design of highly
efficient Carry Select Adder using Square-root technique
suggests many opportunities for increasing the speed and
reducing the area of any data processor. Generally, we have the
carry select adder (CSLA), the fastest adder which is used in
many data-processing processors to perform fast arithmetic
operations. If we study the structure of CSLA, we come to know
that there is scope in area reduction and delay. In this study, a
carry select adder for the computational process is explained
which has some modules to be implemented and synthesized
using HDL coding. Carry select adder (CSLA) is one of the fastest
adder in comparison to all other adders. This review undergoes
very simple and efficient gate-level modification to reduce the
area and delay of the CSLA. Based on this modification, 8-bit,
16-bit, 32-bit and 64-bit Square-Root CSLA (SQRT CSLA)
architecture have been developed having comparison with the
regular SQRT CSLA architecture. The proposed circuit design
has reduced area and delay as compared with the regular SQRT
CSLA.
Ripple Carry Adders have most compact design but they are
having slow speed of operation. Whereas, the Carry Look
Ahead Adder has fast speed but it consumes more area. Carry
Select Adder solves both the problem as generated by that of
the Ripple Carry Adder and Carry Look Ahead Adder. A CarrySelect Adder can be structured by using a single Ripple-Carry
Adder and an add-one circuit rather than using the dual RippleCarry Adders.Based on the area, delay and power consumption
requirements, several adder structures have been proposed. A
multiplexer-based add-one circuit is proposed to reduce the
area with less speed penalty. This acts as the sum for each bit
position in an adder which is generated serially only after the
previous bit position has been summed and a carry is
propagated to the next position.
Keywords: CSLA, RCA, BEC
I. INTRODUCTION
IN recent years, the increasing demand for high-speed
arithmetic units in micro-processors, image processing units
and DSP chips has paved the path for development of highspeed adders as addition is an important operation in almost
every arithmetic unit, and it too acts as the general building
block for synthesis of all other arithmetic computations. If we
have to increase the portability of systems as well as the
reliability of the battery, area and power are the critical aspects
which are generally considered. In digital adders and
corresponding circuit designs, the speed of addition has
somerestrictions by the time required to propagate a carry
through the adder. The designs of area and high-speed data
path logic systems arethe most important areas of research&
study in VLSI system design. In electronic system and
applications adders are mostly used. As we know that in
The CSLA is used in many calculation systems to avoid the

problem of carry propagation delay by independently
generating multiple carries and then select a carry to generate
the sum. However, the regular or conventional CSLA is not
area efficient as it uses multiple pairs of Ripple Carry Adders
(RCA) to generate partial sum and carry by taking carry input
Cin=0 and Cin=1,where the final sum and carry are selected by
the multiplexers.
39
attain low power dissipation and high speed. Ripple Carry Adder
consists of cascaded N single bit full adders. Output carry,
i.e. Cout of previous adder becomes the input carry of next full
adder. Therefore, the carry of this adder traverses longest path
called worst case delay path through N stages. Figure 1 shows
the block diagram of Ripple Carry Adder (RCA). Now, as the
value of N increases, delay of adder increases linearly. So,
RCA has the slowest speed amongst all adders because of
large propagationdelay, but it occupies the least area. Now
CSLA provides a way to get around this linear dependency to
anticipate all possible values of input carry i.e. 0 and 1 and
evaluate the result in advance. Once the original value of carry
is known, result can be selected using the multiplexer stage.
So,the conventional CSLA makes use of dual RCAs to
producethe partial sum and carry by taking the input carry Cin
= 0 and Cin = 1, then the final sum and carry are selected by
multiplexers. Figure 2 shows the 16-bit SQRT. CSLA.The Sqrt.
CSLA is area consuming due to the use of dual RCAs.
The basic idea of this study is to use Binary to Excess-1

Converter (BEC) rather than that of RCA withCin=1 in the regular
CSLA to obtain lower area and delay. As, in BEC logic,lesser
number of logic gates are used and hence the circuit is
optimized, the modified CSLA is more efficient than that of the
regular CSLA.
II. LITERATURE SURVEY
.Much of the research efforts of the past years in the area of
digital electronics have been directed towards increasing the
speed of digital system.There are different types of fast adders
used in processors such as Ripple Carry Adder (RCA),Carry
Look Ahead Adder (CLA)and Carry Select Adder. Ripple carry
adder generates the compact design but their computation
time is high. Carry Look Ahead Adder basically provides fast
result but it results in increase in area. Carry Select Adder
provides a better approach between RCA and Carry Look Ahead
Adder. Ripple Carry Adder generates worst case delay, because
it comprises ofN single bit full adders. Each adder gives the
sum and carry. The carry generated by the previous full adder
is given as the input to the next adder. The carry is transferred
through every stage and produces a delay which is called as a
worst case delay. In Ripple Carry Adder, as value of N increases,
delay also increases.
Recently the requirement of portability and the moderate
improvement in battery performance indicates that the power
dissipation is one of the most critical design parameter. The
three most widely accepted parameters to measure the quality
of a circuit or to compare various circuit styles are area, delay
and power dissipation. Portability imposes a strict restriction
on power dissipation while still requires high computational
speed. Hence, in recent VLSI Systems, the power-delay product
becomes the most important aspect of performance. The
reduction of the power dissipation and the improvement of
speed require optimizations at all levels of the design procedure.
Figure 1. Four-Bit Ripple Carry Adder.
SQRT CSLA has been chosen for comparison with modified

design using BEC as it has more balanced delay, less area and
low power [4]. Regular SQRT CSLA also uses dual RCAs. In
order to reduce the delay, area and power, the design is modified
by using BEC instead of RCA with Cin=1. Therefore, the
modified SQRT CSLA occupies less area, delay and low power.
Further, the parameters like delay, area and power can be
reduced.
Ripple Carry Adder has the lowest speed among the fast adders.
The CSLA is used to find out all possible values of input carry
i.e. 0 and 1 and calculates the result in advance. The result is
passed through a select line by the multiplexer. The CSLA
generallyuses dual RCAs to generate partial sum and carry by
considering Cin=0 and Cin=1 then the final sum and carry is
selected by using multiplier. In regular CSLA area consumed is
more due to the use of dual RCAs. The basic idea of this study
is to use Binary to excess-1 converter (BEC) rather than that of
RCA with Cin=1 to reduce the area and power. The advantage
of BEC is that it requires less number of logic gates than that of
the N bit full adders. To reduce the delay, N bit ripple carry
adders are replaced with N+1 bit BEC.So, the newly modified
Sqrt. CSLA is area consuming than regular CSLA.
Figure 2. Sixteen-Bit Regular SQRT CSLA.
Since, most digital circuitry comprises of simple and/or complex

gates; we study the best way to implement adders in order to
A conventional carry select adder is a configuration of dual

RCA in which one RCA generates sum and carry output by
40
inevitable carry propagation chain. For example, the delay of a

fast CPA for converting the final carry-saved number to its
twos complement form in a Wallace tree multiplier is typically
25% to 35% of the total multiplier delay [10].Power is an
important factor for which power optimization refers to number
of Joules dissipated over a certain amount of time whereas
energy is the measure of the total number of Joules dissipated
by a circuit. In digital CMOS[2] design, the well-known powerdelay product is commonly used to assess the merits of designs.
In a sense, this can be shown as power delay = (energy/
delay) delay = energy, which implies delay is irrelevant.Bedrij
(1971) [7] suggested that the propagation delay can be reduced
by independently generating multiple carries and using these
carries to generate simultaneously by generating sums.
Ramkumar and Kannan [1] proposed that a BEC to reduce the
maximum delay of carry propagation in final stage of Carry
Save Adder. Chang and Hsiao [10] proposed the implementation
of low power and area efficient carry select adder using DLatch instead of BEC. Kim and Kim [11] proposed BEC
technique which is a simple and gate level efficient modification
to significantly reduce the area and power of SQRT CSLA. The
proposed model uses BEC instead of RCA which is used in
regular CSLA.
assuming Cin = 0and the other RCA produce carry and sum and
sum assuming Cin= 1 [3]. This conventional carry select adder
has less carry propagation delay than conventional RCA adder
but increases the complexity due to dual RCA structure. A
carry select adder generating carry of block with carry in as1
from the block with carry in as 0 was proposed by Tyagi.[13] in
1990. Later in 1998, Chang and Hsiao[10] proposed a carry
select adder consisting of single ripple carry adder. This was a
real start in the carry select adder history.In 2001 a further
modified carry select adder with increased delay but reduced
area and power was givenby Kim and Kim [11]. Here the RCA
section with Cin = 1 was replaced using an add one circuit
using multiplexer (MUX). Later in the year 2005 a further modified
carry select adder which reduces the area and power
consumption was proposed by Amelifard, Fallah and
Pedram[12]. It reduces the gap between carry select adder and
ripple carry adder.
Later a Sqrt. CSLA was proposed which helps in implementing
large bit width adders with less delay. In this system the CSLAs
with increasing bit widths are cascaded with each other. It
helps in minimizingthe overall adder delay. A BEC based CSLA
was further proposed byRamkumar and Kittur[1] which had
fewer resources than conventional CSLA but with more delay.
A CBL (common Boolean logic) based CSLA[10] was also
proposed which requires less logic resources but CPD(carry
propagation delay) was similar to that of RCA. A CBL based
Sqrt. CSLA [11] was also proposed but the design requires
more logic resource and delay than BEC based Sqrt. CSLA.
III. RIPPLE CARRY ADDER (RCA)

Ripple carry adder is logical circuit using multiple full adders
to add N-bit numbers. Each full adder provides the input as
Cin, which is the Coutof the previous adder. This kind of adder is
known as a ripple carry adder, since each carry bit ripples to
the next full adder. The sum and the output carry of any stage
cannot be produced until the carry input occurs which causes
a time delay in the addition process. The carry propagation
delay for each full adder as shown in Figure 3 is a time from the
application of the input carries until the output carry occurs.
Now a further modification of CSLA called Area-Delay-Power

Efficient Carry Select Adder [1] was proposed. Here the carry
generation is faster but the area consumption is not much
reduced. The carry of the system is calculated before the sum
generation.Also the carry generation unit was also replaced
using an optimized logic.Thus the system has lesser carry
output delay than all other system. Though the carry generation
is faster, the area and power consumption are not much
reduced. So a further modification with a reduction in area and
power consumption, thus obtaining an optimized area-delay
and power carry efficient carry select adder is proposed here.
Figure 3. Four-Bit Ripple Carry Adder.
The Ripple Carry Adder [1, 2] is used for evaluating addition of

two N-bit numbers. For addition of N-bit numbers, N full adders
are needed. From the second full adder carry input of every full
adder is the carry output of its previous full adder. This kind of
adder is stated as Ripple Carry Adder because of rippling of
carry to next full adder is governed here. The general structure
of full adder is shown in Figure4.
The CSLA[1] is used in many computational systems to remove

the problem of carry propagation delay by independently
generating multiple carries and then select a carry to generate
the sum [3]. However, the CSLA is not area efficient because it
uses multiple pairs of Ripple Carry Adders (RCA) to generate
partial sum and carry by considering carry input Cin=0 and
Cin=1, then the final sum and carry are selected by the
multiplexers.The SQRT CSLA has been chosen for comparison
with the proposed design as it has a more balanced delay, and
requires lower power and area [6].In particular; CarryPropagation Adder (CPA) is frequently part of the critical delay
path limiting the overall system performance due to the
Figure 4. Basic Diagram of Full Adder.
41
SQRT Carry Select Adder (CSLA). Normally the CSLA is

designed with the dual Ripple Carry Adders with the carry
being 1 and 0.Here, rather than that of having dual ripple
carry we are having only single ripple carry adder while the
binary to excess one converter is connected instead of RCA
with Carry 1.[8]-[12].
Using the equation Cin = Gn-1+Pn-1Cn-1, conventional Ripple

Carry Adder is structured. Here each stage uses the output of
the previous stage. The delay is directly proportional to the
number of bits as shown in Figure 5. This adder undertakes
the minimum number of logic gates and the worst case delay is
generally more. It is suggested that the adder has a regular
layout and uses 5 logic gates per bit. For an n bit adder total
number of logic gates used is 5n and the delay is 2n+2 logic
gates. For area calculation only two input AND, OR and XOR
gates are considered.
The block diagram of conventional Carry Select Adder (CSLA)

[1] is shown in Figure 7. CSLA uses RCA to generate sum and
carry values using initial carry as 0 and 1 respectively, before
the actually carry arrives in. Upper RCA is given with carry
initial value as logic 0 while lower RCA is given with carry
initial value as logic 1. Multiplexer selects the result of carry
0 path if the previous carry is logic 0 or the result of carry
1 path if the previous carry is logic 1 i.e. actual carry is used
to select the sum and carry using a multiplexer.
Figure 5. Block Diagram of Four-Bit Ripple Carry Adder.
Half Adders are used to add two one bit binary numbers. It is
also possible to structure a logical circuit using multiple full
adders to add N-bit binary numbers. Each full adder inputs
aCin, which is the Cout of the previous adder. This kind of adder
is a ripple carry adder, since each carry bit ripples to the
next full adder. The first (and only the first) full adder may be
replaced by a half adder.
Figure 7. Block Diagram of Conventional CSLA.
IV. CARRY SELECT ADDER

Carry Select Adder is a fast adder which is used in digital
communication and Memory Architectures as shown in Figure
6. The Carry of one ripple carry adder will be 0 and another
will be 1.Here the output sum and carry is identified by the 2
to 1 multiplexers. The control signal of the multiplexer can be
represented by carry (Cin).
Each RCA pair in CSLA can compute in parallel the value of

sum before the previous stage carry comes. Thus, the critical
path of an N bit adder is reduced. Delay in CSLA is much lesser
than RCA because the critical path in case of conventional
adder is N-bit carry propagation path and one sum generating
stage while in case of CSLA, the critical path is (N/L)-bit carry
propagation path and L stage multiplexer with one sum
generating stage in the N- bit CSLA, where L is number of
stages in CSLA as shown in Figure 7. Since L is much less
thanN and multiplexer delay is less than the delay in full adder,
hence the delay in the CSLA is much less than that in the RCA
but there exists copy of hardware in each stage which leads to
an increase in the amount of power consumption and cost.
V. BASIC ADDER BLOCK
The adder block using a Ripple carry adder, BEC and Mux is
described in this section. In this, we explain the delay & area
using the theoretical approach and show how the delay and
area effect the total implementation. The AND, OR, and Inverter
(AOI) implementation of an XOR gate is shown in Figure 8.
The delay and area evaluation methodology considers all gates
to be made up of AND, OR, and Inverter, each having delay of
1 unit and area of 1 unit. We can then add up the number of
gates in the longest path of a logic block that contributes to
Figure 6. Basic Carry Select Adder Circuit.
The Carry Select Adders are divided into two types: Uniform
sized adders and variable sized adders. When thebit length is
equally divided it is stated as an uniform sized adder. It is also
called as the linear Carry Select Adder. In variable sized adders
the bit lengths are generally unequally divided. It is also called
42
of this task is to use BEC instead of the RCA with Cin=1 in order
to reduce the area and increase the speed of operation in the
regular CSLA to obtain modified CSLA. To replace the n-bit
RCA, n+1 bit BEC logic is required as shown in Figure 10.
Figure 11 shows the BEC using carry out.
the maximum delay. The area evaluation is calculated by

counting the total number of AOI gates required for each logic
block. Based on this method, the blocks of 2:1 mux, Half Adder
(HA), and Full Adder (FA) are evaluated and listed in Table 1.
Figure 10. Four-Bit Binary to Excess-1 Converter.

Figure 8. Delay and Area Evaluation of XOR.
The Boolean expressions of the 4-bit BEC is given as (note the

functional symbols! NOT, & AND, ^XOR).
X0 =! B0
X1 = B0^B1
X2 = B2^ (B0 & B1)
X3 = B3^ (B0 & B1 & B2)
Table 1DELAY AND AREA EVALUATION OF CSLA
The next figure i.e. Figure 9 illustrates how the basic function
of the CSLA is obtained by using the 4-bit BEC together with
the Mux. One input of the 8:4 mux gets as it input (B3, B2, B1,
and B0) and another input of the mux is the BEC output. This
produces the two possible partial results in parallel and the
mux is used to select either the BEC output or the direct inputs
according to the control or carry signal Cin.
Figure 11. Four-Bit Binary to Excess-1 Converter Using Carry Out.
The respective block level implementation includes the Ripple

Carry adder, BEC unit as well as the sum and the carry selection
unit, which are accordingly connected to each other with the
marked bits such as 0 as well as the carry in and carry out. The
respective order of n signifies the level of bits such as 1, 2etc.
as shown in the Figure 12. Here, at the output section, the
sums as well as the carry units are accordingly generated.The
truth table of 4-bit binary to excess - 1 logic is respectively
shown in the Table 2.
Figure 9. Four-Bit BEC with 8:4 MUX.
VI. BINARY TO EXCESS-1 CONVERTER (BEC)

The general aspect is to use Binary to Excess-1 Converter
(BEC) in the regular CSLA to attain lower area and increased
speed of operation. This logic is replaced in RCA with Cin= 1.
This logic can be applied for different bits which are used in
the modified design. The main benefit of this BEC logic arrives
from the fact that it uses lesser number of logic gates than the
n-bit Full Adder (FA) structure. As stated above the main idea
Figure 12. Connection of RCA, BEC and Sum & Carry Block
43

TABLE 2TRUTH TABLE OF FOUR-BIT BEC
Binary Logic
B0 B1 B2 B3
Excess-1 Logic
E0 E1 E2 E3
0000
0001
0001
0010
0010
0011
0011
0100
0100
0101
0101
0110
0110
0111
0111
1000
Figure 13. Sixteen-Bit Regular SQRT CSLA.
1000
1001
1001
1010
1010
1011
1011
1100
1100
1101
1101
1110
Basically, the proposed structure of the modified CSLA will

contain the design specification of the NAND Gate instead of
the NOR Gate. As a result, the number of gates will be reduced
and hence the parameters such as area. The delay of the
proposed circuit will also be getting affected.The comparison
of the RCA &CSLA in terms of the delay as well size parameters
denoted in the form of n is shown in table 3.
1110
1111
1111
0000
Table 3--COMPARISON TABLE OF RCA & CSLA
VII. MODERN APPROACH

This architecture is similar to regular 16-bit SQRT CSLA, the
only change is that, we replace RCA with Cin=1 among the two
available RCAs in a group with a BEC. This BEC has a feature
that it can perform the similar operation as that of the replaced
RCA with Cin=1. Figure 13 shows the modified block diagram
of 16-bit SQRT CSLA. The number of bits required for BEC
logic is 1 bit more than that of the RCA bits. The modified
block diagram [1] is also divided into various groups of variable
sizes of bits with each group having the ripple carry adders,
BEC and corresponding mux. Thus, the sum1 and carry 1
(output from mux) are depending on mux and resultscomputed
by RCA and BEC respectively. The sum2 depends on carry 1
and mux. For the remaining parts the arrival time of mux
selection input is always greater than the arrival time of data
inputs from the BECs.
VIII. CONCLUSION
Power, delay and area are the main performance parameters of
CSLA and the reduction of these parameters is the challenging
issue of todays VLSI research. Many methods and techniques
have been proposed to design fast, compact and less power
consuming CSLA. But as we can analyze from the recent
method proposed that there is a trade-off between area
consumption and delay of CSLA. Therefore, there is a scope
to make CSLA more delay and area efficient by optimizing the
circuit. The overall improvement in Modified CSLA shows
better results in terms of area power and delay. Hence, proposed
modified CSLA is being used for power and area efficient
devices.
IX. ACKNOWLEDGEMENT
Authors thank Ajay Kumar Garg Engineering College for
providing facilities.
III. DISCUSSION OF RESULTS

The results from the galvanostatic charge/ discharge showed
how the current and voltage in a capacitor are. When one of
them rose, the other one also rises and vice versa as shown in
figure 2. The charge energy also depended on them as shown
in figure 3. The capacitance of the supercapacitor was observed
to also change during the charging and discharging periods. It
increased while charging and decreased while discharging.
This is not in conformity with equation 3 in which the
capacitance is considered to be constant.
X. REFERENCES
[1].
[2].
44
B. Ramkumar and H.M. Kittur, 2012, Low-power and areaefficient carry-select adder, IEEE Transactions on Very Large
Scale Integration (VLSI) System. vol. 20, no. 2, pp. 371375.
J. Kinniment, 1996, An evaluation of asynchronous addition,
IEEE transaction on Very Large Scale Integration (VLSI)
Systems, vol.4, pp.137-140.

[3].
[4].
[5].
[6].
[7].
[8].
[9].
[10].
[11].
[12].
[13].
Hiroyuki Morinaka, Hiroshi Makino, YasunobuNakase,

Hiroaki Suzuki and Koichiro Mashiko,1995 A 64bit Carry
Look-ahead CMOS Adder using Modified Carry Select,
Proceeding of IEEE on Custom Integrated Circuits Conference,
pp.585-588.
J. M. Rabaey, 2002, Digital Integrated CircuitsA Design
Perspective,Upper Saddle River, NJ: Prentice-Hall, a book
for general study.
June Wang, Zhongde Wang, G.A. Jullien and W.C. Miller, 1994,
Area time analysis of Carry Look ahead Adders using enhanced
multiple output domino logic, IEEE International Symposium
on Circuits and systems, vol.4, pp.59-62.
Nhon T. Quach and Michael J. Flynn, 1992, High speed
addition in CMOS, IEEE transaction on Computers, Vol.41,
pp.1612-1615.
O.J. Bedrij, 1962, Carry-Select Adder, IRE transactions on
Electronics Computers, Vol.EC-11, pp. 340-346.
Richard P. Brent and H. T. Kung, 1982, A Regular Layout for
Parallel Adders, IEEE transactions on Computers, Vol.c-31,
pp.260-264.
Sarabdeep Singh, Dilip Kumar, 2011, Design of Area and
Power Efficient Modified Carry Select Adder, International
Journal of Computer Applications, Vol. 33, No. 3, pp.14-18.
T.-Y.Chang and M.-J.Hsiao, 1998, CSLA Electronics letters,
Vol.34, pp.2101-2103.
Y. Kim and L.-S. Kim, 2001, 64-bit carry-select adder with
Reduced area, Electron. Letters. Vol. 37, No. 10, pp.614
615.
Amelifard B, Fallah F and Pedram M, 2005, Closing the Gap
between Carry Select Adder and Ripple Carry Adder: A New
Class of Low-Power High-Performance Adders, Quality of
Electronic Design, IEEE Sixth International Symposium, pp.
148-152.
Akhilesh Tyagi, 1990. A Reduced-Area Scheme for CarrySelect Adders, IEEE Transactions on Computers, Volume 42,
No. 10, pp. 1163-1170.
Rishabh Rai is pursuing M.Tech (2013-15)

from Ajay Kumar Garg Engineering
College,Ghaziabad (affiliated to Uttar Pradesh
Technical University,Lucknow) in VLSI Design.
His areas of interest are Digital System
Design,Embedded System Design, & Low Power
VLSI Design.He completed his B.Techfrom
Vishveshwarya Institute of Engineering &
Technology, Gr.Noida (affiliated to Uttar
Pradesh Technical University, Lucknow) in
Electronics
and
Telecommunication
Engineering with Honours in the year 2013. During his career he has
been appreciated and certified for securing Rank in Top Five Positions
in the respective branch for consecutive four years during B.Tech and
Amul Vidya Bhushan Award for his performance in AISSCE-2009,at the
District Level. During his graduation, he has also been awarded with the
Best Paper Presentation in the IEEE Sponsored National Conference,
ETEAT-2013. He is the student member of IEEE.
Rajni Parashar is currently working as an
Assistant Professor in Department of
Electronics and Communication Engineering
with Ajay Kumar Garg Engineering
College,Ghaziabad (affiliated to Uttar Pradesh
Technical University, Lucknow). She
completed her B.Tech from Punjab Technical
University, Jalandhar and M.Tech from
Kurukshetra University, Kurukshetra. She has
four years of teaching experience and six
months of industrial experience to her credit.
Her research interests are in the areas of Digital and Analog Circuit
Design & Microelectronics.
45

Department of Electronics and Communication Engineering, Ajay Kumar Garg Engineering College,
27 Km stone, NH-24, Adhyatmik Nagar, Ghaziabad 201009 UP India
1
me.pronnatisingh@gmail.com, 2kamlakanttripathi@gmail.com
As we know it is very costly to buy real network devices and
tools required to establish or deploy a complete system for
building any simple or complex communication network
systems. In addition, it is difficult to deploy tested systems
without having the real equipment such as computers,
switches, routers, oscilloscopes and also the different software
required for the systems. To overcome these problems many
researchers and software engineers developed different
network simulation tools that can help in designing the
complete network system. This work compares the performance
and tradeoffs of popular digital modulation systems. The work
presents combination of high-level modelling environments
and automatic code generation with hardware/software codesign which elaborates the simulation to synthesis of digital
modulation schemes using the MATLAB program and its
implementation in a XILINXs Spartan-III kit using system
generator. The specific digital design from analysis over
creating the simulation model to mapping the modulator to the
FPGA is discussed. Test benches created for both traditional
and block diagram oriented Simulink system generator
combination approaches. The results indicate that synthesis
on FPGA hardware can be generated automatically reducing
the design time from days to minutes.
Abstract -- This paper presents an overview of the Implementation

of Digital Modulator BASK, BFSK, and BPSK on FPGA and
presents a new approach for its implementation. The simulation
of a Digital Modulator using Matlab environment and a tool
from Xilinx is used for FPGA design as well as the implementation
of the modulator on FPGA using a Spartan 3E starter kit. The
modulator algorithm has been implemented on FPGA using the
VHDL language on Xilinx ISE 12.3. Based on recent development
of software tools and FPGA circuits, the technique used in this
paper improves a solution for implementing the Digital
Modulator on FPGA. The modulated signal obtained from
simulations h a s b e e n compared with the signal obtained after
implementation. The modulator design has been simulated and
theirs performances has evaluated by measurements.
Keywords: BASK, BFSK, BPSK, Digital Modulator,FPGA.
I. INTRODUCTION
FIELD-PROGRAMMABLE gate arrays (FPGAs) are
semiconductor devices containing programmable logic
elements (LEs) and a hierarchy of reconfigurable interconnects
to realize any complex combinational or sequential logic
functions. Hardware implemented in an FPGA can be
reconfigured by programming the logic elements and
interconnections for specific applications, even after the
product has been installed in the field. Todays FPGAs consist
of configurable embedded static random-access memories
(SRAMs), high speed transceivers, high-speed input/output
(I/O) elements, network interfaces, and even hard-embedded
processors
II. THEORY OF DIGITAL MODULATIONS

BASK Modulation : The BASK is obtained by the alteration
of the amplitude of the carrier wave. It has a very poor
bandwidth efficiency. The basic merit of this technique is its
simple implementations, but is highly prone to noise and the
performance is well established only in the linear region, which
does not make it a viable digital modulation technique for
wireless or mobile application in the present scenario.
A literature survey shows that FPGAs are widely used in

different applications, such as motor controllers, neural network
fuzzy-logic controllers etc. On the other hand implementation
of digital modulation and demodulation using FPGAs has
received considerable attention. Signal-processing systems
such as software-defined radios (SDRs) can receive various
kinds of modulated signals via software programming using
digital signal processors (DSPs).
In a BASK (binary amplitude-shift keying) modulation process,

the amplitude of the sinusoidal carrier signal is changed
according to the message level (0 or1"), while keeping the
frequency and phase constant.
A BASK signal can be expressed as:
Since digital modulation is less complex, more secure, and more

efficient in long-distance transmission and noise detection/
correction than its analog counterpart, it has an important place
in modern communications.
S(t ) = m(t ) A sin (2 fc t + 0) , 0 < t < T

where m(t)=0 or 1 (the binary message), T is the bit duration,
46
FPGA IMPLEMENTATION OF DIGITAL MODULATORS
and A and fc, and 0 are the amplitude and frequency of the
sinusoidal carrier signal.
Figure 4. The modulating-signal (message) and

BFSK signal waveforms.
BPSK Modulation: In a BPSK (binary phase-shift keying)

modulation process, the phase of the sinusoidal carrier signal
is changed according to the message level (0 or 1) while
keeping the amplitude and frequency constant.
Figure 1. A block diagram of BASK modulation.
A BPSK signal can be expressed as:

SBPSK(t) = A sin [2 fct + m(t) ] ,
0<t<T
where m(t)=0 or 1 (the binary message), T is the bit duration

,and A and fc are the amplitude and frequency of the sinusoidal
carrier signal.
Figure 2. The modulating-signal (message) and BASK signal
waveforms.
BFSK Modulation: In a BFSK (binary frequency-shift keying)

modulation process, the frequency of the sinusoidal carrier
signal is changed according to the message level (0 or 1)
while keeping the amplitude and phase constant.
A BFSK signal can be expressed as:
SBFSK(t ) = A sin{2 [fc + m(t) fm] t + 0 }, 0 < t < T
where m(t ) = 0 or m(t ) = 1 (the binary message), T is the bit
duration, and A, fc, and 0 are the amplitude, frequency, and
phase of the sinusoidal carrier signal.
Figure 5. A block diagram of BPSK modulation.
Figure 3. A block diagram of BFSK modulation.
Figure 6. The modulating-signal (message) and

BPSK signal waveform.
47
III. MATLAB MODEL FOR DIGITAL MODULATORS

Before solving a problem, one needs to first define and
formulate the problem one intends to solve. Implementation of
Digital modulator through Matlab creates the virtual
environment to reduce the hardware cost and area overheads
by increasing the frequency as a major parameter. To implement
the above design we have used MATLAB to simulate and
XILINX Spartan III to implement design on the FPGA Kit.
Implementation of Digital Modulator on FPGA: The setup
Lab measurement used for realizing the Digital Modulator is
illustrated in figure 7 below. Some of the resources used are
Spartan 3E starter kit board. Spartan 3E FPGA starter kit is
development platform based on Spartan 3E FPGA, it provides
a development platform for Embedded processing application.
The Spartan 3E family of FPGAs is designed to be well suited
for wide range of electronics applications.
Figure 8. BASK Result.
BFSK Simulation Result: For generating the modulating signal

of BASK the value of first carrier frequency is 1000 Hz, second
carrier frequency is 2000 Hz and Modulating Frequency is 125
Hz. Simulation result of BFSK modulator shown in figure 9.
Figure 7. Spartan Kit.
IV. SIMULATION AND EXPERIMENTAL RESULT

Prior to the FPGA hardware implementation, the designed
BASK, BFSK, and BPSK digital modulators were verified
through simulations using the Matlab/Simulink environment.
There are two parameters used in designing of Digital
Modulator i.e. carrier frequency and modulating frequency.
Figure 9. BFSK Result.
BPSK Simulation Result: For generating the modulating signal

of BASK the value of carrier frequency is 1000 Hz and
Modulating Frequency is 250 Hz. Simulation result of BPSK
modulator shown in figure 10.
BASK Simulation Result: For generating the modulating signal

of BASK the value of carrier frequency is 1000 Hz and
Modulating frequency is 500 Hz. Simulation result of BASK
modulator shown in figure 8.
48
FPGA IMPLEMENTATION OF DIGITAL MODULATORS
[4]
[5]
[6]
[7]
Figure 10. BPSK Result.
V. CONCLUSION
The choice of digital modulation scheme significantly affects
the characteristics and resulting physical realization of
communication system. This work describes the Concepts and
simulations to Methods of hardware implementations of all
the main digital modulation schemes used such as BASK,
BFSK, and BPSK. It elaborates the simulation to synthesis of
digital modulation schemes using the MATLAB/Simulink
program and its implementation in a XILINXs Spartan- III kit.
Dr. K.K. Tripathi possesses in-depth

experience of 48 years in field of technical
education, in teaching, guiding research and
administration. He was founder Professor and
HoD of Electronics Engineering Department
of H.B.T.I. Kanpur. After completing 36 years
of distinguished service at H.B.T.I. Kanpur, he
joined premier technical institutions AKGEC,
RKGIT, IMS and HRIT, Ghaziabad.
VII. REFERENCES
[2]
[3]
K. Li, X. Lu, W. Zhang, and F. Wang, Design and

Implementation of Digital Modulator Based on Improved
Direct Digital Synthesizer Technology and DSP Builder, Proc.
IEEE 5th International Conference on Wireless
Communications, Networking and Mobile Computing (WiCom
09), September 24-26, 2009, pp. 1-5.
F. M. Demir, U. Kafadar, S. Dikmese, and H. Dincer, FPGA
Based Implementation of Communication Modulation, Proc.
IEEE 15th Signal Processing and Communications
Applications (SIU 07), June 11-13, 2007, pp. 1-4.
Ahamed and F. A. Scarpino, An Educational Digital
Communications Project Using FPGAs to Implement a BPSK
Detector, IEEE Transactions on Education, Vol. 48, No. 1,
2005, pp. 191-197.
Pronnati obtained B. Tech in Electronics and
communication engineering from Institute Of
Technology and Management, Gorakhpur
(U.P.) . Currently, pursuing M.Tech (VLSI
Design) in the Department of Electronics and
Communication Engineering at Ajay Kumar
Garg Engineering College, Ghaziabad.
Her areas of interest are Embedded Systems
and SOC. After completing M. Tech she plans
to pursue career in teaching.
VI. ACKNOWLEDGEMENT
Authors are grateful to HoD, ECE, AKGEC for providing the
Deptt Lab facilities to undertake the research work.
[1]
Cybernetics and Technical Informatics (ICCC- CONTI 10),

May 27-29, 2010, pp. 327-332.
M. Rice, C. Dick, and F. Harris, Maximum Likelihood Carrier
Phase Synchronization in FPGA-Based Software Defined
Radios, Proc. IEEE International Conference on Acoustics,
Speech and Signal Processing (ICASSP 01), May 7-11, 2001,
pp.889-892.
C. Erdogan, I. Myderrizi, and S. Minaei FPGA

Implementation of BASK-BFSK-BPSK Digital Modulators
IEEE Antennas and Propagation Magazine, Vol. 54, No. 2,
April 2012.
F. Amaya-Fernandez and J. Velasco-Medina, Design of
Baseband Processor for Software Radio Using FPGAs, Proc.
IEEE International Conference SOC (SOCC 08), September
17-20, 2008, pp. 315-318.
S. O. Popescu, G. Budura, and A. S. Gontean, Review of
PSK and QAM Digital Modulation Techniques on FPGA,
Proc. IEEE International Conference on Computational
He is a voracious reader. His area of research

interest includes Embedded Systems, Wireless Optical Communication.
His current area of interest is I.C.T. specially Adhoc and Sensor network.
Presently he is Professor Emeritus in ECE Deptt. of A.K.G.E.C.,
Ghaziabad.
49
AKGEC INTERNATIONAL JOURNAL OF TECHNOLOGY, Vol. 6, No.1
Design and Implementation of Inset feed Square Patch

Micro Strip Antenna Array for WLAN Application
Using Dielectric Substrate
Priya Upadhyay1, Dr. Ranjit Singh2 FIETE and Arundhati Tiwari3
Department of Electronics and Communication Engineering, HI-TECH Engineering College,
27 Km stone, NH-24, Ghaziabad 201009 UP India
2
Department of Electronics and Communication Engineering, Ajay Kumar Garg Engineering College,
27 Km stone, NH-24, Adhyatmik Nagar , Ghaziabad 201009 UP India
1,3
Abstract -- A Square patch Micro strip antenna array using inset

feed for Wireless Local Area Network (WLAN) and worldwide
interoperability S-band frequency is presented. The proposed
antenna is fabricated on dielectric substrate with dielectric
constant 4.2 and thickness of 1.5 mm. The key feature of this
substrate is that it can withstand high temperature. The return
loss is about -16dB at the operating frequency of 2.45 GHz with
50 input impedance. The basic parameters of the proposed
antenna such as Return Loss, VSWR, Radiation Pattern and 3D
Polar Plots are simulated using An soft HFSS. Simulation results
of antenna parameters of single patch antenna array are analyzed
and presented.
Figure 1. Microstrip antenna configuration.
Specifications for the design of the structure are as follows
Number of elements : 4
Input impedance : 50
Resonance frequency : 2.4GHz
VSWR: 1 1.4.
Keywords: Radiation Pattern, VSWR, 3D Polar Plot, Inset feed.
I. INTRODUCTION
ANTENNA is one of the important elements of a wireless
communications system. Wireless technology provides less
expensive alternative and a flexible way for communication.
Communication plays a vital role in the worldwide society nowa-days and the communication systems are rapidly switching
from wired to wireless. Accordingly, antenna design has
become one of the most active fields in the communication
studies.
These specifications were chosen to design a lightweight and

compact Micro strip Array Antenna at S-band for Man packs
Wireless Communication. The design of the whole structure is
performed in the following steps.
i)
ii)
iii)
One common type of antenna is the Micro strip patch antenna

[1]. A good antenna design can improve overall performance
of the system. In the present paper, a 4 element high gain
parallel micro strip antenna array using Inset feeding network
at S-band is presented. The Inset-fed Micro strip antenna
provides a method of impedance control with a planar feed
configuration. This antenna features advantages of the printed
circuit technology. These advantages make Micro strip
antennas popular in wireless communication applications such
as satellite communication, radar, medical applications, etc.
Micro strip antenna in its simplest configuration is shown in
Fig1. It consists of a radiating patch on one side of dielectric
substrate (rd10) and a ground plane on other side.
To design a single Micro strip patch antenna

To design the power divider to feed the Antenna
To design the complete array.
This paper provides a way to choose the effective feeding

technique between the transmission lines and Micro strip patch
antenna. By comparing the antenna parameters the best feeding
technique will be selected for the design of Micro strip patch
array antenna as Inset feed technique.
II. MICRO STRIP PATCH ANTENNA ARRAY
A patch antenna is a narrowband, wide-beam antenna fabricated
by etching the antenna element pattern in metal trace bonded
to an insulating dielectric substrate, such as a printed circuit
board, with a continuous metal layer bonded to the opposite
side of the substrate which forms a ground plane. Micro strip
50
MICRO STRIP ANTENNA ARRAY FOR WLAN
patch is generally made of conducting material such as copper

or gold and can take any possible shape. Common micro strip
antenna shapes are square, rectangular, circular and elliptical,
but any continuous shape is possible. Some patch antennas
do not use a dielectric substrate and instead use a metal patch
mounted above a ground plane using dielectric spacers. The
resulting structure is less rugged but has a wider bandwidth.
Because such antennas have a very low profile, are
mechanically rugged and can be shaped to conform to the
curving skin of a vehicle, they are often mounted on the exterior
of aircraft and spacecraft, or are incorporated into mobile radio
communications devices [11].
III. FEEDING OF ANTENNA ARRAY

Feed line is used to excite to radiate by direct or indirect contact.
The radiating patch and the feed lines are usually photo etched
on the dielectric substrate. Micro strip antenna consists of
very small conducting patch built on a ground plane separated
by dielectric substrate. The conducting patch, theoretically,
can be designed of any shape like square, triangular, circular,
or rectangular. However rectangular and circular configurations
are the most commonly used. Micro strip antenna has a
drawback of small bandwidth and low gain. The bandwidth
can be increased by cutting slots and stacking configuration
and Gain can be increased by using different patch elements in
an array to achieve optimum radiation characteristics.
Figure 3. Proposed parallel microstrip patch antenna array.
There are many different techniques of feeding. Four most

common techniques are coaxial probe feed, micro strip line,
aperture coupling and proximity coupling. The parallel or
corporate feed has a single input port and multiple feed lines in
parallel with the output port [11]. Each of these feed lines is
terminated at an individual radiating element. Existing methods
to feed Micro strip arrays can be categorized into parallel and
series feed.
The series feed usually consists of a continuous transmission
line from which small proportion of energy are progressively
coupled into the individual element disposed along the line.
The series feed constitutes a traveling wave array if the feed
line is terminated in a matched load. For a uniform aperture
distribution, the power is equally split at each junction.
However different power divider ratios can be chosen to
generate a tapered distribution across the array. A corporate
feed is most widely used parallel feed configuration. In this
paper the corporate feed with inset feed is discussed for the
antenna array design.
Figure 2. Structure of Microstrip patch antenna.
Consider a Micro strip patch antenna illustrated in figure 2.

Micro strip patch antennae radiate primarily because of the
fringing fields between the patch edge and the ground plane.
For a rectangular patch, the length L of the patch usually
satisfies
IV. DESIGN CONSIDERATION OF 4X1 MICROSTRIP

PATCH ANTENNA ARRAY
In this paper a 4X1 array of individual Micro strip patch antenna
is designed to achieve higher gain, better bandwidth, and input
impedance of the antenna array. A single antenna has limited
bandwidth. The square patch is chosen because it simplifies
analysis and performance prediction. The antenna is designed
to operate at 2.4 GHz with input impedance of 50 , using FR4
(r = 4.2) and height (h = 1.6mm).
0.33330 < L < 0.5 0,

where 0 is the free-space wavelength (0= 0.125 mm). The
patch is selected to be very thin such that t << 0 (where t is
the thickness of patch).
The height h of the dielectric substrate is usually 0.0030 < h <
0.050 . The dielectric constant of the substrate is typically in
the range 1.2 < r < 12.
The design starts with the simple rectangular Micro strip

antenna with inset feed. Then, the Micro strip antenna is
51
VI. SIMULATION RESULTS

The simulated results were obtained by considering an
equivalent circuit of square micro strip patch antenna using
HFSS for calculating various parameters. The designed
parameters are utilized on HFSS software. The software used
to model and simulate the Parallel Micro strip patch antennae
is High Frequency Simulation Software HFSS version 11.1 [14].
simulated using the An soft HFSS Software. After simulation,

the M,icro strip antenna is fabricated using FR4, with dielectric
constant (r = 4.2) and height of 1.6 mm. Finally the Micro strip
antenna performance is measured using the network analyzer
and the measured values are compared with the simulated
values.
A single element design is shown in figure 3. The dimension of
the patch is 29 mm x 29 mm with inset feed at 8 mm. The width
of the transmission line is 3mm as shown in figure 3.
Radiation Pattern radiates electromagnetic wave in one

direction. Two types of radiation pattern are measured like EPlane radiation pattern and H-Plane radiation pattern. E-Plane
radiation pattern has circular and Omni directional radiation
pattern that means it has a perfect circle. Gain is improved for
the frequency range 2.4 GHz by using the inset feed patch
antenna. Gain is increased when multiple of antennas are used
in form of arrays. Here in this paper 4X1 elements are combined
together in form of arrays to improve the Gain and Bandwidth
of the antenna array [15].
V. DESIGN EQUATIONS
For an efficient radiation, the practical width of the patch can
be calculated by using the following.
W = 1/(2ro o)z/(r+1)
W = 29mm
Length of the antenna (L)
The radiation patterns at the center frequency 2.4GHz, for Sband is plotted as shown in Fig 4.
L = 0.49X0.123/ 4.2
L = 29mm
Free space wavelength (0)
0= C/F
0 = 0.125 mm
Effective Dielectric Constant (re)
= 4.18 mm
Guide wavelength (g)
= 0 /eff
= 6.1 mm
nret
Micro strip Length of the Antenna (ML)

= Rr x50
= 157.5 mm
For 50 , L = 16.994 mm W= 3.063mm, For 70.7 ,
L = 17.426mm, W = 1.623 mm
Figure 4. Radiation Pattern.
VSWR
The value of voltage standing wave ratio (VSWR) should be
in the range between 1 and 2. The acceptable VSWR is 1.5.
Figure 5 shows below that the value of VSWR is close to the
ideal value of 1 and 2:1 VSWR Bandwidth = 0.89796 with the
measurements that are provided as shown in figure 5.
52
MICRO STRIP ANTENNA ARRAY FOR WLAN
Figure 7. Return Loss.
Figure 5. VSWR plot.
VII. CONCLUSION
This paper presents the design and performance analysis of
Micro strip Phased Array Antenna for WLAN Application.
Physical patch dimensions were calculated in HFSS. Antenna
simulator software was used to evaluate performance of the
patch. The selected patches were arranged in planner array
form for WLAN application. 4 patch elements were selected to
achieve high gain and good efficiency. This proposed antenna
model is found to be cost effective, features high efficiency for
applications in 2.45GHz frequency range. The optimum design
parameters were used to achieve the compact dimensions and
high radiation efficiency. It provides a gain of 16.31 dBi, 95.6
percent efficiency and VSWR < 2 is achieved over the complete
frequency band with linear polarization of antenna in the desired
part of the beam.
3D Polar Plots
The antenna should not have the side lobes and back lobes
ideally. We cannot remove them completely but we can minimize
them. Micro strip antennas can provide directivity in the range
of 14 dB as shown in figure 6.
VIII. ACKNOWLEDGMENT
The authors acknowledge Ajay Kumar Garg Engineering
College, Ghaziabad for providing inspiring and propitious
academic ecosystem and facilities.
IV. REFERENCES
[1]
[2]
Figure 6. 3D polar plot.
[3]
Return Loss
The S11 parameter for the proposed antenna was calculated
and the simulated return loss results are shown in Figure below.
The value of return loss is -16 dB in this proposed antenna.
The achieved return loss value is small enough and frequency
is very closed enough to the specified frequency band for 2.45
GHz WLAN applications. Return loss as shown in Fig: 7.
[4]
[5]
[6]
53
James and P.S. Hall (Eds), Handbook of Micro strip Antenna,

Peter Peregrinus, London, UK, 1989.
J. C. Maxwell, A Treatise on Electricity and Magnetism, 3rd
ed., vol. 2. Oxford: Clarendon, 1892, pp.6873.
R. Garg, P. Bartia, I. Bahl, et al., Micro strip Antenna Design
Handbook, 2001, pp 1 68, 253 316.
M. Young, The Technical Writers Handbook, Mill Valley, CA:
University Science, 1989.
Kashwan, R. Kumar, T. Gunasegaram et al., Design and
Characterization of Pin Fed Micro strip Patch Antennae, IEEE
proceedings of FSKD, 2011.
N. Kanniyappan, Dr. R. Indra Gandhi, Design and Analysis of
Micro strip Patch Antenna Feeding Techniques, Proc. IEEE
International Conference on Computational Intelligence and
Computing Research, 2011

[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16].
Mehmet ABBAK, Micro strip Patch Antenna Array for Range

Extension of RFID Applications, Faculty of Engineering and
Natural Science, Sabanci University 34956, Istanbul, Turkey.
D. Orban and G.J.K. Moernaut, The Basics of Patch Antennas,
IEEE Antennas and Wireless Propagat. Lett. Vol. 1, 2002, pp
56-59.
M. T. I. Huque, et al., Design and Simulation of a Low-cost
and High Gain Micro strip Patch Antenna Arrays for the Xband Applications, Proc. International Conference on Network
Communication and Computer ICNCC 2011, New Delhi, India.
A. Balanis, Antenna Theory analysis and design, Micro strip
Antenna, Chapter 14, pp.720-784.
C. A. Balanis, Antenna Engineering, 2nd ed., Willey, 1982.
D. M. Pozar, Micro strip Antennas, Proc. IEEE, Vol.80, No.1,
January 1992, pp. 79-81.
http://www.antennatheory.com/arrays/main.php
HFSS user manual version 11.1 and ANSYS Software License
Agreement.
http://www.antennatheory.com/definitions/vswr.php
M. A. Matin and A. I. Sayeed, A Design Rule for Inset-fed
Rectangular Micro strip Patch Antenna, Proc. International
Conference on WSEAS transactions on communications, ISSN:
1109-2742 Bangladesh, Volume 9, Issue 1, March 21-23, 2011.
Dr Ranjit Singh obtained B.Tech, M.Tech.

and Ph.D degrees all from Indian Institute of
Technology, Kanpur in 1969, 1971 and 1976
respectively. He specialized in the area of
Electronic communication circuits and devices.
Published large number of technical papers in
IETE journals in addition to in-depth
technology-reviews covering emerging trends
in Communications and information
technology.
Since Sept 2008, he taught at Ajay Kumar Garg
Engineering College where, he served as a Professor in the Department
of Electronics and Communication Engineering.
He is a voracious reader. He has abiding passion for teaching and research.
Currently guiding M. Tech and PhD scholars besides supervising B.Tech
projects. He is Life Fellow of the IETE and attended international
Technical conferences held in France, Singapore, USA, Hong Kong and
Nepal. Daily practices advanced Art-of-Living meditation.
Arundhati Tiwari obtained Bachelor of
technology degree from
UP Technical
University and Master of Technology degree
from Indian Institute of Technology, New
Delhi. She is currently teaching at Electronics
and Communications Engineering Department,
HiTech Engineering College Ghaziabad. Her
Research area is energy conversion and
communication.
Priya Upadhyay completed her higher

secondary examination with science stream in
2000. She received Diploma in Electronics
Engineering from Govt. Polytechnic
Ghaziabad in 2005.
She received the B-Tech Degree in Electronics
and communication engineering from ABES
Engineering College Ghaziabad in 2008 and
M-Tech Degree in Electronics and
communication engineering from AKGEC,
Ghaziabad in 2012. During 2008-2010, she
worked with IBM as a Technical Analyst. Currently working as Assistant
Professor (ECE Department) in HIET Engineering College, Ghaziabad.
Her research area is Antenna Arrays, Wireless communication and
optical fiber communications.
54
EXTRACTING MARK-HAUWINK-SAKURADA PARAMETERS

Aniruddh Singh1 and Mohammad Asad2
1
Department of Applied Science, Ajay Kumar Garg Engineering College, Ghaziabad 201009 UP, India
Department of Mechanical Engineering, Ajay Kumar Garg Engineering College, Ghaziabad 201009 UP, India
Abstract -- MarkHauwinkSakurada parameters are calculated

by measuring viscosity of solution of polymers of known molecular
weight. The molecular weight is generally determined by an
independent method like light scattering or gel permeation
chromatography. In this paper a new method of measurement of
these parameters is discussed which rely solely on viscosity data
and does not need the measurement of molecular mass as a
prerequisite.
Keywords: Mark-Hauwink-Sakurada Parameters, Permeation
Chromatography, Molecular Weight.
Figure 1. Fluid motion.
I. INTRODUCTION
MOLECULAR weight is an important parameter characterizing
a polymer sample. The molecular weight can be determined by
chemical or physical analysis which include functional group
analysis, by measurement of the colligative properties, light
scattering, ultracentrifugation or measurement of viscosity of
dilute solution. All methods except the last one are absolute.
The viscosity method is an indirect method but its value lies
in its simplicity and that it can be applicable to a large group of
polymer systems. All the physical methods require solubility
of the polymer and extrapolation to infinite dilution [1].
The force F acting at area at right angle to the diagram and

parallel to u is proportional to the area and the velocity
gradient.
F A(vel.gradient)
Or:
Where is a constant for the liquid and is called the coefficient

of viscosity.
The solution viscosity as a measure of polymer molecular

weight is recognized as early as 1930 by Staudinger. Solution
viscosity is the measure of size or extension in space of a
polymer molecule. Viscosity measurements are simple and they
are extremely useful in correlating molecular weights that they
have become a valuable tool for molecular characterization of
polymers.
When the determination of molecular weight is required another

related quantity called the intrinsic viscosity is brought into
picture. The intrinsic viscosity is a quantity which is
independent of concentration of the solution but is the function
of the solvent used. The intrinsic viscosity is defined as:
II. THEORY
When adjacent layers of a fluid move with relative velocity,
forces known as viscous forces come into play to reduce their
relative motion. When we consider a fluid whose upper layer
is moving with a velocity u in a fixed direction then a state will
be reached when the lower most layer is at rest and the
intermediate layers move with velocity less than u as shown in
Figure 1.
Where /o is the viscosity ratio and c is the concentration.

The MarkHouwink equation, also known as the Mark
HouwinkSakurada equation or the KuhnMarkHouwink
Sakurada equation gives a relation between intrinsic viscosity
[]and molecular weight M:
[]=KMa
55
properties. International Journal of Biological Macromolecules

2011; 48: 286-291)
From this equation the molecular weight of a polymer can be

determined from data on the intrinsic viscosity and vice versa.
The values of the MarkHouwink parameters, a and K, depend
on the particular polymer-solvent system. For solvents, a value
of a=0.5 is indicative of a theta solvent. A value of a=0.8 is
typical for good solvents.
III. CALCULATION
Ref [2], [3] and [4] were taken as a base for the following
calculations. Part of the data of the three references were taken
and values of the parameters were calculated by applying the
formulae developed in the appendix.
A) Measurement of a.
The data is taken from [2] where the Mark-Hauwink-Sakurada
parameters for Poly (Methyl Methacrylate) are evaluated.
Using the values of intrinsic viscosity of the solution at

different temperatures and the values of a from table 3 we
calculates the values of K from equation (14) of the appendix.
The experimental data is compared with that calculated from
equation (14) is presented in table 4.
The data is summarized in table 1.

TABLE 1 -- VALUES OF AVERAGE VALUES OF A AND
INTRINSIC VISCOSITY OF POLY(METHYL
METHACRYLATE) [2]
TABLE 4 -- COMPARISON OF EXPERIMENTAL

K WITH CALCULATED K.
IV. CONCLUSION
It has been shown that the new method of measuring the MarkHauwink parameters yields results close to the values obtained
by other methods. The method described in this paper has a
positive future in context of determining the molecular mass of
a given polymer which is important as a quality control in
various polymer industries.
Using equation (6) of the appendix one calculates a and and

the result is presented in table 2.
TABLE 2 -- COMPARISON OF EXPERIMENTAL VALUES OF
A WITH THOSE CALCULATED FROM EQUATION (6)
V. ACKNOWLEDGEMENTS
The authors thank Prof. P.K. Sharda, HOD Applied Science for
many fruitful discussions. The authors thank the facilities
provided by the chemistry lab of Ajay Kumar Garg Engineering
College, especially the Lab assistant Mr. Manoj Kumar.
VI. REFERENCES
B) Measurement of K
The data presented in ref[4] is used to verify equation (14) of
the appendix which is meant to calculate K. The table of ref [4]
which is used in the following calculation is reproduced here.
[1].
[2].
[3].
[4].
TABLE 3-- MARK-HOUWINK PARAMETERS

OBTAINED FOR PECTIN.
Data provided courtesy of Elsevier (Masuelli, M. Viscometric

study of pectin. Effect of temperature on the hydrodynamic
56
Textbook of Polymer Science: Fred W. Billmeyer

www.nist.gov/data/PDFfiles/jpcrd316.pdf
www.nist.gov/data/PDFfiles/jpcrd286.pdf
Mark-Houwink Parameters for Aqueous-Soluble Polymers and
Biopolymers at Various Temperatures.Martin Alberto
Masuelli, Journal of Polymer and Biopolymer Physics
Chemistry, 2014, Vol. 2, No. 2, pp. 37- 43. Available online at
http://pubs.sciepub.com/jpbpc/2/2/2
EXTRACTING MARK-HAUWINK-SAKURADA PARAMETERS
original and Masticated solution respectively. The Mark

Houwink equation for the mixture(Original +Masticated) will
read:
VII. APPENDIX
The derivation of important formulae which extract the Mark
Hauwink parameters from viscosity data alone:
Section a) The Mark Hauwink equation relates the intrinsic
viscosity of a polymer solution with its average molecular mass
through a set of parameters (a and K) which are dependent on
the nature of the polymer and the solvent. The Mark Hauwink
equation reads:
(3)
Dividing (1) by (2) we get:
[] = KMa
(4)
The quantity on the left hand side is called the intrinsic viscosity
and M on the right hand side is the average molecular mass of
the given sample of polymer. K and a are the Mark Hauwink
parameters.
And dividing (3) by (1) we get:

(5)
To derive the parameters a and K one takes the polymer solution

by dissolving a known mass of polymer sample in the given
solvent. The viscosity of the solution is measured at different
concentrations by the method described in the proposal. The
intrinsic viscosity is extracted from this data by taking the limit
to zero concentration. Let us call this as intrinsic viscosity
[1].
Taking the value of N2/N1 from (4) and substituting in (5)
(6)
[1] = KM1a
(6) becomes our governing equation to determine the parameter
a.
Now the solution is masticated for some given time so that the
polymer in the solution breaks down and its average molecular
mass reduces. Let the reduced average molecular mass be called
M2. The intrinsic viscosity of the masticated solution is also
extracted in the same way by experimenting on the new
solution. Let the new viscocity be called [2]. Then from the
Mark Hauwink equation:
Section b) To find K we determine the intrinsic viscosity of a

given sample at two nearby temperatures.
Let the two temperatures be T1 and T2 and the corresponding
viscosities be (T1) and (T2). Let us now differentiate the
Mark Houwink equation with respect to temperature. We get:
[2] = KM2a
The original solution is made in duplicate. Now the two
solutions (Original +Masticated) are mixed together. Let the
total mass of the polymer before dissolution be TM. Then the
average molecular mass of the polymer in the solution is TM
divided by the no. of polymer molecules. Thus:
(7)
Let the values of a and K at temperature T1 and T2 be a1, a2, K1
and K2 respectively.
Then from (7):
(1)
(8)
And
.
Since from the Mark Hauwink equation we get:

(2)
(9)
We can get K2-K1 from the above equation (8).
Where N1 and N2 are the no. of polymer molecules in the
57

Dr. Aniruddh Singh obtained PhD in
Theoretical Nuclear Physics from Jamia Millia
Islamia, New Delhi. He obtained BSc Hons in
Physics from Delhi University and MSc Physics
from IIT Kanpur. His PhD thesis is in the field
of Variational Monte Carlo methods as applied
to light nuclei and hypernuclei.
(10)
And so:
(11)
He has over seven years of teaching experience

and two years research experience in industry.
Substituting (11) for K2-K1 and and using Mark Houwink

equation for M viz:
Currently, he is an assistant professor with the Department of Applied

Sciences, Ajay Kumar Garg Engineering College, Ghaziabad.
(12)
Mohammad Asad (b. 13 Nov 1994) in

Varanasi. Passed High school ICSE board in the
year 2011 with 87% marks. Passed Intermediate
from CBSE board in PCM with 74%.
We get equation for K:
Pursuing B.Tech from Ajay Kumar Garg

Engineering College, Ghaziabad. Currently in
2nd year. Passed 1st year with 70.8% marks.
And:
(13)
Which gives on simplification :
(14)
Equation (14) becomes the master equation for determining K.
The viscosities are measured and from it, the as are calculated
in the manner described in previous section.
58
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Design of a Digital Clock Using Very High Speed IC Hardware Description Language
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Hybrid Method For Automatically Filling of the Chemical Liquid into Bottles Using PLC & SCADA
A. Chandrashekar, B.S. Ajaykumar and H.N. Reddappa
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Dr. Amit K. Jain
Public Sector Comparator: A Useful Decision Making Tool in Infrastructure
Akhil Damodaran
Variation of the Capacitance of Supercapacitors with Current and Frequency
Design and Implementation of Inset feed Square Patch Micro strip Antenna Array for WLAN .....
A Novel Method of Extracting Mark-Hauwink-Sakurada Parameters from Viscosity Data
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AKGEC

Design of a Digital Clock Using Very High Speed IC Hardware

Application of Queuing Model: With Special Reference to Construction

Hybrid Method For Automatically Filling of the Chemical Liquid

Friction Stir Welding: Tool Material and Geometry

Determination of Natural Frequency of a Turning Specimen

Circuit Architecture for Photon Counting Pixel Detector

Public Sector Comparator: A Useful Decision Making Tool in Infrastructure

Variation of the Capacitance of Supercapacitors with Current and Frequency

An Efficient Carry Select AdderA Review

FPGA Implementation of Digital Modulators

A Novel Method of Extracting Mark-Hauwink-Sakurada

Ajay Kumar Garg Engineering College

27th km Stone, Delhi-Hapur Bypass Road, PO Adhyatmic Nagar,

EDITORIAL ADVISORY BOARD

Prof. Kripa Shanker

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Former Vice Chancellor

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Department of Electrical Engineering

Prof. Suneet Tuli

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Prof. S.P. Singh

Prof. Vinod Kumar

Shri V.K. Gupta

Prof. Surinder Prasad

Prof. N.N. Kishore

Prof. N.S. Vyas

January - June 2015

AKGEC International Journal of Technology

Application of Queuing Model: With Special Reference to

Hybrid Method For Automatically Filling of the Chemical Liquid

Friction Stir Welding: Tool Material and Geometry

Determination of Natural Frequency of a Turning Specimen

Circuit Architecture for Photon Counting Pixel Detector

Public Sector Comparator: A Useful Decision Making

Variation of the Capacitance of Supercapacitors with

An Efficient Carry Select AdderA Review

FPGA Implementation of Digital Modulators

Dr. R.K. Agarwal

Design and Implementation of Inset feed Square Patch Micro

A Novel Method of Extracting Mark-Hauwink-Sakurada

Ajay Kumar Garg Engineering College

(ISO 9001 : 2008 Certified and Accredited by NBA)

27th Km Stone, Delhi-Hapur Bypass Road, PO Adhyatmic Nagar,

Copyright AKGEC International Journal of Technology

DESIGN OF A DIGITAL CLOCK

Design of a Digital Clock Using Very High Speed IC

clock and other components. The seconds count after each

Abstract -- Very High Speed IC Hardware Description Language

Five switches stop, settime, sethr, setmin and inct

Keywords: VHDL, Programmable Logic Devices, FPGA

The same principle is used to reset minutes using setmin.

The Clock: This is designed to display time in the format hr:

AKGEC INTERNATIONAL JOURNAL OF TECHNOLOGY, Vol. 6, No. 1

button has to be activated for it to be displayed on the seven

The top level consists of 7 segment display decoders for

The Date: This has a value of 0 to 31 which increments at the

Codes for interchanging between one display mode and the

signal from the various components and determine the

Tb_tplevel.vhd is a test bench file for the entire digital

Figure 1. Register Transfer Level of the digital clock.

DESIGN OF A DIGITAL CLOCK

The table below shows how the resources in the Spartan- 3