SMS Methodology

Naksha Technologies Inc
1313 North Milpitas Blvd #165.

Milpitas, CA 95035
SMS Methodology
Rev 2.8
Author: Narasimha N
Introduction
The Self Test And Repair (STAR) Memory System is an embedded memory system that has
redundant memories, fuse-box and a processor.
SMS allows the embedding of multiple megabits of SRAM into SOC (System-On-Chip) very
economically.
1) Processor will test of the memories and compute the repair information for the failed
memory. Also does the lots of other things like, diagnostic down load, fuse loading
during the power-on etc.
2) Fuse-box: is an array of fuses which can be blown (individual bits can be made 0 or 1) by
using the laser light on the wafer. This is used only if the hard (permanent) repair option
is used for the memories.
Laser fuses are metal links that can be blown by a laser after the wafer is processed.
Each foundry has its own exact layout rules and process for making laser fuses.
Non-Volatile Fuse which can be made zero or one permanently using the high voltage,
and is very easy for the hard repair. We are using the Laser Fuse only for the hard repair,
because Non-Volatile Fuse technology was not available for the implementation at that
time.
3) Redundant Memory is nothing but regular memory with one extra column
(I/O bit
Din and Q) and a register called a redundancy register. Extra column is used to replace
the regular column which has faulty memory cell. Which column of the memory needs to
be replaced is indicated by the content of redundancy register.
Following is a block diagram of SOC which uses the STAR Memory system.
Figure : 1 typical SOC with SMS.
SMS comes with IEEE P1500 interfaces for the self test and repair of the memories,
details of which is given in section 5.1.
Figure 2. A Typical multi SMS System
The integrated test and repair capability ensures higher yielding semiconductors, and
can potentially save millions of dollars in recovered silicon, substantially reduce test
costs, and enable faster time to volume.
Embedded Test and Repair (ET&R) can take place either in the factory during wafer
probe (hard repair) or in the field while the SOC is used in the end product (soft
repair)
Understanding the redundant Memories
Consider a simple memory (8x4) as an example to understand the concept.

Redundancy
Reg
R-0
Q3
Q2
Q1
Q0
Mem Data
0
0
000
001
Mem
Addr
C3-0
C2-0
C1-0
C0-0
C r-0
C3-1
C2-1
C1-1
C0-1
Cr-1
C3-2
C2-2
C1-2
C0-2
Cr-2
C3-3
C2-3
C1-3
C0-3
Cr-3
C3-4
C2-4
C1-4
C0-4
Cr-4
C3-5
C2-5
C1-5
C0-5
Cr-5
C3-6
C2-6
C1-6
C0-6
Cr-6
C3-7
C2-7
C1-7
C0-7
Cr-7
Column-C3
Column-C2
Column-C1
Column-C0
Column-Cr
010
011
A0
A1
A2
100
Addres101
Decoding
Logic 110
111
1
1
1
1
D3
D2
D1
D0
Figure 3: 8x4 Redundant Memory (Column redundancy)

[Its a just logical representation, not the real memory structure]
The memory has 8 words and each word is of 4 bits. (mem width is 4 and depth is 8).
R-1 R-2 R-3

0 1
0
Redundant memories which are used here have one extra column of memory cells
(Cr-0 to Cr-7 cells in this example) and a register called redundancy register (which is 4 bits
in this case.)
If any memory cell has fault during the manufacturing, then the whole column of memory
cells with the faulty cell will be replaced by the extra column of memory cells.
Assuming that cell C2-3 has failure then the column C2 will be replaced by extra
(redundant) column Cr.
The replacing of the columns is done by the redundancy register in the memory. In this case
this register is written with value 4b0100 so the 3rd column C2 is replaced by the redundant
column Cr.
So now we have two ways to write the redundancy register, which in turn repairs the memory.
1) Soft repair.
Soft repair is a temporary fix, the next time you reset the chip, and memories loose the
repair. So each time the chip is reset, STAR processor runs the BIST and analyzes the
failure and shifts the required values in to the redundancy register of the memory, and
faulty column will be replaced by the extra column and hence the memory is repaired.
2) Hard repair. (Find the faulty column and blow the fuses accordingly once during the
manufacturing phase, such a way that during each power-on, the content of the fuse-box
is loaded in to the redundancy register.)
STAR processor will find out the failed memory cell and its column by doing the bist
operation on the memories. The BIST operation can be triggered by writing the BISTPRODUCTION command in to the WIR register.
BIST operation is nothing but the sequence of write and reads to the memories based certain
algorithms, chosen during the SMS generation. Currently the default algorithms ( March ED
(15N + 2) for Single Port memories and March (32N + 4) for the Dual Port
memories. Details of these algorithms are given at the end in section 9) is used from
the SMS compiler.
At the end of the of the BIST operation, star processor comes up with status of memory pass
or fail, also if the memories are failed it provides the other information such as which
memory failed, what is the data bit and what address on which failure occurred etc.
SMS also provides the information whether the memory is repairable or not and scans out the
fuse repair information (which represent failed column).
Now we can fix the Memory manufacturing problem by using redundant column available in
that memory, if the scanned status is repairable. This can be achieved by writing appropriate
values in the redundancy register of the corresponding memory. (Provided that the
redundant memory cells itself have no faults).
Soft Repair and Hard repair
1) Soft repair: star processor will shift appropriate values in the redundancy registers of the
memory which is having the failure, once it done the bist operation. So in the case of soft
repair every time during the power-on BIST will run and the repair bits are loaded in the
redundancy register.
2) Hard Repair: BIST is done only once during the manufacturing phase and then fuses are
blown according to the repair status scan. Every time during chip power-on, content of
Fuse-Box will be loaded in to the redundancy register of the memories by STAR
processor.
SMS HARDWARE IMPLEMETATION (SMS Generation)
3.0 Envrinment setup and commands to launch the tool.

Set the following environment variables before to launch the Virage tool.
setenv CTMCHOME /vendors/virage_tsmc13/latest
alias ctmc $CTMCHOME/bin/ctmc
alias cover $CTMCHOME/bin/cover
setenv CTMCLIB /vendors/virage_tsmc13/virage_ship_naksha_26feb2003/complib
setenv VL_LICENSE_FILE /usr/local/flexlm/licenses/license.dat
Type ctmc on the command line, to launch the Vitage compiler for the SMS and memory
generation.
The version of the compiler used for the Viper, Cobra and Cougar is Rev: 3.4.4 (build
REL-3-4-4-2003-08-15)
3.1 Getting Started

11) Initiate Integrator (CTMC). For more details on using the Integrator, please refer to
Custom-Touch Memory Compiler Users Guide manual.
22) Click > File
33) Click > New
44) Click > Add
55) Select the foundry of interest
6) Select the process
17) Click Compiler: button and select your STAR memory compiler
28) Click > Revision
39) Click > OK
3.2 Specifying the STAR Memory configuration(s)

For the following discussion, please refer to Integrators Memory Generation GUI shown in
Figure 1.
11) Input the Number of Words
22) Input the Number of Bits (I/Os)
33) Choose a Column Mux option
44) Select the Number of Bits in Subword (if this feature is enabled)
55) Input the Frequency that the memory will run at
66) Input a memory instance name or accept the default
77) Click > Views and deselect the views not required
88) Click > OK.
99) Click > Apply
1010) If more STAR Memory instances from the same compiler are required, use the same
session to generate the other memory instances by adding more instances.
1111) When finished adding memory instances, close the STAR memory window by clicking on
Cancel button.
1212) If hard repair is required, then proceed to the Generating the Fusebox steps.
Figure 3-1: Integrators Memory Generation GUI
3.3 Specifying the fuse box

This section assumes you are still in the Integrator session from above. Specifying the fuse
box is similar to adding more instances with the exception that the instance is a fuse box. If
you are planning to use soft repair only, skip this section and go to the section Specifying the
STAR processor configuration.
For the following discussion, please refer to Integrators Fuse Box Generation GUI shown in
Figure 2.
11) Click > Add
22) Select the foundry (must be the same as used in the STAR Memory instance generation)
33) Select the process (must be the same as used in the STAR Memory instance generation)
44) Click Compiler: and choose the fuse box
55) Select the revision
66) Click > Ok: a window for fuse box generation will pop up
17) Click > Views button and deselect the views that are not required
28) Click > OK (in the Views window)
39) Click > OK (in the fuse box window)
Figure 3-2: Integrators Fuse box Generation GUI
3.4 Specifying the STAR processor configuration

For the following discussion, please refer to Integrators STAR Processor Generation GUI
shown in Figure 3.
11) Click > Add
22) Select the foundry (must be the same as used in the STAR Memory instance generation)
33) Select the process (must be the same as used in the STAR Memory instance generation)
44) Select the STAR processor
55) Select the appropriate revision
66) Under STAR Instances, if multiple numbers of the same memory configuration are
required, then specify the number in the Instances box .
17) The up arrows can be used to change the order in which the STAR Memories are tested.
28) After specifying the number of memory instances, click the Update button. This
updates the number of fuses.
39) In the STAR processor GUI, choose either soft repair, hard repair, or a combination of the
two.
410) Click > Views button and deselect the views that are not required
511) Click > OK when finished.
Figure 3-3: Integrators STAR processor generation GUI
3.5 Generating the STAR Memory System

Now you are ready to generate the STAR memories, fuse box, and the STAR processor.
11) In the Integrator GUI, choose Run either on the top left row of pull-downs or click the
Run button and Select All Instances
This will generate directories corresponding to your memories, fuse box, and processor
under ..../compout/views directory. The sms directory contains module definitions for the top
level SMS (STAR Memory System), along with STAR processor and the wrappers. A testbench is
also provided, which can be used for testing the generated SMS system. For the memory and fuse
box models, use their behavioral models under Best, Worst, or Typical directories.
Important Note: When memories are added or removed and/or if the number of instances is
changed, the processor must be edited. This edit entails clicking the update button in the
STAR processor GUI.
SMS integration
Now that you have generated the STAR Memory System, you can have the memories, the fuse
box and the processor placed anywhere within your design and connect them through your design
hierarchy. For the SMS, the IEEE P1500 standard is adopted in order to support system-on-chip
(SOC) testability. Furthermore, SMS also supports an easy handshake interface with external
logic, using the standard IEEE 1149.1 JTAG.
Top
C7
C1
C7 group Logic
sms_c1
SMS_C1_SMS
Synchronizer
clk to JTCK
JTAG
1149.1
Synchronizer
JTCK to clk
LOGIC VISION
BIST
ASSEMBLY
Cn
C5
C3
C2
C1 group Logic
Figure 4:
SMS integration in to the chip.
Compiler writes out the top level sms module (sms_c1_sms) which is the integration of
memories, memory wrappers, processor, fuse-box etc. At the port level of this module only
Memory signals and P1500 signals will be visible and remaining interconnections taken care by
the Virage tool.
NAKSHA COMMUNICATIONS, INC CONFIDENTIAL
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Mustang SMS-JTAG interface
SMS and Logic Visions Bist controller assembly are instantiated together with required
synchronizers is and some glue logic to manipulate the memory controls for the testability and
functionality. This module is kind of wrapper to the Virages SMS and Logic Visions bist
controller.
The sms_c1 is integrated at the group level, since all the memories are under the sms_c1
hierarchy, and any module which uses the memory need to have the memory signals brought to
the group level hierarchy.
Logic visions assembly logic is used for the BIST of RF memories (Register files) which consist
of register files and BIST collars and BIST controller from the vendor Logic Vision, for all the
register files (RF memories) in that particular group.
Virage didnt have BIST solution for the RF memories or we might have needed to buy another
license, instead we decided to use the existing BIST solution from the Logic Vision.
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3
3.1
JTAG-SMS Interface Details

IEEE P1500 (Standard for Embedded Core Test)
IEEE P1500 defines a serial and a parallel test access mechanism a rich instruction set for
testing
cores, i.e. reusable megacells, and SoC interconnect and features for core isolation and protection.
Block level Details of IEEE P1500 standard is shown below.

SMS has IEEE P1500 interface and by using this serial interface, all the SMS
operations can be performed such as running the bist operation, getting the diagnostic
data and fuse loading etc.
Figure 1 IEEE P1500 Interface Memory System
P1500 Standard signals are compatible to Tap controller signals as per the interface is
concerned, except that it has one extra signals called SelectWIR. This extra signal is
used is used to select either WIR or data registers of STAR processor.
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So JTAG can be easily used to interface with the P1500 interface as both are
compatible.
3.2
SMS(P1500) and JTAG connectivity

The p1500 Interface consists of an Instruction and Data Register. By loading the
appropriate instruction in the WIR instruction register and scanning out the
appropriate SMS data registers all the required operations such as BIST, Soft repair,
hard repair, Diagnostic etc. can be performed.
SMS has a set of output signals, which represent the current status (BISTErr, STR
Ready, Etc.) of the memory system. The status of the given SMS system can be
observed by capturing the status signals in to one of the JTAG data registers and by
shifting that register content out through the TDO pin.
JTDO
JTRSTL
JTCK
JTMS
JTDI
BYPASS
JTAG
IDCODE, BSR,
etc
WSO_p
WIR
tap_C1_enb_retention_q
C1_tap_etrtdo_d
C1_tap_rscout_q
RSCOUT
BistError[3:0]
CurrentError[3:0]
STR_Ready
SelectWIR
WSI
UpdateWR
CaptureWR
ShiftWR
BCLK
WRCK
WRSTN
BiraFail[3:0]
Clock Synchronizser
clk -> JTCK
Mux-Decode l
EnRet
VBistEn
C1_SelectWIR
Logic
tap_C1_enb_retention_q
...... Cn status
EnRet
C2 status
JTDI
tap_C1_update_dr_q
tap_C1_scan_en_q
JTCK
clk
JTRSTL
tap_C1_scan_capture_q
C1 status
Logic
BYPASS
Diagnostic Data
SMS
SERIAL_SF0
Expanded Repair Data
Compressed Repair Data
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CLK
C1_sp_1_ADR [6:0]
C1_sp_1_D [31:0]
C1_sp_1_ME
C1_sp_1_WE
C1_sp_1_OE
C1_sp_1_AWT
CONTROL[4:0] = 4'b0
PARALLEL_ENABLE = 1'b0
SMART_red = 1'b0
SMART=1'b0
BCLK
Functional Ram Ports
C1_sp_1_Q [31:0]
sms_rst
Memory Parameter
Figure 4 JTAG - SMS Interface
Interface for the JTAG and SMS (which has 4 memories) is shown in the Figure 4.
The details of the above mentioned SMS signals are described below. The SMS
consists of 4 instances of 16kx32 single port srams. The memory ports of only one
instance are shown in Figure.
3.3
Input Ports
Table 1 SMS Input Ports
Port Name
CLK
BCLK
EnRet
WSI
WRCK
sms_rst
SelectWIR
CaptureWR
ShiftWR
UpdateWR
WRSTN
CONTROL [4:0]
PARALLEL_ENABLE
SMART
SMART_red
3.4
Description
Normal mode clock input for SRAM.
Clock input for BIST.(same as the normal mode clock)
Enables Retention operation.
Wrapper Serial Input of IEEE P1500 interface.
Used for scan-in of serial instructions and data through the IEEE
P1500 interface.
Clock input of IEEE P1500 Interface.
Used to reset reconfiguration registers of all STAR memory
instances, memory parameters registers, Scheduling engine and
Smart engine.
Control signal of IEEE P1500 interface, used to select whether the
WIR or a Wrapper Data Register(WDR) is connected between WSI
and WSO.
Control signal of IEEE P1500 interface, used to capture data into
WIR or WDR depending on SelectWIR.
Control signal of IEEE P1500 interface, used to enable shift
operation.
Control signal of IEEE P1500 interface, used to update serially
loaded data into WIR or WDR depending on SelectWIR.
Control signal of IEEE P1500 interface, used to reset WIR and SMS.
(WIR resets asynchronously, SMS synchronously)
Input bus, used to parallel load of WIR.(tied to 0 since it is not used)
Input control signal, used to enable parallel access to WIR.(tied to 0
since not used)
Used to run the Smart Mode.(this feature is not used always tied to 0)
Used to run the Reduced Smart Mode. .(Planning to use)
Output Ports
Table 2 SMS Output Ports
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Output Port Names

RunRet
STR_Ready
WSO
WSO_p
BistError[3:0]
CurrentError[3:0]
BIRAFail[3:0]
Description
Indicates the starting point of retention.
Indicates completion of the BIST run. STR_Ready goes to logic low
once any of BIST instructions is loaded in WIR and stays low until
execution of that instruction is completed.
Wrapper Serial Output of IEEE P1500 interface.
Used for scan-out of serial instructions and data through the IEEE
P1500 interface.
Has the same functionality as the WSO pin, is used to keep JTAG
functionality effectiveness.
This bit indicates detection of faults (one or more) in result of BIST run
on 4 instances of memory respectively. Its value resets by applying
sms_rst or Update WIR operation.
Indicates fault detection of the memory instances (4 in this case) during
the test run.
Used in Diagnostic mode only.
This signal indicates that BIRA engine of the
'mg_star_sp_16kx32_mg_star_sp_16kx32_1' wrapper failed to cover
the occurred faults.
Running SMS Tests.
This part of the document explains how the sms is operated during a diagnostic mode.
The sequence of JTAG and SMS instructions and procedures which are involved are
described (in order) in the section below.
4.1
Load Opcode in to the SMS WIR Register

Load the instruction (JTAG_Prog_sms_DataReg) which will make the WIR Register
of the selected SMS as the active Data Register for the JTAG Interface.
The width of the WIR register is 6, instructions and their opcodes are given in the
below table.
STAR Processor Instruction Set
Details about the individual instruction is given in the section 10.
Opcode mnemonic
FUNCTIONAL (BYPASS**)
BIST_PRODUCTION
BIST_DIAGNOSTIC
BIRA_BISR_PF0
BIRA_BISR_PF1
EXT_BIRA_PF0
EXT_BIRA_PF1
EXT_BISR
Decimal value
0
1
2
3
4
5
6
7
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Binary value
00000
00001
00010
00011
00100
00101
00110
00111
SERIAL_SF1
LOAD_FUSE_PF0
LOAD_FUSE_PF1
LOAD_MEM_PARAM
MPREG_RESET
SET_FUSE_BOX_LOADED
RESET_FUSE_BOX_LOADED
FUSE_BOX_LOADING
SCHEDULE_LOADING
RESET_SCHEDULE
SERIAL_SF0
9
11
12
13
14
20
21
22
23
24
25
01001
01011
01100
01101
01110
10100
10101
10110
10111
11000
11001
Shift 6 bits of opcode (000010 BIST_DIAGNOSTIC) in to the WIR. Data will

be shifted from MSB to LSB in the register, so use following sequence
0,1,0,0,0,0 of values on the TDI. (opposite of loading the JTAG instruction).
After the data is shifted, there will be a update cycle, which actually updates the
WIR register.
As soon as WIR updates with instruction BIST_DIAGNOSTIC, SMS starts the
BIST operation in Diagnostics mode.
4.1.1 Observe the Status of a Diagnostic Run

To observe the status of the BIST (or any other operation) in diagnostic mode we
need to observe the current error signal or STR_Ready, BistError, BIRAFail etc,
and that can be done by using the following steps.
Load the VBistEn Data Register of JTAG Interface with appropriate value
corresponding to the required SMS Status Register .
Load the JTAG Interface with instruction JTAG_RUNVBIST.
At this point, SMS Status Register will be the active register for the TDO pin.
While the SMS Status Register is not being shifted out, the TDO representins
the ORed value of cur_error for all the enabled SMSs. In case of an error (i.e
TDO = 1), the error status can be captured using two methods.
4.1.2 Scanning out the SMS Status Register in the JTAG Interface
We can shift out the SMS Status Register of the JTAG Interface,
which is already in the active path of the TDO pin.
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The SMS Status Register in the Jtag Interface represents the

current state of the status signals between the selected SMS and the
Jtag Interface.
4.1.3 Scanning out the Diagnostic Data from the SMS

Shift out the Diagnostic data from the SMS using the following
procedure.
Load the JTAG_Prog_sms_DiagReg instruction in to the Jtag
Interface.
Once we load the JTAG_Prog_sms_DiagReg instruction, the
Diagnostic Register of the selected SMS will be the active data register
for the TDO pin.
Using above procedure, different SMS instructions can be executed and the
corresponding status can be scanned out.
4.1.4 VBIST pass/fail test sequence.

a) Loding the Jtag Instruction PROG_VBIST_EN_REG into Tap controller . Shift
the Data through TDI to program the VBist Enable Register to enable All SMS
. Format is as specified above .
b) Loding the Jtag Instruction PROG_SMS_DATA_REG . By doing this WIR
register will get selected between TDI and TDO .
c) Load WIR of corresponding SMS with BIST_PRODUCTION instruction
opcode and update . Since All the sms are enabled , all the WIR will get updated
with same value.
d) After instruction is loaded into the WIR, STR_Ready signal becomes logic low
and processor unit of STAR Processor executes appropriate test sequence.
Completion of executing of those tests is indicated with STR_Ready come up
logic high. If an error is detected in memory, BistError becomes logic high i.e.
appropriate status bit/pin and is set to logic high. Since we Enabled all the SMS ,
all the SMS will start simultaneously. But Each SRAM will be tested
sequentially under each SMS.
e) When all the SMS completes the test , we can unload the vbist test status from
each SMS . We need to unload the status from each SMS by enabling one SMS at
a time .
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f) Loding the Jtag Instruction PROG_VBIST_EN_REG . Shift the Data through

TDI to program the VBist Enable Register to enable only One SMS .
g) Loding the Jtag Instruction RUN_VBIST into Tap controller . By doing this
VBIST status register correspond to the Enabled SMS ( w.r.t VBist Enable
Register ) will get selected between TDI and TDO. SMS status information will
get scan-out through TDO .
h) The step (f) and (g) will get repeated for all the SMS .
4.1.5 VBIST Fuse repair signature test sequence.

a. Loding the Jtag Instruction PROG_VBIST_EN_REG . Shift the Data through
TDI to program the VBist Enable Register to enable All SMS .
b. Loding the Jtag Instruction PROG_SMS_DATA_REG . By doing this WIR
register will get selected between TDI and TDO .
c. Load WIR of corresponding SMS with EXT_BIRA_PF0 instruction opcode.
d. In this mode the BIST circuitry runs at speed and the results are collected by
BIRA engine. Once the STR_Ready signal goes to high, the compressed
repair information is ready to be read out by the external
device using the
P1500 interface
e. Checks whether the all the STR_ready signals goes high in the simulation or
wait that many bist cycle to complete the above instruction .
f.
Loding the Jtag Instruction PROG_VBIST_EN_REG . Shift the Data through

TDI to program the VBist Enable Register to enable only One SMS
g. Loding the Jtag Instruction RUN_VBIST into Tap controller . By doing this
VBIST status register correspond to the Enabled SMS ( w.r.t VBist Enable
Register ) will get selected between TDI and TDO. SMS status information
(pass/fail and repairable/non-repairable ) will get scan-out through TDO .
h. Loding the Jtag Instruction PROG_SMS_DIAG_REG . By doing this WIRselect
signal will go low and DATA register ( compressed Repir data information of all
the SRAM will be selected out of the many DATA registers since WIR carry the
instruction EXT_BIRA_PF0 ) will get selected between WSI and WSO ,
ultimately between TDI and TDO . SMS configuration repair information will
get scan-out through TDO .
i.
The step (f) through (h) will get repeated for all the SMS
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5
5.1
Clocks and Resets

Clocks
SMS has three input clocks.

1) BCLK
2) CLK
3) WRCLK
5.2 BCLK
This clock is used by the SMS to control the test and repair operations.
Requirement of the BCLK is that, it should be same as the memory clock. So BCLK is
connected to the core clock clk.
5.3 CLK
This is connected to the memory clock. If memory is dual-port then there will be two
such clocks called CLKA and CLKB.
In the Mustang CLK, CLKA and CLKB of the SMS are connected to the core clock
clk.
5.4 WRCK
SMS uses this clock for the P1500 interface, by which we can load the instructions in to
the WIR, and scan out the SMS data registers for the repair and diagnostic data.
WRCK is must for the proper operation of the SMS, even when it was not using the
P1500 interface and it should be at least 7 times slower than the BCLK. But during the
normal operation of the Mustang, JTCK is shut-off.
Requirements:
1) WRCK should be active during the power-up to load the content of the fusebox in
the reconfiguration registers of the rams.
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2) WRCK should be connected to the JTCK, when Jtag is interfacing with the SMS
through P1500 interface.
3) JTCK will be shut-off during the normal operation of the mustang on the board.
Requirements 1 and 3 are conflicting; this can be resolved by muxing the JTCK with the
VCXO_2.2MHz clock.
5.5
Generating the WRCK clock
The select to that mux is connected to the Jtag data register called VBistEn[3], after the
power-on reset, this register bit VBistEn[3] will be 0, and will select VCXO_2.2 clock.
On the tester when Jtag will interface with the SMS through P1500 interface, first Jtag
has to make this register bit VBistEn[3] to1 so that JTCK is connected to the WRCK.
Once WRCK is connected to JTCK data can be shifted in-out of the SMS through P1500
interface, hence SMS can be operated by the JTAG on the tester.
SMS
SMS
SMS
WRCK
VCXO_2.2MHz
JTCK
WRCK
TDI
VBistEN[2]
VBistEN[1]
VBistEN[0]
TDO
JTAG
Control
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RESETS
SMS has 2 resets WRSTN and sms_rst.

1) WRSTN: Resets asynchronously WIR register, and synchronously to some other
registers in the SMS. This is active low reset.
2) sms_rst: Resets reconfiguration registers and some other SMS registers
synchronously. This is active high reset.
For the SMS to reset properly, WRSTN and sms_rst should be active for at least 2
WRCK clocks and should be de-asserted w.r.t the core clock clk.
SMS when comes out of the reset, loads the content of fuse to the reconfiguration
registers of the ram. (Assuming that smart_red signal is tied to 1). So we have to make
sure that, the system is still in the reset state till the fuse load happens.
Load Time =
Tsms_clk x (clk_relation x (Fuse_box_size) + $foreach

(STAR_Memory_NB +5) +100)
Fuse_load_time = WRCK_Period *( (Max No of Fuses + 2) * No of Inst ) +

Clk_period * (Bits in the Word*No of Inst + 100)
= 16 * (6+2) * 4 + (32*4+100)/2 VCXO clocks.
= 626 VCXO clocks.
6.1
Regular Power-On reset sequence
The power-on reset sequence, when the internal PLL is used.
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WRCK=VCXO/16
clk = 166 MHz (core clock)
BCLK = clk
128 vcxo clocks
POR_L
50 us
100 us
WRSTN_L
.
3 BCLK
STR_Ready
> 32WRCK
(32*16 VCXO clocks)
system_rst_l
6.2
Hard reset sequence
The Hard reset sequence, when internal is not used.
WRCK=VCXO/16
WRCK=JTCK when VBistEn[2] = 1
clk = core clock
BCLK = clk
HRST_L
STR_Ready
3 BCLK
.
WRSTN_L
128
VCXO
clocks
> 32 WRCK
(32*16 VCXO clocks)
system_rst_l
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Note: After de-asserting of SMS resets, it takes 3 BCLK clocks for STR_ready to
go Low, and approximate fuse load time is >32 * WRCK . So reset module can look
for the STR_ready after 32 WRCK clocks for de-asserting the system reset.
*128 VCXO clock cycle duration is used to assert SMS resets after clocks are stable.
Test Algorithms for 512k SP and DP SRAMS.
9.1.1 Test Algorithm for Single Port STAR memories

March ED (15N + 2)
W(0000)
R(0000), W(1111), R(1111), W(0000)
R(0000), W(1111)
R(1111), W(0000), R(0000), W(1111)
De(lay)
R(1111)
R(1111), W(0000)
Del
R(0000)
WM(1111), R(0000) (For one(Min) address);
Notations:
R Read.
W Write.
WM Write with Masking all bits.
Del Delay
Background patterns:
CM=4
ADR1 ADR0 Pattern
c0 0 0 00000000...(00...)
c1 0 1 00000000...(00...)
c2 1 0 00000000...(00...)
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c3 1 1 00000000...(00...)
CM=8
For all combinations of ADR2, ADR1, ADR0, all 0 patterns work here.
CM=16
For all combinations of ADR3, ADR2, ADR1, ADR0, all 0 pattern work.
When going from one row to the next, the patterns are to be inverted.
9.1.2 Test Algorithm for Dual Port STAR memories
March (32N + 4)
[ WA(0000)];
[ RAT2B(0000), WAT2B(1111), RA(1111), WA(0000)];
[ RAB(0000), RA(0000), WA(1111)];
[ RAT2B(1111), WAT2B(0000), RA(0000), WA(1111)];
Del;
[ RA(1111)];
[ RAB(1111), RA(1111), WA(0000)];
Del;
[ RA(0000)];
[ RAB(0000), RB(0000), WB(1111) ];
[ RBT2A(1111), WBT2A(0000), RB(0000), WB(1111) ];
[ RAB(1111), RB(1111), WB(0000) ];
[ RBT2A(0000), WBT2A(1111), RB(1111), WB(0000) ];
[ RB(0000) ];
WMA(1111), RB(0000), WMB(1111), RA(0000) (For one(Min) address);
Notations:
RA Read from Port A. No operation on Port B. Test2A/ Test2B disabled.
RB Read from Port B. No operation on Port A. Test2A/ Test2B disabled.
RAB Read from Port A and from Port B. Test2A/ Test2B disabled.
RBT2A Read from Port B. No operation on Port A.Test2A enabled. Test2B disabled.
RAT2B Read from Port A. No operation on Port B. Test2A disabled. Test2B enabled.
WA Write through Port A. No operation on Port B. Test2A/ Test2B disabled.
WAT2B Write through Port A. No operation on Port B.Test2A disabled. Test2B
enabled.
WB Write through Port B. No operation on Port A. Test2A/ Test2B disabled.
WBT2A Write through Port B. No operation on Port A. Test2A enabled. Test2B
disabled.
WMA Write through Port A. Mask all bits. No operation on Port B. Test2A/ Test2B
disabled.
WMB - Write through Port B. Mask all bits. No operation on Port A.Test2A/ Test2B
disabled.
Del Delay.
Background patterns:
CM=4
ADR1 ADR0 Pattern
c0 0 0 00000000...(00...)
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c1 0 1 11111111...(11...)
c2 1 0 00000000...(00...)
c3 1 1 11111111...(11...)
CM=8
ADR2 ADR1 ADR0 Pattern
c0 0 0 0 00000000...(00...)
c1 0 0 1 11111111...(11...)
c2 0 1 0 00000000...(00...)
c3 0 1 1 11111111...(11...)
c0 1 0 0 00000000...(00...)
c1 1 0 1 11111111...(11...)
c2 1 1 0 00000000...(00...)
c3 1 1 1 11111111...(11...)
CM=16
The same above patterns repeat for ADR3=0 and 1
When going from one row to the next, the patterns are to be inverted.
9.1.3 Mixed Test algorithm for Single / Dual Port STAR memories
March (32N + 4)
[ WA(0000)];
[ RAT2B(0000), WAT2B(1111), RA(1111), WA(0000)];
[ RAB(0000), RA(0000), WA(1111)];
Virage Logic Corp Proprietary
User Guide 75 STAR Processor for SMS 512k SP/DP
STAR/ASAP SRAM
[ RAT2B(1111), WAT2B(0000), RA(0000), WA(1111)];

Del;
[ RA(1111)];
[ RAB(1111), RA(1111), WA(0000)];
Del;
[ RA(0000)];
[ RAB(0000), RB(0000), WB(1111) ];
[ RBT2A(1111), WBT2A(0000), RB(0000), WB(1111) ];
[ RAB(1111), RB(1111), WB(0000) ];
[ RBT2A(0000), WBT2A(1111), RB(1111), WB(0000) ];
[ RB(0000) ];
WMA(1111), RB(0000), WMB(1111), RA(0000) (For one(Min) address);
Notations:
RA For SP: Operation Read;
For DP: Read from Port A. No operation on Port B. Test2A/ Test2B disabled.
RB For SP: Operation Read;
For DP: Read from Port B. No operation on Port A. Test2A/ Test2B disabled.
RAB For SP: Operation Read;
For DP: Read from Port A and from Port B. Test2A/ Test2B disabled.
RBT2A For SP: Operation Read;
For DP: Read from Port B. No operation on Port A.Test2A enabled. Test2B
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disabled.
RAT2B For SP: Operation Read;
For DP: Read from Port A. No operation on Port B. Test2A disabled. Test2B
enabled.
WA For SP: Operation Write;
For DP: Write through Port A. No operation on Port B. Test2A/ Test2B disabled.
WB For SP: Operation Write;
For DP: Write through Port B. No operation on Port A. Test2A/ Test2B disabled.
WAT2B For SP: Operation Write;
For DP: Write through Port A. No operation on Port B.Test2A disabled. Test2B
enabled.
WBT2A For SP: Operation Write;
For DP: Write through Port B. No operation on Port A. Test2A enabled. Test2B
disabled.
WMA For SP: Operation Write. Mask all bits;
For DP: Write through Port A. Mask all bits. No operation on Port B. Test2A/
Test2B disabled.
WMB - For SP: Operation Write. Mask all bits;
For DP: Write through Port B. Mask all bits. No operation on Port A.Test2A/ Test2B
disabled.
Del Delay.
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Instructions Detail for the STAR processor.
8.1
FUNCTIONAL (BYPASS)
FUNCTIONAL and BYPASS instructions has the same opcode. To put
the SMS into the FUNCTIONAL (BYPASS) Mode the following
instruction value should be loaded into the WIR:
Mnemonic
Binary opcode
BYPASS
00000
In this mode a one-bit bypass register is selected between

serial input and serial output pins of the SMS.
Memory runs in the functional mode.
8.2
BIST_PRODUCTION
To put the SMS into the Bist Production Mode the following
Mnemonic
Binary opcode
BIST_PRODUCTION
00001
At the end of the at-speed test run the STR-Ready signal goes
high. The high level of the BistError indicates that memory
fault(s) has been detected during the test run.
8.3
BIST_DIAGNOSTIC
To put the STAR Memory System into the BIST Diagnostic Mode the
following instruction value should be loaded into the WIR:
Mnemonic
Binary opcode
BIST_DIAGNOSTIC
00010
During the Diagnostic test run once a failure is detected,

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270031805.doc
the STAR Memory System enters the halt state and the
CurrentError goes high. The STAR Memory System will stay
in the halt state until the failure diagnostic data is scanned
out using the Scan Out DR procedure within 214 WRCK cycles.
After scanning out of the DR, CurrentError becomes low and the
STAR Memory System resumes test running.
8.4
BIRA_BISR_PF0
To put the STAR Memory System into the BiraBisr Mode the
following instruction value instruction should be
loaded into the WIR:
Mnemonic
Binary opcode
BIRA_BISR_PF0
00011
In this instruction the BIST switches into the production mode and
reports results using the BistError port or appropriate status bit
upon the end of test run. In this mode the BIRA engine works in
parallel with BIST engine and analyses the occurred faults on the
fly. Upon the test run completed, the BIRA engine comes up with
the BiraFail set. The high level of BiraFail, both port and status
bit, indicate that a non-repairable set of faults has been found.
The low level of the BiraFail, both port and status bit, indicate
that the occurred faults have been covered with the redundant
elements and the Memory Reconfiguration registers have been loaded
with repair data obtained from the T&R (Test and Repair) engine
(soft repair).
8.5
BIRA_BISR_PF1
To put the STAR Memory System into the BiraBisr Mode the
Mnemonic
Binary opcode
BIRA_BISR_PF1
00100
In this instruction the BIST switches into the production mode and
reports results using the BistError port upon the end of test run.
In this mode the BIRA engine (the results of BIRA analysis will be
based on the contents of register with information about detected
faults from pre-run tests) works in parallel with BIST engine and
analyses the occurred faults on the fly. Upon the test run
completed, the BIRA comes up with the BiraFail set. The high level
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of BiraFail indicates that a non-repairable set of faults has been

found. The low level of the BiraFail indicates the occurred faults
have been covered with the redundant elements and the Memory
Reconfiguration registers have been loaded with repair data
obtained from the T&R engine (soft repair).
8.6
EXT_BIRA_PF0
To put STAR Memory System into ExtBira Mode the following
Mnemonic
Binary opcode
EXT_BIRA_PF0
00101
In this mode the BIST circuitry runs at speed and the results are
collected by BIRA engine. Once the STR_Ready signal goes to high,
the repair information is ready to be read out by the external
device using the P1500 interface. The Scan out DR procedure
performs scanning out of the repair information for 36 WRCK cycles.
8.7
EXT_BIRA_PF1
To put STAR Memory System into the ExtBira Mode the following
Mnemonic
Binary opcode
EXT_BIRA_PF1
00110
In this mode the BIST circuitry runs at speed and collects the
results of the BIRA circuitry(the results of BIRA analysis will be
based on the contents of register with information about detected
faults from pre-run tests) works in parallel with BIST engine.
Once the STR_Ready signal goes to high, the repair information is
ready to be read out by the external device using the P1500
interface. The Scan out DR procedure performs scanning out of the
repair information for 36 WRCK cycles.
8.8
EXT_BISR
To put STAR Memory System into the ExtBisr Mode the
Mnemonic
EXT_BISR
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Binary opcode
8.9
00111
In this mode the repair information from the external source can
be downloaded into the memory's reconfiguration register through
P1500 interface using the Scan In DR operation for
192 WRCK cycles.
This mode provides the diagnostic functionalities when testing
the STAR memory Soft repair features.
SERIAL_SF1
The following instruction value should be loaded
into the WIR in order to force the scan chain data
(preloaded in boundary scan registers) to the memory
test inputs (address, data, control)
Mnemonic
Binary opcode
8.10
SERIAL_SF1
01001
LOAD_FUSE_PF0
To load the repair information from repair box
into the reconfiguration register of the STAR SRAM(s)
the following instruction value should be loaded
into the WIR:
Mnemonic
Binary opcode
LOAD_FUSE_PF0
01011
By executing this instruction the engine generating repair

information for STAR memories reads out a compressed repair data
from Repair Box, expands this data and loads this into
reconfiguration registers of STAR instances.
8.11
LOAD_FUSE_PF1
To load the repair information from repair box into the
reconfiguration register of the STAR SRAM(s) the following
Mnemonic
Binary opcode
LOAD_FUSE_PF1
01100
By executing this instruction the engine generating repair

information for STAR memories reads out a compressed repair data
30
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from Repair Box, expands this data and loads this into
reconfiguration registers of STAR instances.
In contrast to LOAD_FUSE_PF0 instruction, the repair data is also
loaded in register that during the Production tests run stores the
faults. This is done in order to provide under Soft repair the new
faults adding to previously detected ones. Typically this
instruction is applied prior to:
- BIRA_BISR_PF1 instruction run
- EXT_BIRA_PF1 instruction run
8.12
LOAD_MEM_PARAM
To load the memory parameters such as AWT, RM (Read Margin),
Test1, Test2(only for dual port memories) the following
Mnemonic
Binary opcode
8.13
LOAD_MEM_PARAM
01101
MPREG_RESET
To reset the memory parameters register the following
Mnemonic
Binary opcode
8.14
MPREG_RESET
01110
SET_FUSE_BOX_LOADED
In order the STAR Processor uses the data in the scanable part of
Repair Box that was serially preloaded the flag FUSEBOXLOADED
should be set. The instruction value is the following:
Mnemonic
Binary opcode
8.15
SET_FUSE_BOX_LOADED
10100
In order the STAR Processor could use the data stored in
the non-volatile part of the Repair Box the flag FUSEBOXLOADED
should be reset if that used to be set before.
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Mnemonic
Binary opcode
10101
The same can be reached by using the Reset WIR operation.
8.16
FUSE_BOX_LOADING
To provide loading of information from an external source through
P1500 interface into Repair Box the following instruction should be
Mnemonic
Binary opcode
8.17
FUSE_BOX_LOADING
10110
SCHEDULE_LOADING
To provide loading of information about the sequence
of instance testing the following instruction value
should be loaded into the WIR:
Mnemonic
Binary opcode
8.18
SCHEDULE_LOADING
10111
RESET_SCHEDULE
To reset the information about the sequence of instance
testing to zero the following instruction should be
Mnemonic
Binary opcode
RESET_SCHEDULE
11000
After that instruction applied all the instances will be tested in

parallel.
8.19
SERIAL_SF0
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To provide serial access to Boundary scan registers through P1500

interface, the following instruction should be loaded into the WIR:
Mnemonic
Binary opcode
SERIAL_SF0
11001
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SMS Methodology

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SMS Methodology

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Naksha Technologies Inc

1313 North Milpitas Blvd #165.

Figure : 1 typical SOC with SMS.

Figure 2. A Typical multi SMS System

Understanding the redundant Memories

Consider a simple memory (8x4) as an example to understand the concept.

Figure 3: 8x4 Redundant Memory (Column redundancy)

R-1 R-2 R-3

Soft Repair and Hard repair

SMS HARDWARE IMPLEMETATION (SMS Generation)

3.0 Envrinment setup and commands to launch the tool.

3.1 Getting Started

3.2 Specifying the STAR Memory configuration(s)

Figure 3-1: Integrators Memory Generation GUI

3.3 Specifying the fuse box

Figure 3-2: Integrators Fuse box Generation GUI

3.4 Specifying the STAR processor configuration

Figure 3-3: Integrators STAR processor generation GUI

3.5 Generating the STAR Memory System

SMS integration in to the chip.

NAKSHA COMMUNICATIONS, INC CONFIDENTIAL

Mustang SMS-JTAG interface

NAKSHA COMMUNICATIONS, INC CONFIDENTIAL

Mustang SMS-JTAG interface

JTAG-SMS Interface Details

Block level Details of IEEE P1500 standard is shown below.

Figure 1 IEEE P1500 Interface Memory System

NAKSHA COMMUNICATIONS, INC CONFIDENTIAL

Mustang SMS-JTAG interface

SMS(P1500) and JTAG connectivity

NAKSHA COMMUNICATIONS, INC CONFIDENTIAL

Functional Ram Ports

Mustang SMS-JTAG interface

Figure 4 JTAG - SMS Interface

NAKSHA COMMUNICATIONS, INC CONFIDENTIAL

Mustang SMS-JTAG interface

Output Port Names

Running SMS Tests.

Load Opcode in to the SMS WIR Register

NAKSHA COMMUNICATIONS, INC CONFIDENTIAL

Shift 6 bits of opcode (000010 BIST_DIAGNOSTIC) in to the WIR. Data will

4.1.1 Observe the Status of a Diagnostic Run

Mustang SMS-JTAG interface

The SMS Status Register in the Jtag Interface represents the

4.1.3 Scanning out the Diagnostic Data from the SMS

4.1.4 VBIST pass/fail test sequence.

NAKSHA COMMUNICATIONS, INC CONFIDENTIAL

Mustang SMS-JTAG interface

f) Loding the Jtag Instruction PROG_VBIST_EN_REG . Shift the Data through

4.1.5 VBIST Fuse repair signature test sequence.

Loding the Jtag Instruction PROG_VBIST_EN_REG . Shift the Data through

NAKSHA COMMUNICATIONS, INC CONFIDENTIAL

Mustang SMS-JTAG interface

Clocks and Resets

SMS has three input clocks.

Mustang SMS-JTAG interface

Generating the WRCK clock

NAKSHA COMMUNICATIONS, INC CONFIDENTIAL

Mustang SMS-JTAG interface

SMS has 2 resets WRSTN and sms_rst.

Tsms_clk x (clk_relation x (Fuse_box_size) + $foreach

Fuse_load_time = WRCK_Period *( (Max No of Fuses + 2) * No of Inst ) +

Regular Power-On reset sequence

The power-on reset sequence, when the internal PLL is used.

Fuse_load_time = WRCK_Period ( (Max No of Fuses + 2) No of Inst ) +