Professional Documents
Culture Documents
6, DECEMBER 2007
3001
AbstractAdjustable-speed drives involve common-mode voltages, which generate common-mode currents flowing to the
ground through stray capacitances of electric machines. These
currents are known to provoke premature motor-bearing failures, as well as electromagnetic interferences disturbing neighbor electronic devices. Furthermore, high-voltage applications
involve high levels of these conducted emissions, which must be
lowered by using bulky and expensive filters. This paper aims
at elaborating a new pulsewidth-modulation (PWM) strategy in
order to reduce the common-mode currents generated by threelevel neutral-point-clamped inverters. The proposed strategy also
provides the ability to balance the neutral point of the dc-bus
capacitors. Experimental results both in time and frequency domains confirm that the new PWM improves the electromagneticcompatibility behavior of the drive compared with conventional
strategies.
Index TermsCommon-mode currents, electromagnetic
compatibility (EMC), neutral-point-clamped (NPC) inverters,
pulsewidth modulation (PWM), variable-speed drives.
I. I NTRODUCTION
pulsewidth-modulation (PWM) strategies for classical hardswitched two-level and multilevel inverters [1], [7][11]. Since
industrial application requires low-cost and easy-to-implement
solutions, the work on PWM strategies is promising because no
additional component is needed.
Moreover, multilevel voltage-source inverters are interesting for high-power applications because they allow reduced
voltage constraints on the switches, as well as lowered total
harmonic distortion (THD) of the output voltages. Furthermore,
their reduced step-voltage variations involve less EMI than the
conventional two-level inverters.
This paper focuses on the three-level neutral-point-clamped
(NPC) inverter and proposes a new PWM strategy [13] which
is able to reduce the generated common-mode currents. The
basic control principles of the three-phase NPC inverter are
introduced, and the link between the PWM strategy and the
common-mode voltage is clarified. Two solutions for the reduction of common-mode currents are presented and combined
into the proposed PWM: the Flat-Top technique and the doublecommutation mechanism. Compared with previous strategies,
the new method provides several degrees of freedom which
are used to ensure the real synchronism of the double commutations by controlling their nature and avoiding dead-time
effects.
A very important issue in using an NPC inverter is the ability
to control the midpoint voltage of the dc-bus capacitors [12].
This paper shows that the degrees of freedom of the new PWM
still permit this regulation in addition to the electromagneticcompatibility (EMC) improvement of the drive. The maximum
balancing capacity is also compared with conventional PWM
through simulation.
The proposed strategy has been implemented into a
20-kVA NPC prototype with a new carrier-based modulator.
Time- and frequency-domain experimental results confirm the
best EMC performances of the new PWM compared with
conventional strategies. The dc-bus balancing ability is also
verified.
II. C ONVENTIONAL C ARRIER -B ASED C ONTROL OF
AN NPC C ONVERTER
A. General Overview
The three-phase three-level NPC inverter is shown in Fig. 1.
The dc bus (E) is distributed on the two capacitors (C), and
3002
Fig. 3.
their respective voltages are noted us1 and us2 (normally us1 =
us2 = E/2). Therefore, the output voltage (VAO , VBO , or
VCO ) between one phase (A, B, or C) and the midpoint of
the dc-bus capacitors (O) can either be E/2, 0, or +E/2
according to the configuration of the switches. This corresponds
to three possible states symbolized as 1, 0, and +1. Thus, the
whole system has 27 possible states (33 ) which are represented
in a well-known vectorial diagram (Fig. 2). In this figure, the
phase-to-neutral voltages of the load (VAN , VBN , VCN ), defined
by (1), can be deduced from the position of the states by
projection on the axes A, B, and C.
Given a reference vector (V ref ), the goal of the PWM
strategy is to build up this vector by using neighbor states
from the figure (such as the ones circled around V ref ). It
can be noticed that this diagram contains redundant states, as
some vectors can be obtained with different combinations of
states (near the center of the figure): This provides a degree of
freedom about the choice of the states.
One important quantity is the common-mode voltage (VCM )
defined in (2). It is directly linked to the states of the three
) is reported between
legs; thus, its normalized value (VCM
(1)
(2)
VIDET et al.: CARRIER-BASED PWM PROVIDING COMMON-MODE CURRENTS REDUCTION AND DC-BUS BALANCING
3003
(3)
k {A, B, C} :
(4)
k {A, B, C} :
k {A, B, C} :
C. Midpoint Balancing
The use of an NPC converter must comply with the requirement of midpoint-balancing ability. Indeed, a voltage imbalance
on the dc-bus capacitors would induce a voltage increase on
some switches, which could reach dangerous levels. Normally,
the us1 and us2 voltages (Fig. 1) should be equal to E/2
and E/2, respectively; thus, their sum us [(7)] should be
null. However, under particular control and load conditions,
us might drift from zero and diverge [16] (us actually
characterizes the dc-bus imbalance). Therefore, a solution to
bring it back to zero must be provided, which can be obtained
with appropriate control of the PWM [17].
Since the voltage references (hAN , hBN , hCN ) cannot be
modified, the homopolar component hNO is the degree of
us = us1 + us2
i0 = C dus/dt
(7)
(8)
(9)
3004
shows one commutation and its associated common-modecurrent response. Since stray inductive elements also exist
along the common-mode path, ICM runs into oscillationsat
1.8 MHz in this example.
Thus, in order to reduce the common-mode currents, PWM
strategies should limit the number of transitions in the generated
common-mode voltage.
B. Flat-Top Solution
As long as conventional strategies are considered, there
are as many common-mode-current pulses as commutations.
Consequently, the only solution is to limit the number of
commutations, which means the use of the Flat-Top technique.
Indeed, PWM strategies can be classified as continuous
(CPWM) or discontinuous (DPWM) modulations, depending
on the hNO (t) characteristic [21]. In practice, during one
switching period, the three legs of the inverter are switching in CPWM, whereas only two are switching in DPWM,
in which the Flat-Top technique is applied. Moreover, each
switching leg performs two commutations per switching period.
Therefore, CPWM strategies involve six commutations per
switching period, whereas DPWM perform only four. Therefore, the Flat-Top technique limits the number of commonmode-voltage transitions to four per switching period instead
of six.
However, building up any reference vector requires at least
two switching legs. Therefore, conventional PWM cannot reduce the common-mode current below four pulses per switching period.
Fig. 5.
Fig. 6.
C. Double-Commutation Solution
VIDET et al.: CARRIER-BASED PWM PROVIDING COMMON-MODE CURRENTS REDUCTION AND DC-BUS BALANCING
Fig. 7.
3005
100
E
Uk2 .
(10)
k2
Fig. 8. Degree of freedom: Choice of the triangle and its sequence of states.
TABLE I
NUMBER OF AVAILABLE TRIANGLES
3006
TABLE II
NUMBER OF AVAILABLE VALUES FOR THE HOMOPOLAR COMPONENT
VIDET et al.: CARRIER-BASED PWM PROVIDING COMMON-MODE CURRENTS REDUCTION AND DC-BUS BALANCING
3007
3008
Fig. 11. Degradation of the balancing capacity with the new PWM.
Fig. 13.
Fig. 14.
Experimental setup.
i max
0
T0
(12)
VIDET et al.: CARRIER-BASED PWM PROVIDING COMMON-MODE CURRENTS REDUCTION AND DC-BUS BALANCING
3009
Fig. 17. Importance of the EMC constraints: Proposed PWM without meeting
the (a) first or the (b) second constraint (time: 20 s/div, voltage: 300 V/div,
current: 0.5 A/div).
3010
Fig. 19. Example of the dc-bus balancing with the new PWM (time:
100 ms/div, voltages: 20 V/div (us1 and us2) and 10 V/div (us),
current: 2 A/div).
[6] H. Xiangning, A. Chen, W. Hongyang, D. Yan, and Z. Rongxiang, Simple passive lossless snubber for high-power multilevel inverters, IEEE
Trans. Ind. Electron., vol. 53, no. 3, pp. 727735, Jun. 2006.
[7] H. J. Kim, H. D. Lee, and S. K. Sul, A new PWM strategy for commonmode voltage reduction in neutral point clamped inverter-fed AC motor drives, IEEE Trans. Ind. Appl., vol. 37, no. 6, pp. 18401845,
Nov./Dec. 2001.
[8] H. Zhang, A. Von Jouanne, S. Dai, A. K. Wallace, and F. Wang,
Multilevel inverter modulation schemes to eliminate common mode
voltages, IEEE Trans. Ind. Appl., vol. 36, no. 6, pp. 16451653,
Nov./Dec. 2000.
[9] A. Benabdelghani, C. A. Martins, X. Roboam, and T. A. Meynard, Use
of extra degrees of freedom in multilevel drives, IEEE Trans. Ind. Appl.,
vol. 49, no. 5, pp. 965977, Oct. 2002.
[10] J. Zitzelsberger and W. Hofmann, Reduction of bearing currents in
inverter fed drive applications by using Sequentially Positioned Pulse
modulation, EPE J., vol. 14, no. 4, pp. 1925, Nov. 2004.
[11] J. Rodriguez, J. Pontt, P. Correa, P. Cortes, and C. Silva, A new
modulation method to reduce common-mode voltages in multilevel inverters, IEEE Trans. Ind. Electron., vol. 51, no. 4, pp. 834839,
Aug. 2004.
[12] J. Pou, D. Boroyevich, and R. Pindado, Effects of imbalances and
nonlinear loads on the voltage balance of a neutral-point-clamped inverter, IEEE Trans. Power Electron., vol. 20, no. 1, pp. 123131,
Jan. 2005.
[13] A. Videt, P. Le Moigne, N. Idir, P. Baudesson, and J. Ecrabey, A new
carrier-based PWM for the reduction of common mode currents applied
to neutral-point-clamped inverters, in Proc. IEEE APEC, Feb. 2007,
pp. 12241230.
[14] P. Delarue, P. Le Moigne, P. Baudesson, P. Bartholomeus, and
X. Cimetire, Dispositif de commande dun convertisseur dnergie lectrique et convertisseur comportant un tel dispositif, Patent 0 413 872,
Dec. 2004.
[15] P. Delarue, P. Bartholomeus, P. Le Moigne, P. Baudesson, and
X. Cimetire, Convertisseur 4 bras: montage N.P.C. avec contrle de
point milieu utilisant un modulateur porteuses triangulaires, in Proc.
EPF, 2004. CD-ROM.
[16] J. Pou, P. Rodriguez, V. Sala, J. Zaragoza, R. Burgos, and D. Boroyevich,
Fast-processing modulation strategy for the neutral-point-clamped converter with total elimination of the low-frequency voltage oscillations in
the neutral point, in Proc. IEEE IECON, Nov. 2005, pp. 10541059.
[17] A. Bendre, G. Venkataramanan, D. Rosene, and V. Srinivasan, Modeling
and design of a neutral-point voltage regulator for a three-level diodeclamped inverter using multiple-carrier modulation, IEEE Trans. Ind.
Electron., vol. 53, no. 3, pp. 718726, Jun. 2006.
[18] H. Midavaine, P. Le Moigne, and P. Bartholomeus, Multilevel threephase rectifier with sinusoidal input currents, in Proc. IEEE PESC, 1996,
pp. 15951600.
[19] H. J. Kim, D. W. Jung, and S. K. Sul, A new discontinuous PWM
strategy of neutral-point clamped inverter, in Proc. IEEE IAS, Oct. 2000,
pp. 20172023.
[20] P. Delarue, P. Le Moigne, P. Baudesson, P. Bartholomeus, and
X. Cimetire, Dispositif de commande dun convertisseur et convertisseur lectrique comportant un tel dispositif, Patent 0 501 888, Feb. 2005.
[21] A. M. Hava, R. J. Kerkman, and T. A. Lipo, Simple analytical and graphical methods for carrier-based PWM-VSI drives, IEEE Trans. Power
Electron., vol. 14, no. 1, pp. 4961, Jan. 1999.
[22] Y. S. Lai and F. S. Shyu, Optimal common-mode voltage reduction
PWM technique for inverter control with consideration of the dead-time
effectsPart I: Basic development, IEEE Trans. Ind. Appl., vol. 40,
no. 6, pp. 16051612, Nov./Dec. 2004.
[23] A. Bendre, S. Krstic, J. Vander Meer, and G. Venkataramanan, Comparative evaluation of modulation algorithms for neutral-point-clamped
converters, IEEE Trans. Ind. Appl., vol. 41, no. 2, pp. 634643,
Mar./Apr. 2005.
[24] N. Idir, J. J. Franchaud, and R. Bausire, Effects of inverter commutations on common mode and differential mode currents in adjustable speed
drives, Int. Rev. Elect. Eng. (IREE), no. 5, Oct. 2006.
[25] P. F. Seixas, M. A. Severo Mendes, P. Donoso-Garcia, and A. M. N. Lima,
A space vector PWM method for three-level voltage source inverters, in
Proc. IEEE APEC, Feb. 2000, vol. 1, pp. 549555.
[26] D. Drennan and H. d. T. Mouton, An experimental investigation into natural balancing of three level neutral point clamped multi-level inverters,
in Proc. AFRICON, Oct. 2002, vol. 2, pp. 749754.
[27] A. Videt, P. Le Moigne, P. Baudesson, and N. Idir, Dispositif et procd
de commande dun convertisseur et convertisseur lectrique comportant
un tel dispositif, Patent 0 604 090, Jun. 2006.
VIDET et al.: CARRIER-BASED PWM PROVIDING COMMON-MODE CURRENTS REDUCTION AND DC-BUS BALANCING
Arnaud Videt received the M.S. degree in electrical engineering from the University of Lille, Lille,
France, in 2005. He is currently working toward
the Ph.D. degree in electrical engineering at the
Laboratoire dElectrotechnique et dElectronique de
Puissance, Ecole Centrale de Lille, Lille.
His main research interests include power electronics and electromagnetic compatibility for motordrive applications.
3011
Philippe Le Moigne (M93) received the Engineering degree from the Institut Industriel du Nord, Lille,
France, in 1986 and the Ph.D. degree in electrical engineering from the University of Lille, Lille,
in 1990.
He is currently a Professor with the Laboratoire
dElectrotechnique et dElectronique de Puissance,
Ecole Centrale de Lille, Lille, where he is also the
Head of the Power Electronics Department. His major fields of interest include hard switched power
converters and supercapacitors, especially the control of multilevel topologies for medium- and high-power applications with the
aim of high power quality and high efficiency.