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FEATURES
DESCRIPTION
U
APPLICATIONS
TYPICAL APPLICATION
Low Power, 200kHz, 14-Bit Sampling A/D Converter
5V
10F
VDD
1.0
SER/PAR
LTC1418
D13
AIN+
14-BIT ADC
14
4.096V
REFCOMP
10F
SELECTABLE
SERIAL/
PARALLEL
PORT
BUFFER
D5
D4 (EXTCLKIN)
D3 (SCLK)
D2 (CLKOUT)
D1 (DOUT)
D0 (EXT/INT)
0.5
INL (LSBs)
S/H
AIN
0.5
8k
VREF
TIMING AND
LOGIC
2.5V
REFERENCE
1F
BUSY
CS
RD
CONVST
SHDN
1.0
0
4096
8192
12288
16384
OUTPUT CODE
AGND
VSS
(0V OR 5V)
DGND
1418 TA02
1418 TA01
LTC1418
W W
PARAMETER
28 VDD
27 VSS
VREF
26 BUSY
REFCOMP
25 CS
AGND
24 CONVST
D13 (MSB)
23 RD
D12
22 SHDN
D11
21 SER/PAR
D10
20 D0 (EXT/INT)
D9 10
19 D1 (DOUT)
D8 11
18 D2 (CLKOUT)
D7 12
17 D3 (SCLK)
D6 13
16 D4 (EXTCLKIN)
DGND 14
15 D5
G PACKAGE
28-LEAD PLASTIC SSOP
N PACKAGE
28-LEAD NARROW PDIP
MIN
(Note 7)
(Note 8)
Full-Scale Error
Internal Reference
External Reference = 2.5V
Full-Scale Tempco
LTC1418
TYP
MAX
MIN
13
LTC1418A
TYP
MAX
14
UNITS
Bits
0.8
0.5
0.7
1.5
0.35
LSB
20
10
LSB
10
5
60
30
20
5
60
15
LSB
LSB
10
20
1
45
ppm/C
ppm/C
ppm/C
MAX
UNITS
15
5
1.25
LSB
(Note 5)
SYMBOL PARAMETER
CONDITIONS
VIN
IIN
CS = High
CIN
tACQ
Commercial
Industrial
LTC1418ACG
LTC1418ACN
LTC1418AIG
LTC1418AIN
LTC1418CG
LTC1418CN
LTC1418IG
LTC1418IN
A ALOG I PUT
ORDER PART
NUMBER
TOP VIEW
AIN+
AIN
CONDITIONS
PACKAGE/ORDER INFORMATION
(Notes 1, 2)
CO VERTER CHARACTERISTICS
MIN
TYP
0 to 4.096
2.048
V
V
1
25
5
300
300
A
pF
pF
1000
1000
ns
ns
LTC1418
W U
DY A IC ACCURACY
(Note 5)
SYMBOL PARAMETER
CONDITIONS
THD
SFDR
IMD
Intermodulation Distortion
MIN
TYP
79
81.5
94
86
U
U
U
I TER AL REFERE CE CHARACTERISTICS
MAX
UNITS
dB
86
dB
95
dB
90
dB
MHz
0.5
MHz
(Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IOUT = 0
2.480
2.500
2.520
IOUT = 0, Commercial
IOUT = 0, Industrial
10
20
45
0.05
0.05
CONDITIONS
MIN
VDD = 5.25V
VIL
VDD = 4.75V
IIN
VIN = 0V to VDD
CIN
VOH
LSB/ V
LSB/ V
k
(Note 5)
VIH
VOL
ppm/C
ppm/C
TYP
MAX
2.4
UNITS
V
0.8
10
1.4
pF
4.74
V
V
4.0
0.05
0.10
0.4
V
V
10
IOZ
COZ
CS High (Note 9)
ISOURCE
VOUT = 0V
10
mA
ISINK
VOUT = VDD
10
mA
UW
POWER REQUIRE E TS
15
pF
(Note 5)
SYMBOL PARAMETER
CONDITIONS
MAX
UNITS
4.75
MIN
TYP
5.25
4.75
5.25
VDD
VSS
IDD
3.0
3.9
570
2
4.3
4.5
Nap Mode
Sleep Mode
mA
mA
A
A
1.4
0.1
0.1
1.8
Nap Mode
Sleep Mode
mA
A
A
Unipolar
Bipolar
15.0
26.5
21.5
31.5
mW
mW
ISS
PDIS
Power Dissipation
LTC1418
WU
TI I G CHARACTERISTICS
(Note 5)
SYMBOL
PARAMETER
TYP
MAX
fSAMPLE(MAX)
tCONV
Conversion Time
3.4
tACQ
tACQ + tCONV
Acquisition Time
0.3
3.7
t1
CS to RD Setup Time
(Notes 9, 10)
ns
t2
(Notes 9, 10)
40
ns
t3
(Notes 9, 10)
40
t4
(Note 10)
t5
t6
CL = 25pF
t7
t8
t9
t10
CONDITIONS
(Note 10)
MIN
200
kHz
ns
500
ns
35
20
15
500
CL = 25pF
CL = 100pF
70
ns
35
ns
ns
ns
ns
15
30
40
ns
ns
20
40
55
ns
ns
20
25
30
ns
ns
ns
Commercial
Industrial
ns
40
t11
UNITS
t12
RD Low Time
t13
t14
CL = 25pF (Note 9)
t15
CL = 25pF (Note 9)
fSCLK
(Notes 9, 10)
12.5
MHz
fEXTCLKIN
(Notes 9, 10)
0.03
4.5
MHz
tdEXTCLKIN
(Notes 9, 10)
533
tH SCLK
(Notes 9, 10)
10
tL SCLK
(Notes 9, 10)
20
tH EXTCLKIN
(Notes 9, 10)
250
ns
tL EXTCLKIN
(Notes 9, 10)
250
ns
t10
ns
40
ns
35
15
70
ns
25
ns
ns
ns
LTC1418
U W
90
1.0
0.5
DNL ERROR (LSBs)
0.5
0.5
0.5
4096
8192
12288
4096
OUTPUT CODE
12288
8192
OUTPUT CODE
Signal-to-Noise Ratio
vs Input Frequency
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
40
30
70
60
50
40
30
20
10
0
1k
10k
100k
INPUT FREQUENCY (Hz)
1M
10
16384
1k
40
60
3RD
80
THD
2ND
100
120
1k
10k
100k
INPUT FREQUENCY (Hz)
1M
20
40
60
80
100
120
10k
0
fSAMPLE = 200kHz
fIN = 9.9609375kHz
SFDR = 99.32
SINAD = 82.4
fSAMPLE = 200kHz
fIN = 97.509765kHz
SFDR = 94.29
SINAD = 81.4
40
60
80
120
0
10 20
30 40 50 60 70 80 90 100
FREQUENCY (kHz)
1418 F02a
40
60
80
100
100
100
fSAMPLE = 200kHz
fIN1 = 97.65625kHz
fIN2 = 104.248046kHz
20
AMPLITUDE (dB)
20
AMPLITUDE (dB)
80
1M
1418 G04
60
100k
INPUT FREQUENCY (Hz)
1418 G03
1M
20
40
100k
10k
INPUT FREQUENCY (Hz)
1418 G01
1418 G02
20
VIN = 60dB
20
80
AMPLITUDE (dB)
50
1418 G06
1418 TA02
90
VIN = 20dB
60
16384
VIN = 0dB
70
1.0
1.0
120
80
1.0
INL (LSBs)
120
0
10 20
30 40 50 60 70 80 90 100
FREQUENCY (kHz)
1418 F02b
10 20 30 40 50 60 70 80 90 100
FREQUENCY (kHz)
1418 G05
LTC1418
U W
DISTORTION (dB)
20
40
VSS
VDD
80
DGND
100
90
10
80
60
70
60
50
40
30
20
10
120
1k
10k
100k
1M
FREQUENCY (Hz)
7
6
5
4
3
2
1
0
10M
10
100
1k
10k 100k
INPUT FREQUENCY (Hz)
1418 G08
1M
10
100
100k
1k
10k
INPUT SOURCE RESISTANCE ()
1M
1418 G10
1418 G09
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
75 50 25
75 50 25
0
75 50 25
1418 G11
1418 G13
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
100
150
200
250
50
SAMPLING FREQUENCY (kHz)
300
1418 G14
0
0
50
150
200
250
100
SAMPLING FREQUENCY (kHz)
300
1418 G15
50
150
200
250
100
SAMPLING FREQUENCY (kHz)
300
1418 G16
LTC1418
U
PIN FUNCTIONS
AIN+ (Pin 1): Positive Analog Input.
AIN (Pin 2): Negative Analog Input.
VREF (Pin 3): 2.50V Reference Output. Bypass to AGND
with 1F.
REFCOMP (Pin 4): 4.096V Reference Bypass Pin.
Bypass to AGND with 10F tantalum in parallel with 0.1F
ceramic.
AGND (Pin 5): Analog Ground.
D13 to D6 (Pins 6 to 13): Three-State Data Outputs
(Parallel). D13 is the most significant bit.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
D5 (Pin 15): Three-State Data Output (Parallel).
D4 (EXTCLKIN) (Pin 16): Three-State Data Output
(Parallel). Conversion clock input (serial) when Pin 20
(EXT/INT) is tied high.
D3 (SCLK) (Pin 17): Three-State Data Output (Parallel).
Data clock input (serial).
D2 (CLKOUT) (Pin 18): Three-State Data Output (Parallel).
Conversion clock output (serial).
D1 (DOUT) (Pin 19): Three-State Data Output (Parallel).
Serial data output (serial).
D0 (EXT/INT) (Pin 20): Three-State Data Output (Parallel).
Conversion clock selector (serial). An input low enables
TEST CIRCUITS
Load Circuits for Access Timing
5V
1k
DBN
1k
DBN
1k
CL
DGND
DBN
CL
DBN
1k
30pF
30pF
DGND
B) HI-Z TO VOL AND VOH TO VOL
1418 TC01
A) VOH TO HI-Z
B) VOL TO HI-Z
1418 TC02
LTC1418
W
FUNCTIONAL BLOCK DIAGRA
U
CSAMPLE
AIN+
VDD: 5V
CSAMPLE
AIN
VREF
2.5V
8k
ZEROING SWITCHES
2.5V REF
+
REF AMP
COMP
REFCOMP
4.096V
AGND
DGND
14
SUCCESSIVE APPROXIMATION
REGISTER
SHIFT
REGISTER
D13
D0
D3/(SCLK)
INTERNAL
CLOCK
CONTROL LOGIC
MUX
D1/(DOUT)
1418 BD
D4 (EXTCLKIN)
APPLICATIONS INFORMATION
CONVERSION DETAILS
The LTC1418 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel or serial output. The ADC
is complete with a precision reference and an internal
clock. The control logic provides easy interface to microprocessors and DSPs (please refer to Digital Interface
section for the data format).
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
AIN+
CSAMPLE+
SAMPLE
ZEROING SWITCHES
HOLD
CSAMPLE
SAMPLE
AIN
HOLD
HOLD
HOLD
CDAC+
+
CDAC
VDAC+
COMP
VDAC
14
SAR
OUTPUT
LATCH
D13
D0
1418 F01
LTC1418
APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE
The LTC1418 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used
to test the ADCs frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algorithm, the ADCs spectral content can be examined for
frequencies outside the fundamental. Figure 2 shows a
typical LTC1418 FFT plot.
0
fSAMPLE = 200kHz
fIN = 9.9609375kHz
SFDR = 99.32
SINAD = 82.4
AMPLITUDE (dB)
20
40
60
80
100
120
10 20
30 40 50 60 70 80 90 100
FREQUENCY (kHz)
1418 F02a
20
AMPLITUDE (dB)
Referring to Figure 1, the AIN+ and AIN inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by
the zeroing switches. In this acquire phase, a minimum
delay of 1s will provide enough time for the sample-andhold capacitors to acquire the analog signal. During the
convert phase the comparator zeroing switches open,
putting the comparator into compare mode. The input
switches the CSAMPLE capacitors to ground, transferring
the differential analog input charge onto the summing
junction. This input charge is successively compared with
the binary weighted charges supplied by the differential
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the differential
DAC output balances the AIN+ and AIN input charges. The
SAR contents (a 14-bit data word) which represent the
difference of AIN+ and AIN are loaded into the 14-bit
output latches.
40
60
80
100
120
10 20
30 40 50 60 70 80 90 100
FREQUENCY (kHz)
1418 F02b
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 2a shows a typical spectral content with
a 200kHz sampling rate and a 10kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 100kHz.
LTC1418
U
APPLICATIONS INFORMATION
14
13
12
EFECTIVE BITS
11
Intermodulation Distortion
10
9
8
7
6
5
4
3
2
10k
100k
INPUT FREQUENCY (Hz)
1k
1M
1418 F03
IMD fa + fb = 20Log
THD = 20Log
40
60
80
100
40
120
0
10 20 30 40 50 60 70 80 90 100
FREQUENCY (kHz)
60
1418 G05
3RD
80
THD
2ND
100
1k
10k
100k
INPUT FREQUENCY (Hz)
1M
1418 G03
10
Amplitude at fa
fSAMPLE = 200kHz
fIN1 = 97.65625kHz
fIN2 = 104.248046kHz
20
20
120
AMPLITUDE (dB)
Amplitude at fa + fb
LTC1418
U
APPLICATIONS INFORMATION
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 77dB (12.5 effective bits).
The LTC1418 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with
frequencies above the converters Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
DRIVING THE ANALOG INPUT
The differential analog inputs of the LTC1418 are easy to
drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN input is grounded). The AIN+ and
A IN inputs are sampled at the same instant. Any
unwanted signal that is common mode to both inputs will
be reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low then the LTC1418
inputs can be driven directly. As source impedance
increases so will acquisition time (see Figure 6). For
minimum acquisition time, with high source impedance, a
buffer amplifier must be used. The only requirement is that
the amplifier driving the analog input(s) must settle after
the small current spike before the next conversion starts
1s for full throughput rate.
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, choose an amplifier that
has a low output impedance (<100) at the closed-loop
bandwidth frequency. For example, if an amplifier is used
in a gain of 1 and has a closed-loop bandwidth of 10MHz,
then the output impedance at 10MHz must be less than
100. The second requirement is that the closed-loop
bandwidth must be greater than 5MHz to ensure adequate
10
0.1
1
10
100
1k
10k
SOURCE RESISTANCE ()
100k
1418 F06
11
LTC1418
U
APPLICATIONS INFORMATION
amplifier. 2.2V to 15V supplies. Good AC performance,
input noise voltage = 12nV/Hz (typ).
LT1630/LT1631: 30MHz, 10V/s, Dual/Quad Rail-to-Rail
Input and Output Precision Op Amps. 3.5mA supply
current per amplifier. 2.7V to 15V supplies. Best AC
performance, input noise voltage = 6nV/Hz (typ),
THD = 86dB at 100kHz.
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1418 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 5MHz. Any noise or
distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For example, Figure 7 shows a 2000pF
capacitor from + AIN to ground and a 100 source resistor
to limit the input bandwidth to 800kHz. The 2000pF
capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silver mica type dielectric capacitors
have excellent linearity. Carbon surface mount resistors can
also generate distortion from self heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
100
ANALOG INPUT
2000pF
AIN+
AIN
4
10F
Input Range
VREF
5V
ANALOG
INPUT
LTC1418
VIN
LT1460
AIN
AGND
1418 F07
AIN+
VOUT
REFCOMP
10F
0.1F
5
VREF
VDD
LTC1418
REFCOMP
AGND
1418 F08
12
LTC1418
U
APPLICATIONS INFORMATION
UNIPOLAR / BIPOLAR OPERATION AND ADJUSTMENT
Figure 9a shows the ideal input/output characteristics for
the LTC1418. The code transitions occur midway between
successive integer LSB values (i.e., 0.5LSB, 1.5LSB,
2.5LSB, FS 1.5LSB). The output code is natural binary
with 1LSB = FS/16384 = 4.096V/16384 = 250V. Figure 9b
shows the input/output transfer characteristics for the
bipolar mode in twos complement format.
Unipolar Offset and Full-Scale Error Adjustment
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figures
10a and 10b show the extra components required for full-
1LSB =
111...111
scale error adjustment. Zero offset is achieved by adjusting the offset applied to the AIN input. For zero offset
error apply 125V (i.e., 0.5LSB) at the input and adjust
the offset at the AIN input until the output code flickers
between 0000 0000 0000 00 and 0000 0000 0000 01. For
full-scale adjustment, an input voltage of 4.095625V
(FS 1.5LSBs) is applied to AIN+ and R2 is adjusted until
the output code flickers between 1111 1111 1111 10 and
1111 1111 1111 11.
Bipolar Offset and Full-Scale Error Adjustment
Bipolar offset and full-scale errors are adjusted in a similar
fashion to the unipolar case. Again, bipolar offset error
must be adjusted before full-scale error. Bipolar offset
FS = 4.096V
16384 16384
111...110
5V
ANALOG INPUT
111...101
OUTPUT CODE
R7
48k
R8
100
R1
50k
111...100
R3
24k
AIN+
AIN
R5 R2
47k 50k
UNIPOLAR
ZERO
000...011
R4
100
R6
24k
000...010
5
0.1F
10F
000...001
VDD
VREF
LTC1418
REFCOMP
AGND V
SS
1418 F10a
000...000
0V
1
LSB
FS 1LSB
INPUT VOLTAGE (V)
1418 F9a
5V
011...111
5V
ANALOG INPUT
BIPOLAR
ZERO
011...110
OUTPUT CODE
R1
50k
R3
24k
000...001
000...000
R4
100
R6
24k
111...110
AIN+
AIN
R5 R2
47k 50k
111...111
4
5
100...001
FS = 4.096V
1LSB = FS/16384
100...000
FS/2
1 0V 1
LSB
LSB
INPUT VOLTAGE (V)
FS/2 1LSB
1418 F9b
10F
0.1F
VDD
LTC1418
VREF
REFCOMP
AGND V
SS
*
1418 F10b
1N5817 5V
13
LTC1418
APPLICATIONS INFORMATION
error adjustment is achieved by adjusting the offset
applied to the AIN input. For zero offset error apply
125V (i.e., 0.5LSB) at AIN+ and adjust the offset
at the AIN input until the output code flickers between
0000 0000 0000 00 and 1111 1111 1111 11. For
full-scale adjustment, an input voltage of 2.047625V
(FS 1.5LSBs) is applied to AIN+ and R2 is adjusted until
the output code flickers between 0111 1111 1111 10 and
0111 1111 1111 11.
BOARD LAYOUT AND GROUNDING
Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best
performance from the LTC1418, a printed circuit board
with ground plane is required. The ground plane under the
ADC area should be as free of breaks and holes as
possible, such that a low impedance path between all ADC
grounds and all ADC decoupling capacitors is provided. It
is critical to prevent digital noise from being coupled to the
analog input, reference or analog power supply lines.
Layout should ensure that digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND) and Pin 14 (DGND) and all other analog
grounds should be connected to this single analog ground
plane. The REFCOMP bypass capacitor and the VDD bypass capacitor should also be connected to this analog
ground plane. No other digital grounds should be con-
AIN+
AIN
ANALOG
INPUT
CIRCUITRY
nected to this analog ground plane. Low impedance analog and digital power supply common returns are essential
to low noise operation of the ADC and the foil width for
these tracks should be as wide as possible. In applications
where the ADC data outputs and control signals are
connected to a continuously active microprocessor bus, it
is possible to get errors in the conversion results. These
errors are due to feedthrough from the microprocessor to
the successive approximation comparator. The problem
can be eliminated by forcing the microprocessor into a
wait state during conversion or by using three-state buffers to isolate the ADC data bus. The traces connecting the
pins and bypass capacitors must be kept short and should
be made as wide as possible.
The LTC1418 has differential inputs to minimize noise
coupling. Common mode noise on the AIN+ and AIN leads
will be rejected by the input CMRR. The AIN input can be
used as a ground sense for the AIN+ input; the LTC1418 will
hold and convert the difference voltage between AIN+ and
AIN. The leads to AIN+ (Pin 1) and AIN (Pin 2) should be
kept as short as possible. In applications where this is not
possible, the AIN+ and AIN traces should be run side by
side to equalize coupling.
SUPPLY BYPASSING
High quality, low series resistance ceramic, 10F bypass
capacitors should be used at the VDD and REFCOMP pins.
Surface mount ceramic capacitors such as Murata
GRM235Y5V106Z016 provide excellent bypassing in a
small board space. Alternatively 10F tantalum capacitors
in parallel with 0.1F ceramic capacitors can be used.
DIGITAL
SYSTEM
LTC1418
VREF
REFCOMP
4
1F
AGND
5
10F
VDD
VSS
27
10F
DGND
28
14
10F
14
J7
J5
JP5A
JP5B
SER/PAR
CS
SHDN
HC14
U7A
HC14
U7B
C13
10F
16V
C11
1000pF
R15
51
D15
SS12
R16
51
C8
1F
16V
JP2
JP4
DGND
JP5C
VOUT
GND TABGND
2
4
VIN
R19
51
R18
10k
R17
10k
LT1121-5
R22
1M
VCC
C4
0.1F
C12
0.1F
R14
20
0.125W
HC14
U7C
VCC
C14
0.1F
EN2
EN1
20
VSS
13
U8F
U8B
7
SINGLE
16
20 B00
19 B01
18 B02
17 B03
16 B04
15 B05
13 B06
12 B07
B04
B03
B02
B01
B00
EXTCLKIN
SCLK
CLKOUT
DOUT
14
U8C
12
74HC244
U8H
74HC244
17
18
R23
100k
B06
B07
B08
B09
U8G
DGND
U8D
74HC244
15
74HC244
U8A
74HC244
13
B11
10 B09
B10
B12
B10
9
11 B08
11
B11
VSS
Q6
D6
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
J8-6
J8-2
J8-1
J8-3
J8-4
J8-5
HEADER
6-PIN
HC14
12
GND
U7G
HC14
14
VCC
VLOGIC
D7
D6
D5
D4
D3
D2
D1
D0
0E
U6
74HC574
Q7
Q5
D5
D7
Q4
Q3
Q2
Q1
Q0
D4
D3
D2
D1
D0
0E
D06
D07
D08
D09
D10
D11
D12
D13
D05
D04
D03
D02
D01
D00
C6
15pF
R21
1k
12
13
14
15
16
17
18
19
12
13
14
15
16
17
18
19
C1
22F
10V
U5
74HC574
U7F
B13
B04
B05
B03
B02
B01
4
11
D14
SS12
B00
B12
EXT/INT
VOUT
TAB GND
VIN
U1
LT1175-5
SUPPLY SELECT
DUAL
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
B[00:13]
B13
VIN
J1
7V TO
15V
C15
0.1F
DATA READY
74HC244
U8E
74HC244
1
9
DGND
AGND
VSS
BUSY
VDD
SER/PAR
SHDN
RD
CONVST
CS
74HC244
C5
10F
16V
U4
LTC1418
REFCOMP
VREF
AIN
+AIN
JP6
14
27
26
28
21
22
23
24
25
C10
10F
10V
C7
0.1F
VLOGIC
19
R20
19k
VLOGIC VLOGIC
C9
10F
16V
C3
VSS
0.1F
U3
LT1363
2 7
6
3 +
8
1
4
V
V+
VOUT
JP7
C2
22F
10V
JP3
VCC
VLOGIC
CLK
A+
AGND
J2
J4
GND
+VIN
U2
11
HC14
U7D
HC14
U7E
D[00:13]
10
D13
RDY
D13
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
D13
D12
D11
J6-12
J6-11
J6-14
DGND
HEADER
18-PIN
DGND
J6-18
RDY
D13
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
J6-17
J6-16
J6-15
J6-2
J6-1
J6-4
J6-3
J6-6
J6-5
J6-8
J6-7
J6-10
J6-9
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D10
J6-13
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0, 1k
1418 F12a
JP1
LED
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
U
U
W
J3
7V TO
15V
APPLICATIONS INFORMATION
U
VCC
LTC1418
15
LTC1418
U
APPLICATIONS INFORMATION
1418 F12b
Figure 12b. Suggested Evaluation Circuit Board Component Side Top Silkscreen
1418 F12c
16
LTC1418
APPLICATIONS INFORMATION
1418 F12d
Internal Clock
The ADC has an internal clock. In parallel output mode the
internal clock is always used as the conversion clock. In
serial output mode either the internal clock or an external
clock may be used as the conversion clock (see Figure 20).
The internal clock is factory trimmed to achieve a typical
conversion time of 3.4s and a maximum conversion time
over the full operating temperature range of 4s. No external adjustments are required, and with the guaranteed maximum acquisition time of 1s, throughput performance of
200ksps is assured.
Power Shutdown
The LTC1418 provides two power shutdown modes, nap
and sleep, to save power during inactive periods. The nap
mode reduces the power by 80% and leaves only the
digital logic and reference powered up. The wake-up time
from nap to active is 500ns (see Figure 13a). In sleep
mode all bias currents are shut down and only leakage
current remains about 2A. Wake-up time from sleep
17
LTC1418
U
APPLICATIONS INFORMATION
mode is much slower since the reference circuit must
power up and settle to 0.005% for full 14-bit accuracy.
Sleep mode wake-up time is dependent on the value of
the capacitor connected to the REFCOMP (Pin 4). The
wake-up time is 30ms with the recommended 10F
capacitor. Shutdown is controlled by Pin 22 (SHDN); the
ADC is in shutdown when it is low. The shutdown mode
is selected with Pin 25 (CS); low selects nap (see Figure
13b), high selects sleep.
SHDN
t4
CONVST
1418 F13a
CS
t2
CONVST
t1
RD
1418 F14
CS
t3
SHDN
1418 F13b
Conversion Control
Conversion start is controlled by the CS and CONVST
inputs. A falling edge of CONVST pin will start a conversion
after the ADC has been selected (i.e., CS is low, see Figure
14). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the
BUSY output. BUSY is low during a conversion.
Data Output
The data format is controlled by the SER/PAR input pin;
logic low selects parallel output format. In parallel mode
the 14-bit data output word D0 to D13 is updated at the end
of each conversion on Pins 6 to 13 and Pins 15 to 20. A
logic high applied to SER/PAR selects the serial formatted
data output and Pins 16 to 20 assume their serial function,
Pins 6 to 13 and 15 are in the Hi-Z state. In either parallel
18
LTC1418
U
APPLICATIONS INFORMATION
CS = RD = 0
tCONV
(SAMPLE N)
t5
CONVST
t6
t8
BUSY
t7
DATA
DATA (N 1)
DB13 TO DB0
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
1418 F15
Figure 15. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
CS = RD = 0
t13
tCONV
t5
CONVST
t8
t6
t6
BUSY
t7
DATA
DATA (N 1)
DB13 TO DB0
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
1418 F16
Figure 16. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
CS = 0
t12
(SAMPLE N)
tCONV
t5
t8
CONVST
t6
BUSY
t9
t12
t11
RD
t 10
DATA
DATA N
DB13 TO DB0
1418 F17
19
LTC1418
APPLICATIONS INFORMATION
CS = 0
(SAMPLE N)
t8
tCONV
RD = CONVST
t6
t11
BUSY
t10
t7
DATA (N 1)
DB13 TO DB0
DATA
DATA N
DB13 TO DB0
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
1418 F18
tCONV
t8
(SAMPLE N)
RD = CONVST
t6
t11
BUSY
t10
DATA
DATA N
DB13 TO DB0
DATA (N 1)
DB13 TO DB0
1418 F19
20
LTC1418
U
APPLICATIONS INFORMATION
DATA
IN
14
CLOCK
INPUT
SHIFT
REGISTER
23
DATA
OUT
25
THREE
STATE
BUFFER
SAR
17
19
SCLK*
RD
CS
DOUT*
18
EOC
16
20
CLKOUT*
EXTCLKIN*
EXT/INT*
INTERNAL
CLOCK
26
*PINS 16 TO 20 ARE LABELED WITH THEIR SERIAL FUNCTIONS
BUSY
1418 F20
Figure 20. Functional Block Diagram for Serial Mode (SER/PAR = High)
21
LTC1418
U
APPLICATIONS INFORMATION
two zeros. The MSB (D13) will be valid on the first rising
and the first falling edge of the SCLK. D12 will be valid on
the second rising and the second falling edge as will all
the remaining bits. The data may be captured on either
edge. The largest hold time margin is achieved if data is
captured on the rising edge of SCLK.
SCLK
VIL
t14
t15
VOH
DOUT
VOL
1418 F21
CONVST
24
CONVST
BUSY
RD
SCLK
BUSY (= RD)
26
23
LTC1418
CLKOUT
DOUT
EXT/INT
P OR DSP
(CONFIGURED
AS SLAVE)
OR
SHIFT
REGISTER
17
18
CLKOUT ( = SCLK)
19
DOUT
20
1418 F22a
CS
25
(SAMPLE N)
t5
CS = EXT/INT = 0
(SAMPLE N + 1)
CONVST
t13
t6
t8
HOLD
BUSY (= RD)
SAMPLE
HOLD
t10
1
D13
D12
D11
D10
D9
D8
D7
D6
D5
10
11
12
13
14
15
16
D13
D12
D11
CLKOUT (= SCLK)
t7
DOUT
Hi-Z
D4
D3
D2
D1
D0
FILL
ZEROS
D13
Hi-Z
DATA (N 1)
tCONV
DATA N
t11
CLKOUT
(= SCLK)
VIL
t14
t15
DOUT
D13
D12
CAPTURE ON
RISING CLOCK
D11
VOH
VOL
CAPTURE ON
FALLING CLOCK
Figure 22. Internal Conversion Clock Selected. Data Transferred During Conversion Using
the ADC Clock Output as a Master Shift Clock (SCLK Driven from CLKOUT)
22
1418 F22b
LTC1418
APPLICATIONS INFORMATION
serial port after transferring the serial output data by
tying it to the RD pin.
clock and the SCLK. The internal clock has been optimized
for the fastest conversion time, consequently this mode
can provide the best overall speed performance. To select
an internal conversion clock, tie EXT/INT (Pin 20) low. The
internal clock appears on CLKOUT (Pin 18) which can be
tied to SCLK (Pin 17) to supply the SCLK.
CONVST
24
CONVST
BUSY
RD
EXTCLKIN
BUSY (= RD)
26
23
16 EXTCLKIN ( = SCLK)
P OR DSP
LTC1418
SCLK
DOUT
EXT/INT
17
DOUT
19
20
5V
1418 F23a
CS
25
(SAMPLE N)
t5
CS = 0, EXT/INT = 5
(SAMPLE N + 1)
CONVST
t13
t6
t8
HOLD
BUSY (= RD)
SAMPLE
HOLD
tdEXTCLKIN
1
D13
D12
D11
D10
D9
D8
D7
D6
D5
10
11
12
13
14
15
16
D13
D12
D11
EXTCLKIN (= SCLK)
t10
DOUT
Hi-Z
t7
D4
D3
D2
D1
D0
FILL
ZEROS
D13
Hi-Z
DATA (N 1)
tCONV
DATA N
t11
EXTCLKIN
(= SCLK)
1418 F23b
tLEXTCLKIN
VIL
tHEXTCLKIN
t14
t15
DOUT
D13
D12
CAPTURE ON
RISING CLOCK
D11
VOH
VOL
CAPTURE ON
FALLING CLOCK
Figure 23. External Conversion Clock Selected. Data Transferred During Conversion Using
the External Clock (External Clock Drives Both EXTCLKIN and SCLK)
23
LTC1418
U
APPLICATIONS INFORMATION
clock to EXTCLKIN. The same clock is also applied to SCLK
to provide a data shift clock. To maintain accuracy the
conversion clock frequency must be between 30kHz and
4.5MHz.
It is not recommended to clock data with an external clock
during a conversion that is running on an internal clock
because the asynchronous clocks may create noise.
CONVST
24
CONVST
BUSY
RD
SCLK
26
INT
23
C0
17
SCK
P OR DSP
LTC1418
DOUT
EXT/INT
19
MISO
20
1418 F24a
CS
25
t5
CS = EXT/INT = 0
CONVST
t13
t6
t8
SAMPLE
HOLD
BUSY
t9
RD
1
9 10 11 12 13 14 15 16
D13 12 11 10 9
SCLK
t10
Hi-Z
DOUT
t11
4
FILL
ZEROS
Hi-Z
(SAMPLE N)
tCONV
DATA N
1418 F24b
t LSCLK
SCLK
VIL
t HSCLK
t14
t15
DOUT
D13
D12
CAPTURE ON
RISING CLOCK
Figure 24. Internal Conversion Clock Selected. Data Transferred After Conversion
Using an External SCLK. BUSY Indicates End of Conversion
24
D11
CAPTURE ON
FALLING CLOCK
VOH
VOL
LTC1418
U
APPLICATIONS INFORMATION
also allows operation when the SCLK frequency is very low
(less than 30kHz). To select the internal conversion clock
tie EXT/INT low. The external SCLK is applied to SCLK. RD
can be used to gate the external SCLK, such that data will
clock only after RD goes low and to three-state DOUT after
data transfer. If more than 16 SCLKs are provided, more
zeros will be filled in after the data word indefinitely.
CONVST
24
16
CONVST EXTCLKIN
BUSY
CLKOUT
26
INT
23
RD
C0
P OR DSP
LTC1418
17
SCLK
DOUT
EXT/INT
SCK
19
20
MISO
5V
1418 F25a
CS
25
CS = 0, EXT/INT = 5
tdEXTCLKIN 1
9 10 11 12 13 14 15 16
EXTCLKIN
t5
t7
CONVST
t13
t6
t8
SAMPLE
HOLD
BUSY
t9
RD
1
9 10 11 12 13 14 15 16
SCLK
t10
Hi-Z
DOUT
t11
D13 12 11 10 9
FILL
ZEROS
Hi-Z
(SAMPLE N)
tCONV
DATA N
1418 F25b
t LSCLK
SCLK
VIL
t HSCLK
t14
t15
DOUT
D12
D13
CAPTURE ON
RISING CLOCK
D11
VOH
VOL
CAPTURE ON
FALLING CLOCK
Figure 25. External Conversion Clock Selected. Data Transferred After Conversion
Using an External SCLK. BUSY Indicates End of Conversion
25
LTC1418
U
APPLICATIONS INFORMATION
allows the user to synchronize the A/D conversion to an
external clock either to have precise control of the internal
bit test timing or to provide a precise conversion time. As in
Figure 24, this mode works when the SCLK frequency is
very low (less than 30kHz). However, the external conversion clock must be between 30kHz and 4.5MHz to maintain
PACKAGE DESCRIPTION
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.397 0.407*
(10.07 10.33)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
0.301 0.311
(7.65 7.90)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.205 0.212**
(5.20 5.38)
0.068 0.078
(1.73 1.99)
0 8
0.005 0.009
(0.13 0.22)
0.022 0.037
(0.55 0.95)
26
0.0256
(0.65)
BSC
0.010 0.015
(0.25 0.38)
0.002 0.008
(0.05 0.21)
LTC1418
U
PACKAGE DESCRIPTION
N Package
28-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
1.370*
(34.789)
MAX
28
27
26
25
24
23
22
21
20
19
18
17
16
15
10
11
12
13
14
0.255 0.015*
(6.477 0.381)
0.300 0.325
(7.620 8.255)
0.130 0.005
(3.302 0.127)
0.045 0.065
(1.143 1.651)
0.020
(0.508)
MIN
0.009 0.015
(0.229 0.381)
+0.035
0.325 0.015
8.255
+0.889
0.381
0.125
(3.175)
MIN
0.065
(1.651)
TYP
0.005
(0.127)
MIN
0.100 0.010
(2.540 0.254)
0.018 0.003
(0.457 0.076)
N28 1197
27
LTC1418
U
TYPICAL APPLICATION
Single 5V Supply, 200kHz, 14-Bit Sampling A/D Converter
VREF
OUTPUT
2.5V
1F
LTC1418
DIFFERENTIAL 1
+
VDD
ANALOG INPUT 2 AIN
(0V TO 4.096V)
AIN
VSS
3
VREF
BUSY
4
REFCOMP
CS
5
10F
AGND
CONVST
6
D13(MSB)
RD
7
D12
SHDN
8
D11
SER/PAR
9
D10
(EXT/INT)D0
10
D9
(DOUT)D1
11
D8
(CLKOUT)D2
14-BIT
12
PARALLEL
D7
(SCLK)D3
BUS
13
D6
(EXTCLKIN )D4
14
DGND
D5
5V
28
27
10F
26
1N5817*
25
24
23
P CONTROL
LINES
22
21
20
19
18
17
16
15
1418 TA03
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1274/LTC1277
LTC1412
LTC1415
LTC1416
LTC1419
LTC1604
LTC1605
LTC1595
LTC1596
ADCs
DACs
Reference
LT1019-2.5
28