Professional Documents
Culture Documents
Dinesh Sharma
Microelectronics Group, EE Department
IIT Bombay, Mumbai
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I
d
v
o
v
i
Vg
V
d
Id
I
dVg + d dVd
Vg
Vd
Id
= gm (Transconductance)
Vg
Id
= go (O/P conductance)
Vd
gm
vo
=
= gm ro
vi
go
Transistor Characteristics
gm and go depend on the transistor characteristics.
In saturation,
K
Id (Vgs VT )2
2
where, K is the conductivity factor given by:
W
W
K =K
Cox
L
L
VT is the threshold voltage
W and L are transistor width and length respectively.
is the mobility
and Cox is the gate oxide capacitance per unit area.
Transconductance
Let VGT (Vgs VT )
2
KVGT
Then Id =
2
2Id
VGT =
K
W
I
VGT
gm = d = KVGT = K
Vg
L
s
r
p
W
2Id
Also gm = KVGT = K
= 2KId = 2K
Id
K
L
Similarly, K =
2Id
VGT
and
; Therefore gm =
2Id
VGT
VGT =
2Id
VGT
Which formula?
W
L
To increase gm
should we increase VGT ?
s
or decrease it?
W
Is gm linearly dependent on
gm = 2K
Id
L
transistor size?
dependent on its square root?
2I
gm = d
or is it independent of transistor
VGT
size?
In fact, which formula should be applied depends on how the
transistor is biased and sized. If size and VGT are known, the
first formula applies. If the drain current and size are known, the
second one does. If gate voltage and drain current are given
and the transistor is accordingly sized, the third formula should
be used.
gm = K
VGT
Which formula?
W
L
To increase gm
should we increase VGT ?
s
or decrease it?
W
Is gm linearly dependent on
gm = 2K
Id
L
transistor size?
dependent on its square root?
2I
gm = d
or is it independent of transistor
VGT
size?
In fact, which formula should be applied depends on how the
transistor is biased and sized. If size and VGT are known, the
first formula applies. If the drain current and size are known, the
second one does. If gate voltage and drain current are given
and the transistor is accordingly sized, the third formula should
be used.
gm = K
VGT
Which formula?
W
L
To increase gm
should we increase VGT ?
s
or decrease it?
W
Is gm linearly dependent on
Id
gm = 2K
L
transistor size?
dependent on its square root?
2I
gm = d
or is it independent of transistor
VGT
size?
In fact, which formula should be applied depends on how the
transistor is biased and sized. If size and VGT are known, the
first formula applies. If the drain current and size are known, the
second one does. If gate voltage and drain current are given
and the transistor is accordingly sized, the third formula should
be used.
gm = K
VGT
Which formula?
W
L
To increase gm
should we increase VGT ?
s
or decrease it?
W
Is gm linearly dependent on
gm = 2K
Id
L
transistor size?
dependent on its square root?
2I
gm = d
or is it independent of transistor
VGT
size?
In fact, which formula should be applied depends on how the
transistor is biased and sized. If size and VGT are known, the
first formula applies. If the drain current and size are known, the
second one does. If gate voltage and drain current are given
and the transistor is accordingly sized, the third formula should
be used.
gm = K
VGT
Which formula?
W
L
To increase gm
should we increase VGT ?
s
or decrease it?
W
Is gm linearly dependent on
Id
gm = 2K
L
transistor size?
dependent on its square root?
2I
gm = d
or is it independent of transistor
VGT
size?
In fact, which formula should be applied depends on how the
transistor is biased and sized. If size and VGT are known, the
first formula applies. If the drain current and size are known, the
second one does. If gate voltage and drain current are given
and the transistor is accordingly sized, the third formula should
be used.
gm = K
VGT
Which formula?
W
L
To increase gm
should we increase VGT ?
s
or decrease it?
W
Is gm linearly dependent on
Id
gm = 2K
L
transistor size?
dependent on its square root?
2I
gm = d
or is it independent of transistor
VGT
size?
In fact, which formula should be applied depends on how the
transistor is biased and sized. If size and VGT are known, the
first formula applies. If the drain current and size are known, the
second one does. If gate voltage and drain current are given
and the transistor is accordingly sized, the third formula should
be used.
gm = K
VGT
Which formula?
W
L
To increase gm
should we increase VGT ?
s
or decrease it?
W
Is gm linearly dependent on
gm = 2K
Id
L
transistor size?
dependent on its square root?
2I
gm = d
or is it independent of transistor
VGT
size?
In fact, which formula should be applied depends on how the
transistor is biased and sized. If size and VGT are known, the
first formula applies. If the drain current and size are known, the
second one does. If gate voltage and drain current are given
and the transistor is accordingly sized, the third formula should
be used.
gm = K
VGT
Which formula?
W
L
To increase gm
should we increase VGT ?
s
or decrease it?
W
Is gm linearly dependent on
gm = 2K
Id
L
transistor size?
dependent on its square root?
2I
gm = d
or is it independent of transistor
VGT
size?
In fact, which formula should be applied depends on how the
transistor is biased and sized. If size and VGT are known, the
first formula applies. If the drain current and size are known, the
second one does. If gate voltage and drain current are given
and the transistor is accordingly sized, the third formula should
be used.
gm = K
VGT
Output conductance
Assuming a simple Early effect like model, we can write for go :
go Id /L
where L is the channel length and is a technology dependent
parameter. In terms of geometry and VGT , we can write:
go =
K W 2
V
2 L2 GT
VGT
VA
2
Voltage Gain
The voltage gain in terms of geometry and VGT :
Ao =
2L
V
GT
Id
Thus, if the transistor is biased at constant current, the DC gain
is determined by the square root of the gate area.
AC Behaviour
Cgd
vo
G
vi Cg
S
gm vi
ro
D
Co
S
vo
sCo vo = 0
ro
1
gm vo sCgd + + sCo = 0
ro
sCgd (vi vo ) gm vi
vi sCgd
So the AC gain A1 =
1 sCgd /gm
vo
= gm ro
vi
1 + sro (cgd + co )
Bandwidth
A1 = gm ro
1 sCgd /gm
1 + sro (cgd + co )
1 sCgd /gm
1 + sro Ctot
Ao
1 + sro Ctot
Gain (db)
Ao
A - 3db
o
0 db
BW
GBW
Frequency
GBW = gm ro
1
gm
=
ro Ctot
Ctot
Maximum GBW
GBW is max. when there is no load connected and the load is
entirely due to the device capacitance itself. Then the load
capacitance is proportional to the device width.
Ctot = W where is a technological parameter.
GBWmax =
GBWmax
=
=
=
gm
W
K VGT
L
r
1 2K Id
WL
2Id
WVGT
Summary
K WL VGT
go
2
K WVGT
2
2L
Ao
2L
VGT
GBW
GBW max
K WVGT
LCtot
K VGT
L
2K W
L Id
Id
qL
2K WL
Id
2K WId 1
qL Ctot
2K Id
1
WL
2Id
VGT
Id
L
2L
VGT
2Id
VGT Ctot
K VGT
L
Technological Constraint
Ao GBWmax
K VGT
1
2L
=
=
VGT
L
So Ao GBWmax =
2K WL 1
Id
2K Id
WL
2K
Cascode Amplifier
ref
Vg2
Vg1
v in
v out
So gmeq =
Id
with dVd2 = 0
Vg1
and goeq =
Id
with dVg1 = 0
Vd2
M2
V
d1
M1
Equivalent gm of Cascode
Id
Vg1
= dVd1 ,
gmeq =
I
dVds2
V
d2
V
ref
Vg2
Vg1
v in
v out
M2
M1
dVgs2 = dVd1
id
id
So vd1
V
d1
with dVd2 = 0
id
gmeq =
id
gm2 + go2
= gm1
gm1
vg1
go1 + go2 + gm2
Equivalent go of Cascode
goeq =
dVgs1 = 0,
I
d
V
d2
ref
Vg2
Vg1
v in
Id
Vd2
dVgs2 = dVd1 ,
dVds2 = dVd2 dVd1
i
id = 0 + go1 vd1 ,
sovd1 = d
go1
v out
M2
V
d1
with dVg1 = 0
M1
gm2 + go2
+ go2 vd2
go1
id
go1 go2
=
vd2
go1 + go2 + gm2
go2
goeq go1
gm2
DC gain of Cascode
gmeq
gm1 (gm2 + go2 ) g01 + g02 + gm2
=
goeq
g01 + g02 + gm2
g01 g02
gm1 (gm2 + go2 )
gm1
gm2
So
Ao =
=
1+
g01 g02
g01
g02
gm1
common source gain
Let
A01
g01
gm2
And A02 1 +
common gate gain
g02
Ao =
Then,
Ao = A01 A02
AC Behaviour of Cascode
I
d
V
d2
ref
Vg2
Vg1
v in
v out
M2
vi
Cg1 gm1 vi
S
V
d1
M1
ro2
Cdg1
vx
vo
ro1
gm2 vx
Co
ro2
Cdg1
vx
vi
Cg1 gm1 vi
S
gm2 vx +
vx =
vo
ro1
gm2 vx
Co
vx vo
= sCo vo
ro2
1 + sro2 Co
1 + sro2 Co
vo =
vo
1 + gm2 ro2
A2
ro2
Cdg1
vx
vi
Cg1 gm1 vi
S
vo
ro1
gm2 vx
Co
vx
+ sCo vo
ro1
A1 A2
vo
=
vi
1 + sro1 Co (A2 + ro2 /ro1 )
ref
v in
Load capacitance = 1 pF
The two transistors in cascode
I
configuration have identical geometries
d
V
d2
v out
and the load is an ideal current source.
Vg2
M2
Assume the following technological
V
parameters:
d1
Vg1
Kn = 150A/V 2, VTn = 0.5V , VE = 20V
M1
Assume the supply voltage to be 3.3V.
Calculation of gm
The gain bandwidth product is given by
2 108 =
gm
C .
So,
gm1
gm
=
C
1012
So gm1 = 628.3S
Since the same current flows through the two transistors and
they have the same geometry, gm1 = gm2 , go1 = go2 .
Let A =
gm1
gm2
=
go1
go2
Therefore,
gm2
gm1
1+
2500 =
= A(A + 1)
go1
go2
This gives A 49.5.
49.5 =
628.3 106
go1
so go1 = 12.7S
Id
I
= d
VE
20
W
= 5.2, Id = 254A
L
Bias Voltages
1 W 2
Id = K VGT
2
L
d
V
d2
ref
Vg2
Vg1
v in
v out
M2
V
d1
M1
So VGT =
2 254
= .81V
150 5.2
DC level incompatibility
The output DC level of a cascode amplifier is higher than the
input DC level. This causes problems with direct connection to
the next stage, or with DC feed back to itself.
These problems can be reduced if we use
a complementary arrangement of n and p
channel transistors for cascoding.
The upper transistor of the cascode
arrangement can be thought of as a
source follower to its bias voltage, which
keeps the drain voltage of the lower
amplifier transistor (nearly) constant.
Can we use a p channel transistor as a
source follower?
Vdd
Load
Vbiasn
Vout
Vin
Gnd
Alternative Cascode
Vdd
M1
Gnd
M2
Vbiasp
Vout
Load
Folded Cascode
Vdd
Vbiasp1
M3
M2
Vin
M1
Gnd
Vbiasp2
Vout
Load
Io
M1
Vref
M2
K
(Vref VT )2
2
r
2Iref
K
If M2 is also saturated, Io = Iref
Therefore Vref = VT +
Vbiasp2
Vbiasn
Vin
Gnd
Vout
Vx
M1
Io
Io
M3
Vb
Vx
Vy
M1
Vref
M2
Vbiasp2
Vout
Vbiasn2
Vin
M1
Vbiasn1
Gnd
M2
Vbiasp2
Vout
Vbiasn2
Vin
M1
Vbiasn1
Gnd
Differential Amplifiers
Some definitions
It is more convenient to represent the two input voltages and
the two output voltages by their mean and difference values.
vid
vicm
vod
vocm
vi1 vi2
vi1 + vi2
2
vo1 vo2
vo1 + vo2
Acm
vod
vid
vocm
vicm
For a good diff amp, the differential gain should be high and
independent of input common mode voltage, whereas the
common mode gain should be as low as possible. The
common mode rejection ratio is:
CMRR 20 log
Adiff
dB
Acm
vi 2
vi 2
Vs
Is
Mp1
Mp2
i out
vi 1
Mn1
Mn2
Vs
Is
vi 2
Mp1
Mp2
i out
vi 1
Mn1
Mn2
Vs
vi 2
Is
Mp1
Mp3
Mp2
i out
vi 1
Mn1
Vbias
Mn2
Vs
vi 2
vout
Mn3
Mn4
v2
R1
C1
Output Stage
gm22 v2
v0
R2
C2
op-amp Compensation
Pole Splitting
Differential Stage
Cc
Output Stage
v2
R1
gm11 v1
v0
C1
gm22 v2
R2
C2
Miller Compensation
C
A1
A2
Slew rate
Miller compensation also sets the slew rate of the op amp.
For large signal input, the output current of the
Vdd
Mp3
Mp1
Mp2
OTA = tail current.
i out
vout
The effective load capacitance for this stage is
vi 1
Mn1 Mn2 vi 2
Vs
A2 C.
dV
Mn3
Mn4
Vbias
= I(Mn4)
A2 C
dt
Output of the OTA slews at a rate
I(Mn4)
A2 C .
I(Mn4)
C .
Design Equations-I
All transistors must be saturated
Vdd
Mp1
Mp3
Mp2
i out
vi 1
Mn1
Vbias
Mn2
Vs
vi 2
vout
Mn3
Mn4
I(Mn1) = I(Mn2) =
I(Mn1) = I(Mp1)
I(Mp1) = I(MP2)
I(Mn4)
2
(Series connection)
(Mirror)
Design Equations-II
Mp3 has the same Vs , Vg as Mp1.
Vdd
Mp1
Mp3
Mp2
i out
vi 1
Mn1
Vbias
Mn2
Vs
vi 2
vout
Mn3
Mn4
If
W /L(Mp3)
I(Mp3)
=
I(Mp1)
W /L(Mp1)
Design Equations-III
Vdd
Mp1
Mp3
Mp2
i out
vi 1
Mn1
Vbias
Mn2
Vs
vi 2
vout
GBW =
Mn3
Mn4
gm (Mn2)
C
Since the current as well as gm of Mn1 and Mn2 are now known
p
2K W /L(Mn2)I(Mn2)
gm (Mn2) =
W /L(Mn1) = W /L(Mn2)
Design Equations-IV
Currents through Mn2,Mp2, Mp3 and Mn3 are known
(go = Id /VA )
gm (Mn2)gm (Mp3)
(go (Mn2)||go (Mp2))(go (Mp3)||go (Mn3))
As gm for Mn2 and all go values are known, this determines the
gm for MP3.
Once we know the gm as well as the current for Mp3, we can
calculate its geometry.
Example Design-1
Vdd
Mp1
Mp3
Mp2
i out
vi 1
Mn1
Vbias
Mn2
Vs
vi 2
vout
Mn3
Mn4
20
106
= 40A
Example Design-2
Vdd
Mp1
Mp3
Mp2
i out
vi 1
Mn1
Vbias
Mn2
Vs
vi 2
vout
Mn3
Mn4
gm (Mn2)
2 1012
Example Design-3
Vdd
Mp1
Mp3
Mp2
i out
vi 1
Mn1
Vbias
Mn2
Vs
vi 2
vout
Mn3
Mn4
628 gm(Mp3)
2
20
Example Design-4
Vdd
Mp1
Mp3
Mp2
i out
vi 1
Mn1
Vbias
Mn2
Vs
vi 2
vout
Mn3
Mn4
Example Design-5
Vdd
Mp1
Mp3
Mp2
i out
vi 1
Mn1
Vbias
Mn2
Vs
vi 2
vout
Mn3
Mn4
Vdd
Vbiasp2
Vbiasp1
+
-
Vout
Vbiasn2
Vin +
Gnd
Vin -
Vbiasn1
Folded Cascode
The common mode voltage incompatibility of a telescopic
cascode can be solved by using a folded cascode.
Vdd
Vbiasp1
Vbiasp2
Vin +
Vin -
Vout
Vbiasn2
Vbiasn1
Gnd
Push-Pull Op Amp
Differential to single ended conversion can be done in the
output stage, by using a push-pull driver. The output loads in
the differential stage (Mp1 and Mp2) are diode connected.
Current through Mp2 is mirrored in
the output p transistor Mp4.
Vdd
Mp3
vi-
Mp1
Mp2
Mn1
Mn2
Mp4
vi+
Out
Vs
Mn3
Mn4
Vbias
Gnd
Mn5