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ECE 545
Lecture 5
dataflow
Concurrent
statements
structural
Components and
interconnects
behavioral
(sequential)
Sequential statements
Registers
State machines
Instruction decoders
Synthesizable VHDL
Todays Topic
Dataflow VHDL
Design Style
VHDL code
synthesizable
Combinational
Logic
Dataflow VHDL
Design Style
Combinational
Logic
VHDL code
synthesizable
Registers
Data-Flow VHDL
Data-flow VHDL
Concurrent Statements
Major instructions
Concurrent statements
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
x
y
cin
ENTITY fulladd IS
PORT ( x
: IN
y
: IN
cin
: IN
s
: OUT
cout : OUT
END fulladd ;
cout
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ) ;
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Logic Operators
Logic operators
and
or
nand
nor
xor
not
only in VHDL-93
or later
Highest
and
or
nand
not
nor
xnor
xor
xnor
Lowest
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12
No Implied Precedence
E.g.,
status <= '1';
even <= (p1 and p2) or (p3 and p4);
arith_out <= a + b + c - 1;
Wanted: y = ab + cd
Incorrect
y <= a and b or c and d ;
equivalent to
y <= ((a and b) or c) and d ;
equivalent to
y = (ab + c)d
Correct
y <= (a and b) or (c and d) ;
RTL Hardware Design
Chapter 4
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13
Data-flow VHDL
Major instructions
Chapter 4
Concurrent statements
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When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;
Value N
Value N-1
0
1
0
1
0
1
Value 2
Target Signal
Value 1
Condition N-1
Condition 2
Condition 1
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18
Chapter 4
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Chapter 4
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Chapter 4
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Chapter 4
22
Chapter 4
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E.g.,
E.g.,
Chapter 4
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E.g.,
Chapter 4
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Chapter 4
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Operators
Relational operators
/=
<
<=
>
>=
not
=
and
/=
or
<
nand
<=
nor
>
xor
27
>=
xnor
28
VHDL operators
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Data-flow VHDL
Major instructions
Concurrent statements
With Select-When
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32
expression1
choices_1
expression2
choices_2
expressionN
choices_N
WHEN value
WHEN value_1 | value_2 | .... | value N
WHEN OTHERS
target_signal
choice expression
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Syntax
Simplified syntax:
Chapter 4
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35
select_expression
Discrete type or 1-D array
With finite possible values
choice_i
A value of the data type
Choices must be
mutually exclusive
all inclusive
others can be used as last choice_i
Chapter 4
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Chapter 4
38
Chapter 4
39
Chapter 4
40
Chapter 4
42
Chapter 4
41
Chapter 4
43
Chapter 4
44
Conceptual implementation
select_expression is with a data type of 5
values: c0, c1, c2, c3, c4
Achieved by a
multiplexing circuit
Abstract (k+1)-to-1
multiplexer
sel is with a data type
of (k+1) values:
c0, c1, c2, . . . , ck
Chapter 4
45
Chapter 4
46
Chapter 4
48
E.g.,
Chapter 4
47
Chapter 4
49
Chapter 4
50
Comparison
Selected signal assignment:
good match for a circuit described by a
functional table
E.g., binary decoder, multiplexer
Less effective when an input pattern is given a
preferential treatment
Chapter 4
51
Chapter 4
Chapter 4
52
53
Chapter 4
54
A1
MUX_0
MUX_4_1
NEG_A
MLU Example
MUX_1
MUX_2
Y1
IN0
IN1
IN2
OUTPUT
SEL0
IN3
SEL1
NEG_Y
0
B1
L1 L0
MUX_3
NEG_B
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ENTITY mlu IS
PORT(
NEG_A : IN STD_LOGIC;
NEG_B : IN STD_LOGIC;
NEG_Y : IN STD_LOGIC;
A:
IN STD_LOGIC;
B:
IN STD_LOGIC;
L1 :
IN STD_LOGIC;
L0 :
IN STD_LOGIC;
Y:
OUT STD_LOGIC
);
END mlu;
A1 : STD_LOGIC;
B1 : STD_LOGIC;
Y1 : STD_LOGIC;
MUX_0 : STD_LOGIC;
MUX_1 : STD_LOGIC;
MUX_2 : STD_LOGIC;
MUX_3 : STD_LOGIC;
L: STD_LOGIC_VECTOR(1 DOWNTO 0);
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AND B1;
OR B1;
XOR B1;
XNOR B1;
WHEN "00",
WHEN "01",
WHEN "10",
WHEN OTHERS;
END mlu_dataflow;
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10
Signals
SIGNAL a : STD_LOGIC;
a
1
wire
b
bus
61
62
Splitting buses
a
4
10
10
5
c
SIGNAL
SIGNAL
SIGNAL
SIGNAL
b
c
a:
b:
c:
d:
SIGNAL
SIGNAL
SIGNAL
SIGNAL
a:
b:
c:
d:
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64
A
A>>1
AshiftR
0
AshiftR <=
ECE 448 FPGA and ASIC Design with VHDL
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11
Buffers
A
A<<<1
ArotL
A(2) A(1) A(0) A(3)
ArotL <=
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Tri-state Buffer
e
x
f
e=0
0
0
1
1
0
1
0
1
Z
Z
0
1
e=1
x
69
70
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY tri_state IS
PORT ( ena: IN STD_LOGIC;
input: IN STD_LOGIC;
output: OUT STD_LOGIC
);
END tri_state;
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72
12
2-to-1 Multiplexer
s
f
s
w
Multiplexers
0
1
73
74
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
w
ENTITY mux2to1 IS
PORT ( w0, w1, s : IN
STD_LOGIC ;
f
: OUT STD_LOGIC ) ;
END mux2to1 ;
3
2
0
0
1
y
1
s2
s1
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76
4-to-1 Multiplexer
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
s
ENTITY mux_cascade IS
PORT ( w1, w2, w3: IN STD_LOGIC ;
s1, s2
: IN STD_LOGIC ;
f
: OUT STD_LOGIC ) ;
END mux_cascade ;
w
w
w
w
00
01
10
11
77
0
1
2
3
78
13
: IN
: IN
: OUT
STD_LOGIC ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ) ;
Decoders
79
2-to-4 Decoder
80
En w w
1 0
ENTITY dec2to4 IS
PORT ( w : IN
En : IN
y
: OUT
END dec2to4 ;
0
w
1
w
0
y
y
y
En
3
2
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
1
0
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Priority Encoder
w0
y0
w1
y1
w2
w3
Encoders
w3 w 2 w 1 w0
0
0
0
0
1
ECE 448 FPGA and ASIC Design with VHDL
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0
0
0
1
x
0
0
1
x
x
0
1
x
x
x
y 1 y0
d
0
0
1
1
0
1
1
1
1
d
0
1
0
1
84
14
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ) ;
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