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is
(A) 10010111102
(B) 01101000012
(C) 10011111102
(D) 11110111112
3. Conversion of binary number 10100002 to an octal number is
(A) 1198
(B)1018
(C) 1118
(D) 1208
4. Conversion of hexadecimal number 6B2 16to its binary number equivalent
is
(A)
11110001101112
(B) 0110101100102
(C) 01100110011112
(D) 111111112
5. In Boolean expression A+BC equals
(A)(A+B)(A+C)
(B) (A'+B)(A'+C)
(C)(A+B)(A'+C)
(D) (A+B)C
(A) (1111)
(B) (1100)
(C) (1000)
(D) None of these
7. The negative numbers in the binary system can be represented by
(A) Sign magnitude
(B) I's complement
(C) 2's complement
(D) All of the above
8. Excess-3 equivalent representation of hexadecimal (1234) is
(A) (1237)
(B) (4567)
(C) (7993)
(D) (4663)
9. Minimum no. of NAND gate required to implement a Ex-OR function is
(A)2
(B)3
(C)4
(D)5
10. Synchronous means _______
(A) At irregular intervals
(B) At same time
(C) At variable time
(D) None of these
11. The NAND gate output will be low if the two inputs are
(A) 00
(B) 01
(C) 10
(D) 11
12. The Gray code for decimal number 6 is equivalent to
(A) 1100
(B) 1001
(C) 0101
(D) 0110
13. The digital logic family which has minimum power dissipation is
(A) TTL
(B) RTL
(C) DTL
(D) CMOS
14. The output of a logic gate is 1 when all its inputs are at logic 0. the gate
is either
(A) a NAND or an EX-OR
(B) an OR or an EX-NOR
(C) an AND or an EX-OR
(D) a NOR or an EX-NOR
18. The code where all successive numbers differ from their preceding
number by single bit is
(A) Binary code.
(B) BCD.
(C) Excess 3.
(D) Gray.
19. How many AND gates are required to realize Y = CD+EF+G
(A) 4
(B) 5
(C) 3
(D) 2
20. In a positive logic system, logic state 1 corresponds to
(A) positive voltage
22. A universal logic gate is one, which can be used to generate any logic
function. Which of
the following is a universal logic gate?
(A) OR
(B) AND
(C) XOR
(D) NAND
23. A full adder logic circuit will have
(A) Two inputs and one output.
(B) Three inputs and three outputs.
(C) Two inputs and two outputs.
(D) Three inputs and two outputs
(C)AND gate
(D) X-OR gate
(E)
(F)
(A)1
(B)2
(C)3
(D) 4
(E)
(F)
(A)8
(B)16
(C)
(D)
32
64
108.
below:
29. Derive the Boolean expression for the logic circuit shown
109.
(A)
110.
111.
112.
113.
(B)
(C)
(D) ABCDE
a.
b.
c. 30. From the truth table below, determine the standard SOP
expression.
d.
(A)X = ABC + ABC + ABC
(B)X = ABC + ABC + ABC
(C)X = ABC + ABC + ABC
(D)
X = ABC + ABC + ABC
e.
f.
g.h.
i.
j.
k.l.
m.
n. 31. Applying DeMorgan's theorem to the expression
________.
, we get
(A)
A + B + C
(B)(A+B+C)
(C)A + B +CC
(D)
A(B+C)
o.
p.
q.
r.
s.
t.
u.
114.
32. The inverter can be produced with how many NAND gates?
(A)
(B)2
(C)3
(D)
(E)
4
33. Each term in the standard SOP form is called
(A)
Minterm
(B)Maxterm
(C)Dont care
(D)
Literal
115.
(A)2
(B)
(C)(C) 4
(D)
(D)
(E)