Reliability Study of Mounting Structure for High Temperature Power SemiconductorDeviceChip

using High Purity Aluminum

Masanori Yamagiwa1,2, Qiang Yu1, Masato Fujita1, Masanori Shinohara1, Yoshinori Murakami2
1
Department of Mechanical Engineering and Materials Science, Yokohama National University,
Tokiwadai 79-5, Hodogaya-ku, Yokohama-shi, Kanagawa 240-8501, Japan
Phone: +81-45-339-3867 FAX: +81-45-331-6593
2
Electric Propulsion Laboratory, Nissan Research Center, Nissan Motor CO., LTD.
1-1, Morinosatoaoyama, Atsugi-shi, Kanagawa 243-0123, Japan
Phone: +81-46-290-0894 FAX: +81-46-290-0857
Email: m-yamagiwa@mail.nissan.co.jp

ABSTRACT
We propose a new concept of mounting structure for hightemperature operable power semiconductor devices such as
Silicon Carbide (SiC) or Gallium Nitride (GaN) with high
reliability. The proposed structure is composed by high purity
aluminum (Al) as a circuit metal on substrate and hightemperature resistant joint material as a chip joint layer. In this
structure, the circuit metal can deform easily instead of the
joint layer, which is usually hard, by the stress caused by
Coefficient of Thermal Expansion (CTE) mismatches between
the chip and substrate. So, the structure leads Al as the circuit
metal to fulfill the function of reducing stress on the chip in
the advanced SiC Power Module instead of a solder joint layer
used in the conventional Power Module. We also expect that
Al has a possibility to endure the intense thermal cycling tests
such as -50/+300C range.
In order to demonstrate this new concept based on above
mentioned hypothesis, mechanical material tests and Finite
Element Analysis (FEA) were executed. From the test results,
it became clear that the plastic behavior (stress-strain
properties) of Al is similar to that of a tin-based solder alloy
comparatively. By using these data, the FEA simulating the
intense thermal cycles at several structures was carried out to
evaluate the stress on the chip and the inelastic strain on Al.
The calculated stress suggested that such a high stress causing
cracks on the chip is not generated on a structure which is
composed by Al with a ceramic substrate, even though a
displacement caused by CTE mismatch between the chip and
substrate is increased by expanded temperature range.
Continuously, in order to estimate fatigue life of the each
structure against the thermal cycles, mechanical fatigue tests
were carried out by using specimens with a notch for strain
concentration. From the test results, the low cycle fatigue
property of Al was obtained. By that property and the value of
inelastic strain calculated by the FEA, it was expected the
proposed structure has a high potential to secure sufficient
reliability at the high-temperature operable chip joint.
Furthermore, additional tensile tests using three kinds of Al
were carried out to investigate influence by purity of Al. In the
results, it was suggested that an application of 99.99% Al on
the proposed structure brings the best solution to reduce the
stress and to secure reliability at the chip joint compared with
99.5% Al or 99.7% Al.

978-1-4244-1701-8/08/$25.00 2008 IEEE.

KEY WORDS:  Reliability, Mounting Structure, Hightemperature, High Purity Aluminum, SiC, Power Module,
Mechanical Property, FEA, Fatigue Life Cycle
INTRODUCTION
Recently, the development of Hybrid Electric Vehicles
(HEVs), Fuel Cell Vehicles (FCVs) and Electric Vehicles
(EVs) has greatly increased. And the Power Modules used on
them are required size, weight and eventually cost reduction.
In order to meet these requirements, wide-bandgap
semiconductor devices such as SiC or GaN are attractive
proposition as the next generation of power chips, because
they offer the potential for decreasing power loss and
operating at high temperature. So, the higher temperature
operation promises a dramatic reduction in volume and weight
of the Power Module according with chip shrink and radiator
simplification [1].
The existing solder joint layer applied in the general Power
Modules has two functions. The first function is to keep
thermal and electrical conductions between the chip and
substrate. The second function is to keep the stress reduction
caused by CTE mismatches between the chip and substrate.
The second function also works to secure reliability at the chip
joint against thermal cycling. However, the existing solder can
not be used as a joint material for a high-temperature operable
chip such as SiC or GaN. Regarding this matter, some recent
studies have reported certain joint materials with a higher
melting point than the existing solder. However, these
materials suffer from poor ductility related with fatigue
properties [2,3]. Thus, it still needs more consideration to
secure reliability at the chip joint against the intense thermal
cycling tests such as -50/+300C range.
For this reliability problem, we propose a new chip mounting
structure which fulfills the second function by a circuit metal
on the substrate instead of the joint material. We are
considering a chip mounting structure using high purity
aluminum (Al), which can deform easily by low stress, as a
circuit metal instead of cupper (Cu), which is generally used,
and using a high-temperature resistant joint material, which
has higher yield stress than Al. Consequently, it is expected
that the stress on the chip can be reduced by Al deformation
because Al can adapt to the displacement caused by CTE
mismatch between the chip and substrate instead of the joint
layer.

906

M 12
I

R5

30
15

40

15

(82)
JIS G 0567 I-6

Fig.1 Al specimen for mechanical strength tests

30
99.99% Al
Sn3Ag0.5Cu

20

10

0
-100

100
200
300
400
Temperature [C]
Fig.2 0.2% Proof Stress of 99.99% Al and solder at
each temperature

20 C
60 C
140 C
220 C
300 C
Solder(40 C)

1.E-04
Minimum Creep Strain Rate
/s

MECHANICALPROPERTIES OF
HIGH PURITY ALUMINUM
For the FEA, nonlinear properties of 99.99% Al are required.
The tensile and creep tests of 99.99% Al were carried out to
clarify the plastic behavior (stress-strain properties) and creep
behavior (creep properties) with temperature dependences at 20, 60, 140, 220, and 300C. The shape of specimens for the
tests is based on Japanese Industrial Standards (JIS) shown in
Fig.1. They were annealed at 345C for 3 hours to remove
strain induced by mechanical shaping process. The tensile
tests were conducted on 2% strain rate and the creep tests were
conducted between 2MPa and 51Mpa at each temperature.
The results of creep tests were evaluated based on Norton
creep law to use as material data in the nonlinear FEA.
The Stress-Strain curves of 99.99% Al were measured at each
temperature from tensile tests. The value of 0.2% Proof Stress
defined from these curves. It is shown in Fig.2 with that of the
tin-based solder (Sn3Ag0.5Cu) for comparison [5]. Fig.2
clarifies that the value of 0.2% Proof Stress of 99.99% Al
lowers with temperature rising. It is also showing 99.99% Al
has similar characteristics to that of the solder. It indicates a
possibility that 99.99% Al can deform around the chip joint by
low stress like a solder.
The creep properties of 99.99% Al measured from the tests
and shown in Fig.3 with that of the solder at 60C. It clarified
they have a similar characteristic between 99.99% Al and the
solder around room temperature.

0.2% Proof Stress [MPa]

We have reported some studies of the chip mounting systems

using gold (Au) sub-micron powders or silver (Ag) nano
powders as high-temperature resistant joint materials [3,4]. In
this paper, we chose 99.99% purity Al (99.99% Al) as the
circuit metal which has good electrical and thermal
characteristics. We evaluate a possibility of the stress
reduction on the chip and reliability of the new proposed
structure with 99.99% Al against the thermal cycles. In our
initial study, a simplified structure is investigated by according
to an assumption that the ideal interfacial joint is achieved
with sufficient strength directly between the chip and substrate
in order to evaluate the effects of 99.99% Al.

1.E-05
1.E-06
1.E-07
1.E-08
1

10
stress MPa

100

Fig.3 Creep properties of 99.99% Al and solder

We tried to comprehend a creep mechanism from the results
of the creep tests. The temperature dependence of Steady-State
creep rate can be generally expressed by arrhenius type as

H

AV n exp(

Q
),
RT

(1)

where A and n are creep constants, V is the Mises equivalent

stress, T is the absolute temperature, R is the gas constant, and
Q is the relevant activation energy for creep. Arrhenius plots
of strain rate and the reciprocal of the absolute temperature
obtained by the experimental results at higher temperature
than 140C and low stress are shown in Fig.4. This slope
indicates the value of Q at expression (1) which is 138kJ/mol.
It is close to 142-151kJ/mol as activation energy of lattice
diffusion of Al [6]. On the other side, arrhenius plots at low
temperature and high stress indicate that the value of Q is
73kJ/mol which is almost half value of activation energy of
lattice diffusion as shown in Fig.5. They are suggesting
99.99% Al deformation mechanism at high temperature is
depending on lattice diffusion creep and the mechanism at low
temperature is mostly controlled by dislocation core diffusion
creep. From these results, it is anticipated that 99.99% Al has
a high potential to fulfill the function of reducing the stress on
the chip like the existing solder.

907

-20
-30

Q=138kJ/mol

-40
-50
0.0015

0.002

0.0025 0.003 0.0035 0.004

1/T/K
Fig.4 Arrhenius plots of strain rate at 10MPa and the
relevant activation energy for creep
y = -8.8E+03x + 1.3E+01
Ln (H)/s

-10
-20

Q=73kJ/mol

-30
Fixed in x axis

-40
-50
0.0015

0.002

0.0025 0.003 0.0035 0.004

1/T/K
Fig.5 Arrhenius plots of strain rate at 30MPa and the
relevant activation energy for creep

Z
Y

FINITE ELEMENT ANALYSIS

In order to inspect the stress on the chip, the nonlinear FEA at
several models formed by each substrate distinguished from
CTE or Al thickness was carried out. It is also calculated the
equivalent inelastic strain needed at estimation of the fatigue
life cycles at the chip joint. The general purpose commercial
FEM cord ANSYS and ABAQUS were used on the analysis.
All models used in this analysis are shown in Fig.6. The
models are based on the simplified structure of direct bonding
between the chip and substrate.
t

X
Fixed in y axis

Fig.7 FEA model with symmetrical boundary conditions

400
Temperature []

Ln (H)/s

-10

Model (A) is formed by Direct-Bonding-Aluminum (DBA)

substrate based Aluminum Nitride (AlN) whose CTE is 4.5
ppm/K, which is closely matched in that of the chip. Model
(B) is formed by DBA based Aluminum Oxide (Al2O3) whose
CTE is 7.8 ppm/K. Model (C) and (D) are with thin Al plate
and thick Al plate whose CTE is 23.9 ppm/K at 60C, which
models are supposed under the most intensive condition at
CTE mismatch because of no ceramic. They are threedimensional (3D) quarter models and the symmetrical
boundary conditions are defined as shown in Fig.7. Load
condition is 1.5 thermal cycles that temperature range is from 50C to +300C as shown in Fig.8. The number in figure
shows the analysis step. Material properties used in the FEA
including the experimental results of Al are shown in Table.1.
All of the materials were assumed to behave elastically
without temperature dependences except Al. The data of Si
was substituted for SiC because there were no qualified data
for SiC although we are considering a SiC Power Module.

y = -1.7E+04x + 2.1E+01

300

100
1

0
0

chip

10

30
40
50
60
Time [min]
Fig.8 Thermal cycles for FEA

5mm

20

70

Table.1 Material properties for FEA

5mm
Material

ceramic

Si

Model(A):SiC+Al(t=0.4mm)+AlN
Model(B):SiC+Al(t=0.4mm)+Al2 O3

200

-100

Al

Model(C):SiC+thin Al(t=0.4mm)
Model(D):SiC+thick Al(t=3.5mm)

99.99%
Al

Al2O3

Fig.6 Models for FEA

AlN

908

Temperature

Poisson'sratio

CTE[ppm/K]

Young's modulus

VH

creep

0.280

4.2

130.8

20

0.348

21.9

70.8

60

0.350

23.9

68.2

140

0.352

25.4

65.3

220

0.355

26.6

62.1

300

0.358

27.9

58.6

0.300

7.8

300

0.300

4.5

300

measurem measurem
ent
ent

MaximumPrinciple Stress [MPa]

Stress evaluation of the chip

Fig.9 and Fig.10 show the calculated maximum principle
stress on the chip surface and the chip edge at each model. It is
clear in Fig.9 that the stress at 300C increases from model
(A) to (D). These stresses are suggesting that CTE mismatch
between the chip and substrate causes a global curvature and
stress concentration occurs on the chip surface as shown in
Fig.11.
450
400
350
300
250
200
150
100
50
0

-50
300

MaximumPrinciple Stress [MPa]

Fig.9 The stress calculated on the chip surface

-50
300

Model (A) Model (B) Model (C) Model (D)

Fig.10 The stress calculated on the chip edge

Surface

Model (A)

Model(B)

Model(C)

Model(D)

x50

Fig.12 Stress contour and deformation maps of the chip at

300C (enlarged view at the chip edge)

Model (A) Model (B) Model (C) Model (D)

450
400
350
300
250
200
150
100
50
0

Model(A)

Edge

Model (B)

On the other hand, it is clear in Fig.10 that the stress on the

chip edge is almost 100MPa maximum even though CTE
mismatch increases from model (A) to (D). In Fig.12 enlarged
view at the chip edge, large deformation of Al was observed at
model (C) and (D). It is considered that the stress on the chip
edge is depending on the local stress caused by Al
deformation under the chip corner.
These suggestions indicate the stress on the chip surface is
related with how much curvature is caused by the difference
of CTE mismatch or the difference of Al thickness, and the
stress on the chip edge is related with how much stress is
caused on the circuit metal by CTE mismatch.
The general chip strength was referred about 250MPa [7].
Thus, the results of analysis predict the thick Al plate without
any ceramics shown as model (D) is difficult to apply for the
high-temperature resistant structure because of the chip crack.
Inelastic Strain evaluation of Al
Continuously, in order to estimate the fatigue life at the chip
joint of each model, equivalent inelastic strain range (Hin) of
Al was calculated. We used the average value of equivalent
inelastic strain (Hin) because the calculation from a specific
node has a risk of causing the excessive value depending on
mesh size. Therefore, to decide the calculation nodes, crack
propagation analysis was carried out at first. The analysis step
is added deleting works of the elements in general nonlinear
stress-strain analysis. The results indicate strain concentration
in Al occurs under the chip shown in Fig.13. And a crack will
occur around the chip corner and grow to the inside of Al by
crawling under the chip. This behavior is almost same at all
models. Accordingly, it was decided that several nodes of Al
under the chip corner following by the clack propagation are
sampled to calculate the average value of Hin.

Si

Model (C)

Model (D)

x50

Al

Fig.11 Stress contour and deformation maps of the chip

at 300C
Fig.13 Creep Strain contour map of Al (Model (B))

909

CEEQ+PEEQ -

Fig.14 shows the history plots of Hin at each model which are
added equivalent creep strain (CEEQ) and equivalent plastic
strain (PEEQ). The step number in the history plots
corresponds to the analysis step of the thermal cycles shown in
Fig.8. From these results, the total equivalent inelastic strain
range (Hin) per a cycle between -50C and 300C at each
model were calculated as shown in Fig.15.
It clarified Hin is generated about 1% ~ 3% on the chip
mounting structure formed by 99.99% Al and ceramic
substrate like model (A) and (B). But high value of Hin is
predicted in model (C) and (D). This tendency is similar to the
maximum principle stress at 300C on the chip edge as shown
in Fig.10. It is clear in Fig.10 and Fig.15 that the value in
model (D) is higher than that in model (C) even though CTE
mismatch between the chip and substrate is the same in both
models. It is suggesting that the strain of Al under the chip
corner is influenced by not only local deformation by the CTE
mismatch between the chip and circuit metal on the substrate
but also global curvature by the CTE mismatch between the
chip and substrate.
0.50

model (A)

0.40

model (B)

material are considered in FEA to calculate Hin [8]. So, in

order to evaluate the thermal fatigue life at the chip joint of
each model, the mechanical fatigue tests of 99.99% Al were
carried out instead of the thermal fatigue tests which need
much more time. The tests of the tin-based solder
(Sn3Ag0.5Cu) were also enforced for comparison.
The fatigue tests were conducted by repeated triangular
waveform controlled displacement with 1Hz frequency at
room temperature by using INSTRON micro force testing
machine. Fig.16 shows a schematic illustration of the 3 points
bending fatigue tests equipment with a specimen. The
equipment is composed by a middle part which moves to
produce the load and two side parts which set the specimen
not to move even the plastic strain is produced on the
specimen. The specimens are formed with a notch for strain
concentration as shown in Fig.17 in order to imitate the shape
of Al fatiguing under the chip corner. They were annealed at
480C for 2 hours in Nitrogen to remove the damage induced
by the machining shaping process. The specimens of
Sn3Ag0.5Cu were also annealed at 143 C for 2 hours in
Nitrogen.
displacement 

model (C)
0.30
model (D)

2Hin

0.20
0.10

Fig.16 Fatigue testing equipment by 3 points bending

0.00
0

4
Step

20mm

Equivalent inelastic strain range Hin

Fig.14 Total equivalent creep and plastic strain history

on Al under the chip corner at each model

1mm
6mm

0.20
0.15

0.5mm
0.10

Fig.17 Specimen for low cycle fatigue tests

0.05

Low cycle fatigue property of a nonlinear material like a

solder is generally evaluated based on Manson-Coffins law
with an inelastic strain which is calculated by FEA [8]. This
property is expressed as

0.00
Model (A) Model (B) Model (C) Model (D)

Fig.15 Total equivalent inelastic strain range of Al at

each model

Nf

MECHANICAL FATIGUE TEST

An evaluation of the thermal fatigue life at the chip joint based
on the mechanical fatigue property of the joint material is
generally possible if the temperature dependences of the

1000 (

'H in n
) ,
C

( 2)

where Nf is number of cycles to failure, Hin is the equivalent

inelastic strain range, n and C are the material constant. The
constant C indicates the value of Hin when Nf reaches 1,000
cycles. In this study, we tried to apply the expression (2) to

910

Nf

1000(

'H in
)  2.13
5.69 E  02

(3)

From Hin calculated by prior analysis shown in Fig.15 and

expression (3), the thermal fatigue life cycles at the chip joint
of each model were estimated as shown in Table.2. By these
results, the high-temperature resistant mounting structure
which is formed by 99.99% Al and ceramic substrate is
expected to keep satisfied fatigue life more than 4,000 thermal
cycles, even though the temperature range of the thermal cycle
are expanded from -50/+150C for conventional Power
Modules to -50/+300C for SiC Power Modules.

principally led with the nonlinear properties and the fatigue

property of 99.99% Al. In general, the plastic and creep
properties of Al are mentioned to be characterized by
dislocation behavior which is greatly influenced by impurities
into Al. Therefore, the effects are possibly suspected
depending on how much purity of Al. But we need to avoid
demanding too much high purity because of a cost problem.
So, we attempted to investigate the possibility of the effects
influenced by kind of industrial Al on the proposed structure
by working additional tensile tests. We chose 99.5% purity Al
(99.5% Al) and 99.7% purity Al (99.7% Al) as industrial Al
and 99.99% Al as reference. Specimens for the tests were the
same used in the preparative tests shown in Fig.1. The tensile
tests were carried out on 0.4%/s strain rate at room
temperature.
By the results, all Al indicated distinguished nonlinear
characteristics such as low 0.2% Proof Stress and high
ductility comparatively another material as shown in Fig.19. It
also clarifies that 99.5% Al or 99.7% Al shows twice value of
0.2% Proof Stress and lower Elongation compared with
99.99% Al. These results are suggesting that 99.5% Al or
99.7% Al applied on the proposed structure produces much
stress on the chip and poor thermal fatigue life. Therefore, it
became clear that application of 99.99% Al on the proposed
structure is the best solution to reduce stress on the chip and to
secure reliability at the chip joint.

99.99% Al
Sn3Ag0.5Cu
0.2% Proof Stress [MPa]

Equivalent inelastic strain range Hin

1.0E+00

1.0E-01

60

120

50

100

40

80

30

60

20

40
0.2% Proof Stress
Elongation

10

20

1.0E-02
1.0E+02

1.0E+05

99.99%
1 Al

99.7%
2 Al

99.5%
3 Al

Materials

Fig.19 0.2% Proof Stress and Elongation of each

Al measured by tensile tests (0.4%/s strain rate)

Fig.18 Fatigue property of 99.99% Al and

Sn3Ag0.5Cu solder
Table.2 Comparative chart of fatigue life cycles

Model
(A)
(B)
(C)
(D)

0
0

1.0E+03
1.0E+04
Cycles to Failure Nf

Elongation [%]

estimate the fatigue life at the chip joint of each model from
the results of mechanical fatigue tests.
The load condition on the fatigue tests was defined by the
value of Hin on the notch calculated by the FEA simulating
the each bending test. Material properties of 99.99% Al for the
FEA are the same as the data used in prior analysis shown in
Table.1. Material properties of Sn3Ag0.5Cu solder are
referred to the text [5]. Nf was defined by 7% load drop when
the initial crack reached to 50Pm. These values were assumed
by the relationship between the ratio of load drop and the
crack length when the test was finished.
The results of the tests are shown in Fig.18. The low cycle
fatigue property of 99.99% Al was obtained, which could be
presented as expression (3).

Hin [-] Nf [cycles]

1.58E-02
15,269
2.87E-02
4,291
1.21E-01
200
1.76E-01
90

DISCUSSION AND
ADDITIONAL TENSILE TEST
It became clear from the results of FEA and fatigue tests that
the proposed structure has a high potential to secure the SiC
chip joint reliability by using 99.99% Al. These effects are

CONCLUSIONS
The results obtained in this study are as follows.
A proposed high-temperature resistant mounting structure for
SiC devices that formed by high purity Al with a high rigidity
ceramic as a substrate has a possibility to fulfill the function of
reducing stress on the chip like the existing solder against the
intense thermal cycling tests such as -50/+300C.
A proposed structure that formed by high purity Al plate only
as a substrate has risks that a crack occurs on the chip due to
the global curvature caused by CTE mismatches between the
chip and substrate.
A proposed structure that formed by high purity Al with a high
rigidity ceramic as a substrate has a possibility to endure more
than 4,000 thermal cycles of -50/+300C.

911

An application of 99.99% Al on the proposed structure is the

most effective to reduce the stress on the chip and secure
reliability at the chip joint compared with 99.5% Al or 99.7%
Al.
Therefore, it became clear that the proposed mounting
structure for high-temperature device using 99.99% Al has a
high potential for the chip stress reduction and the chip joint
reliability.
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