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Practice Test by Electrical Mentor

(ESE/GATE/PSU)

Author: BNSS Shankar, M.Tech (IITK)

Paper Code: EGP AE01
Branch: Electrical and Electronics Engineering
Subject: Analog Electronics
Instructions:
1.
This Practice Test (PT) will have 30 questions and some questions may need calculator to
solve numerical problems. I will suggest the students to write this PT in 45 minutes
2.
These PTs will helpful for the students who are preparing for ESE/ GATE /PSUs
3.
If you get any doubt while solving the questions, show your work to your teacher and get
clarify your doubt.
4.
If you practice all of my tests, I am very sure that your expertise in the domain
knowledge will improve. All the best and start the test

01.

In the circuit shown in the figure, it is

found that VBE = 0.7 V and VE = 0 V.
If dc = 99 for the transistor, then the value
of RB in kilo ohm is______

02.

An op amp has ideal characteristics except that its open loop gain is given by the
10 4
. this op amp is used in the circuit shown in the given figure.
expression AV (s ) =
1 + 10 3 s
The 3-dB bandwidth of the circuit, in rad/s is

(A)

102

(B)

103

(C)

104

(D)

106

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EGP-AE01: Prepared by BNSS Shankar, M.Tech (IITK)

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03.

Consider a low pass filter module with a pass band ripple of in the gain magnitude. If M
such identical modules are cascaded, ignoring the loading effects, the pass band ripple of
the cascade is
M
(A)
1 (1 )
(B)
M
(C)

04.

IB = 800 nA, If = 50 nA
IB = 800 nA, If = 100 nA
IB = 400 nA, If = 50 nA
IB = 400 nA, If = 100 nA

Ri
Ri
Ri
Ri

= 500 k and Rf = 50 k
= 50 k and Rf = 500 k
= 5 k and Rf = 10 k
= 50 k and Rf = 200 k

For the circuit shown in the figure, assume ideal diodes with zero forward resistance and
zero forward voltage drop. The current through the diode D2 in mA is
(A)
(B)
(C)
(D)

07.

(1 )

The amplifier in the given figure has a gain of -10 and input resistance of 50 k. The
values of Ri and Rf are
(A)
(B)
(C)
(D)

06.

(D)

For the op-amp shown in the figure, the bias current are Ib1 = 450 nA and Ib2 = 350 nA.
The values of the input bias current (IB) and the input offset current (If) are
(A)
(B)
(C)
(D)

05.

(1 )M

5
15
10
20

Assuming an ideal op-amp in linear range of operation, the magnitude of the transfer
v
impedance 0 in M of the current to voltage converter shown in the figure is_____
i
Consider R1 = 45 k, R2 = 5 k and R3 = 55.5 k

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EGP-AE01: Prepared by BNSS Shankar, M.Tech (IITK)

Page 3 of 7

08.

For the circuit shown in the figure, the transistor has = 40, VBE = 0.7 V and the voltage
across the Zener diode is 15 V.

The current (in mA) through the Zener diode is _______

09.

In the figure, transistors T1 and T2 have identical characteristics. VCE(sat) of transistor T3 is

0.1 V. The voltage V1 is high enough to put T3 into saturation. Voltage VBE of T1, T2 and
T3 is 0.7 V. The value of (V1 _V2) is _________ V

10.

The figures show an oscillator having an ideal Schmitt trigger and its input output
characteristics. The time period (in ms) of vo(t) is ________

11.

For the low pass filter shown in the figure, the cut off frequency in Hz will be _____

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EGP-AE01: Prepared by BNSS Shankar, M.Tech (IITK)

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12.

If the base width of bipolar junction transistor is doubled, which one of the following
statements will be TRUE?
(A)
Current gain will increase
(B)
Unity gain frequency will increase
(C)
Emitter base junction capacitance will increase
(D)
Early voltage will increase

13.
In the circuit shown in the figure, the BJT
has a current gain () of 50. For an emitter
base voltage VEB = 600 mV, the emitter
collector voltage VEC (in volt) is
(A)
(B)
(C)
(D)

1
2
3
1.5

14.

In the circuit shown using an ideal op-amp, the 3-dB cut off frequency (in Hz) is____

15.

An npn BJT having reverse saturation current Is = 10-15 A is biased in the forward active
region with VBE = 700 mV. The thermal voltage (VT) is 25 mV and the current gain ()
may vary from 50 to 150 due to manufacturing variations. The maximum emitter current
(in A) is______

16.

In the circuit shown, V0 = V0A for switch SW in position A and V0 = V0B for switch SW in
V
position B. Assume that the op-amp is ideal. The value of 0 B is
V0 A

(A)

(B)

(C)

1.5

(D)

2.5

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EGP-AE01: Prepared by BNSS Shankar, M.Tech (IITK)

Page 5 of 7

17.

In the circuit shown, assume that the op-amp is ideal. If the gain

V0
= 12 , the value of
Vin

R (in k) is
(A)
(B)
(C)
(D)

1
2
3
1.5

18.
In the circuit shown in figure, assume that
the diodes D1 and D2 are ideal and source
voltage is v s = 6 sin (t ) . The average
value of voltage Vab (in volt), across
terminals a and b is ______

19.

If the circuit shown has to function as a clamping circuit, then which one of the following
conditions should be satisfied for the sinusoidal signal of period T?
(A)
(B)
(C)
(D)

20.

In the bi stable circuit shown, the ideal op-amp has saturation levels of 5 V. The value
of R1 (in k) that gives a hysteresis width of 500 mV is
(A)
(B)
(C)
(D)

21.

RC << T
RC = 0.35 T
RC T
RC >> T

0.5
1.0
1.5
2.0

The Fermi level in a p type semi conductor lies close to

(A)
top of the valence band
(B)
bottom of the valence band
(C)
top of the conduction band
(D)
bottom of the conduction band

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EGP-AE01: Prepared by BNSS Shankar, M.Tech (IITK)

Page 6 of 7

22.

The diode in the circuit below has VON = 0.7 V but is ideal otherwise. The current (in
mA) in the 4 k resistor is ______

23.

Assume that the op-amp shown in the circuit is ideal. The output voltage V0 (in volt)
is______

24.

For the voltage regulator shown, the input voltage (Vin)is 20 V 20% and the regulated
output voltage (Vout) is 10 V. Assume the op-amp to be ideal. For a load RL drawing 200
mA, the maximum power dissipation in Q1 (in watt) is ______

25.

In the ac equivalent circuit shown, the two BJTs are biased in active region and have
identical parameters with >> 1. The open circuit small signal voltage gain is
approximately _______

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EGP-AE01: Prepared by BNSS Shankar, M.Tech (IITK)

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26.

The early effect in a bipolar junction transistor is caused by

(A)
fast turn off
(B)
fast turn on
(C)
large emitter to base forward bias
(D)
large collector to base reverse bias

27.

In a JFET, operating above pinch off voltage, the

(A)
drain current increases steeply
(B)
drain current remains practically constant
(C)
drain current starts decreasing
(D)
depletion region reduces

Each of the following THREE questions consists of two statements. One labeled as statement I
and the other as statement II. You are to examine these two statements carefully and select the
answers to these items using the codes given below:
Code:
(A)
Both statement I and statement II are individually true and statement II is correct
explanation for statement I
(B)
Both statement I and statement II are individually true and statement II is not the correct
explanation for statement I
(C)
statement I is true but statement II is false
(D)
statement I is false but statement I is true

28.
Statement I: A FET is current controlled device
Statement II: Operation of a FET depends only on majority carriers

29.
Statement I: Thermal run away is not possible in a FET
Statement II: As the temperature increases, the mobility of carriers decreases

30.
Statement I:

Current limiting resistor is used in series with the light emitting diode
(LED) to limit current and light output
Statement II: The light output of LED is approximately proportional to the current
passing through it

End of the Practice Test

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EGP-AE01: Prepared by BNSS Shankar, M.Tech (IITK)