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JOURNAL OF APPLIED PHYSICS

VOLUME 94, NUMBER 5

1 SEPTEMBER 2003

One-dimensional heat conduction model for an electrical phase change


random access memory device with an 8 F 2 memory cell F 0.15 m
Dae-Hwan Kang, Dong-Ho Ahn, Ki-Bum Kim,a) J. F. Webb, and Kyung-Woo Yi
Research Institute of Advanced Materials, Seoul National University, School of Material Science
and Engineering, San 56-1, Shillim-dong, Kwanak-ku Seoul 151-742, Korea

Received 28 March 2003; accepted 11 June 2003


A one-dimensional heat conduction model is developed for a phase change random access memory
device with an 8F 2 memory cell structure (F0.15 m). The required current level for a reset
operation, which corresponds to the phase switching from a crystalline 1 state to an amorphous
phase 0 state of Ge2 Sb2 Te5 , was investigated by calculating one-dimensional temperature
profiles for the memory cell structure. It is revealed that a reset operation is not achieved at the
current level 2 mA reported for existing devices with a subquarter micron plug size when only TiN
is used as a resistive heater. However, it is possible when an additional heating layer of 5 nm
thickness is inserted between the TiN and Ge2 Sb2 Te5 layers, for which the electrical resistivity elec
is higher than 105 cm, and the thermal conductivity and specific heat c are as low as those of
Ge2 Sb2 Te5 . In addition, it is shown that a reset operation at a low current level of 1 mA can be
realized in this memory cell when amorphous carbon ( 0.2 W/m K and elec106 cm) is
used as an additional heating layer. It is believed that this relatively simple one-dimensional heat
conduction model is a useful tool for analyzing the device operation of phase change random access
memory devices and for selecting the proper conditions for an additional heating layer allowing for
low-current operation. 2003 American Institute of Physics. DOI: 10.1063/1.1598272

I. INTRODUCTION

sesses a similar cell structure to that of a conventional


DRAM. In addition, it is possible to operate at a low switching current of the order of milliamps since phase switching
only occurs in a small region a programmable volume as
shown in Fig. 1 above the plug material. In such a 1T/1R
cell with a plug, it is believed that the selection of the right
plug material is a key to low-current operation because it acts
as a resistive heater increasing the temperature above the
glass transition temperature (T t ) or the melting temperature
(T m ); also it provides a conducting path for the current required for read and write operations. For this reason, the plug
material in contact with the Ge2 Sb2 Te5 layer is often called a
resistive heater. As far as we are aware, no work has yet been
reported on the requirements for a resistive heater in this
context even though several candidates for resistive heater
materials such as doped polysilicon,2 TiN,6,7 and TiAlN Ref.
8 have recently appeared in literature.
It is important to calculate the temperature distribution in
a memory cell for several plug materials having different
thermal and electrical properties, since such information is
helpful for choosing the right resistive heater. In this study, a
one-dimensional heat conduction model is developed in order to simulate the writing operation in the 1T/1R PCRAM
cell with plug contact. Based on this model, the reset current
values are calculated for various plug systems and compared
with the experimental data of other researchers.4,6 8 It is
shown that the insertion of an additional heating layer between the TiN and Ge2 Sb2 Te5 layers makes a reset operation
possible at a current level of 12 mA, suitable for lowcurrent operation. Finally, the requirements of such an additional heating layer are discussed in terms of its electrical

The phase change random access memory PCRAM is a


possible substitute for all kinds of current memory devices
such as dynamic random access memory DRAM, static
random access memory, flash memory, and others. The
PCRAM has a simple cell structure with high scalability; it is
nonvolatile, has a relatively high read/write operation speed
50 ns, and a long cycle life (1014 operations.1 4 Furthermore, superior radiation tolerance makes it attractive for
space-based applications.5,6
The PCRAM operation relies on the fact that
chalcogenide-based materials, such as Ge2 Sb2 Te5 and
Ge1 Sb2 Te4 , can be reversibly switched from an amorphous
phase, also called as reset or 0 state, to a crystalline phase
called a set or 1 state or vice versa by an external electric
current. The electrical resistivity of the amorphous and crystalline phases differs by a factor of 104 , which is very favorable for phase change memory operation. However, there are
still several problems to be solved before the commercialization of PCRAM can be achieved; these include the high operation current 13 mA, the slow set writing speed 50
ns, and the thermal fatigue of the phase change material.
The operation current level should be reduced to a few hundreds of A for low-power high-density memory chip production.
Among several cell structures that have been developed
for PCRAMs, the 1 transitor/1 resistor 1T/1R structure with
contact plug,4,6 shown in Fig. 1, has the strongest potential
for mass production since it is relatively simple and posa

Electronic mail: kibum@snu.ac.kr

0021-8979/2003/94(5)/3536/7/$20.00

3536

2003 American Institute of Physics

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Kang et al.

J. Appl. Phys., Vol. 94, No. 5, 1 September 2003

3537

FIG. 1. Schematic diagram of a 1 transistor/1 resistor 1T/1R structure with


contact plug, showing a unit cell of a phase change random access memory
device from Refs. 4 and 6.

resistivity, thermal conductivity, specific heat, and melting


temperature values.

II. ONE-DIMENSIONAL HEAT CONDUCTION MODEL


DESCRIPTION

We consider a one-dimensional heat conduction model


in order to predict how much external current is necessary
for phase switching of Ge2 Sb2 Te5 from a crystalline to an
amorphous phase in the 1T/1R PCRAM cell structure. Two
different currents are necessary for PCRAM operation. One
is a reset current for switching from a crystalline to an amorphous phase and the other is a set current which switches
from an amorphous to a crystalline phase. The reported values of set and reset currents for a 1T/1R cell structure, with
a subquarter micron plug size, have a range of 0.51.5 mA
and 1.52.5 mA, respectively.4,6,7 Therefore, the reduction of
the reset current level is more important for low-current operation, and we will focus on this. It should also be noted
that it is sufficient to consider a one-dimensional model since
both current flow and heat dissipation mainly occur in the x
direction shown in Fig. 1, although a multidimensional
model is necessary for a more accurate simulation.
Figure 2a shows the schematic cross-sectional diagram
of the memory cell for which the one-dimensional heat
conduction model has been developed. The memory cell
is assumed to have a Si-substrate/W-plug/resistive
heater/Ge2 Sb2 Te5 /TiN/W layered structure, and the thickness
of each layer, not including the substrate, is 0.5, 0.05, 0.1,
0.05, and 0.5 m, respectively. Here, the TiN and W layers
are taken to be a diffusion barrier and a metal plug material,
respectively. In addition, we assume that the current state-ofthe-art 0.15 m DRAM technology with a conventional 8F 2
cell area is used to fabricate the PCRAM device; then the
cross-sectional area of the plug contact (A plug) is F 2 0.0225
m2, and the cross-sectional area of the Ge2 Sb2 Te5 layer
(A GST) is 3F 2 0.0675 m2 where F is a feature size of 0.15
m, as shown in Fig. 2b.

FIG. 2. a The schematic cross section of the PCRAM memory cell for
which a one-dimensional heat conduction model is developed and b the
top view of a conventional 8F 2 memory cell.

The phase switching of Ge2 Sb2 Te5 is triggered by Joule


resistive heating (q Joule), given by
q JouleI F2 Rt,

where, I F is the external forcing current, R is the electrical


resistance of the Joule heating material, and t is the heating
time. Also, R is given by R elec/A, where elec is electrical resistivity, is the length, and A is the cross-sectional
area of the Joule heating material, respectively. The onedimensional temperature profile versus the distance x from

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3538

Kang et al.

J. Appl. Phys., Vol. 94, No. 5, 1 September 2003

the active region of the Si substrate can be obtained by solving the one-dimensional heat equation with a source term of
the form q Joule . For the ith layer, the equation is

T i i 2 T i q Joule,i

t
ci x2
ci

x i1 xx i ,

where i is the density, i is the thermal conductivity, and c i


is the specific heat for ith layer with i1,2,...,n when there
are n layers. First of all, two boundary conditions at xx 0
0 and xx n 1.2 m should be given in order to solve
Eq. 2. Since the Si layer has a relatively high thermal conductivity 148 W/m K at 300 K, the temperature at xx 0 is
considered to be the junction temperature T J that occurs during device operation. It is well known that T J reaches as
much as 80 C under 3.3 or 5 V operation voltage levels in
microelectronics.9 On the other hand, it is believed that the
temperature at xx n remains at room temperature since the
W used in the interconnect metallization has a high thermal
conductivity above 200 W/m K at 300 K, which is about a
factor of 104 higher than that of Ge2 Sb2 Te5 0.46 W/m K.8
Therefore, the two boundary conditions at xx 0 and xx n
are assumed to be T 0 80 C and T n 25 C. The remaining
boundary conditions at the interfaces between the layers are
assumed to have the usual form for layers in perfect thermal
contact, that is, i ( T i / x) xx i i1 ( T i1 / x) xx i and
T i xx i T i1 xx i , i1,...,n1.
In order to estimate the current required for a reset operation, we should consider two parameters, the melting temperature of Ge2 Sb2 Te5 (T m 632 C) and the critical thickness for phase switching (x crit). First, the temperature rise
due to the reset current should be higher than T m in order to
transform the Ge2 Sb2 Te5 layer from a crystalline to a liquid
phase. Second, it is said that the ratio of resistance of a reset
state to that of a set state ought to be greater than 100 for
reliable read operation of a PCRAM,10 which can be expressed as
R RESET
100.
R SET

99 AR c c
x crit ,
a c

Ge2 Sb2 Te5 , respectively. Taking R c to be 1500 , x crit is 93


. Therefore, the programmable distance for a read operation
should be greater than 1/10 of the total thickness 1000 of
the Ge2 Sb2 Te5 layer in the structure depicted in Fig. 2a. As
a result, the critical point (x crit ,T m ) for a reset operation,
calculated from the heat conduction model, is 0.56 m,
632 C. It is concluded that a write operation is only possible
when the temperature profile at x0.56 m generated by a
reset current is greater than or equal to 632 C. Based on this
one-dimensional heat conduction model, it is possible to estimate the reset current value for various plug systems and
compare it with experimental data of other researchers;4,6 8
this will be described in Sec. III.

3
III. RESET CURRENT CALCULATION

This requirement leads to a minimum programmable distance that sets the minimum or critical thickness (x crit) of the
Ge2 Sb2 Te5 . It can easily be calculated using Eq. 3 and a
simple model of the read operation of the PCRAM, as shown
in Fig. 3, leading to
x

FIG. 3. a The resistance of a set state R SET state and b reset state R RESET
for the read operation of the PCRAM. Here, R c is the circuit resistance, c
and a are the electrical resistivities of the crystalline and amorphous phases
of Ge2 Sb2 Te5 , respectively, x is the programmable thickness, is the total
length, and A is the cross-sectional area of the Ge2 Sb2 Te5 layer.

where x is the programmable distance, is the total length,


and A is the cross-sectional area of the Ge2 Sb2 Te5 layer; R c
is the total circuit resistance, excluding that of the Ge2 Sb2 Te5
layer, and is the sum of the channel resistance of the cell
transistor R Tr , source/drain resistance R SD , plug resistance
R plug , metallization resistance R metal , and a series of contact
resistances R contact . It has been found that R c has a range of
10001500 under typical current 0.30.5 mA and voltage 0.5 V conditions for a read operation.4,7,8 In addition,
c and a are the electrical resistivities of the crystalline 416
cm11 and amorphous 100 cm12 phases of

The one-dimensional heat equation, Eq. 2, is solved


using numerical techniques employing an implicit time step
and a second-order finite central difference scheme in space.
It is noted that the temperature dependencies of physical
properties such as thermal conductivity, specific heat, and
electrical resistivity are neglected and we use values at 25 C
in the temperature profile calculation. However, when solving the equation, we take into account the heat loss during
the phase transformation of Ge2 Sb2 Te5 from a crystalline to
a liquid phase at 632 C, which is an endothermic process so
that some of the Joule heat is consumed by the heat of fusion
622 J/cm3 for Ge2 Sb2 Te5 ).
First of all, consider the memory cell of Fig. 2a in
which a TiN layer only is used as a resistive heater, such a
cell is currently being evaluated for its suitability as a
PCRAM memory cell.6,7 The required thermal and electrical
data for W, Ge2 Sb2 Te5 , and TiN at 25 C are given in Table
I. Note that TiN has a wide range of electrical resistivity and
thermal conductivity values. It is well known that the resis-

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Kang et al.

J. Appl. Phys., Vol. 94, No. 5, 1 September 2003

3539

TABLE I. Reported physical properties of W, Ge2 Sb2 Te5 , and TiN at 25 C.

W
Ge2 Sb2 Te5 a
TiN

Melting
temperature
T m C

Mass density
(106 g/m3 )

Specific heat
c J/g K

Thermal conductivity
W/m K

Electrical resistivity
elec cm

3407
632
2950

19.3
6.2
5.24

0.132
0.202
0.784

174
0.46
220.44c

5.39
416b
201000

See Ref. 8.
See Ref. 11.
c
Assumed values from the resistivity or conductivity values of TiN film by using a WiedemannFranz law.
b

tivity of a TiN film ranges from several tens of cm for


high-quality sputtered TiN films13 to thousands of cm
for low-quality chemical vapor deposited TiN films.14,15 So
the value depends on the film composition, impurity level,
and deposition technique. However, since the TiN layer is
regarded as a metallic conductor, the thermal conductivities
of TiN in Table I are estimated using a WiedemannFranz
law which states that the electrical and thermal conductivities of metals are proportional at a given temperature.
Figure 4 shows the calculated temperature profiles for a
Si-substrate/W-plug/TiN-heater/Ge2 Sb2 Te5 /TiN/W structure
at different resistivities and thermal conductivities of TiN.
The current is fixed at 2 mA, a typical value for a reset
current. It is noted that the temperature in the Ge2 Sb2 Te5
layer slightly increases as the resistivity of TiN is increased
but it is as low as 180 C even with a resistivity of 1000
cm and thermal conductivity of 0.44 W/m K. These results indicate that for a memory cell with only a TiN heater,
a reset operation is impossible because its temperature profile does not encompass the critical point 0.56 m and
632 C. It is believed that such a low temperature is due to
the relatively low electrical resistivity and high thermal conductivity of TiN. We can conclude that a good electrical and
thermal conductor, like TiN, is not able to generate enough
Joule heat while at the same time rapidly dissipating the heat
in the Ge2 Sb2 Te5 layer to the surroundings.

FIG. 4. Temperature profiles vs distance x from the active region of the Si


substrate for different values of TiN resistivity and thermal conductivity in
the layered structure: Si substrate/W plug/TiN heater/Ge2 Sb2 Te5 /TiN/W.

For effective Joule heating and heat isolation of the


Ge2 Sb2 Te5 layer, let us introduce an additional heating layer
between the TiN heater and Ge2 Sb2 Te5 , so that the structure
becomes a Si-substrate/W-plug/TiN-heater/additional heating
layer/Ge2 Sb2 Te5 /TiN/W, as shown in Fig. 5. The thickness
of the additional layer is assumed to be 5 nm. Here, a prerequisite is to determine what range of electrical and thermal
properties an additional heating layer should have, especially
compared with those of Ge2 Sb2 Te5 . They are electrical resistivity ( elec), thermal conductivity , specific heat c,
and mass density , as shown in Eqs. 1 and 2.
Figure 6a shows the calculated temperature profiles in
the memory cell in Fig. 5 with different resistivities for the
additional heating layer assuming other physical properties,
such as thermal conductivity, mass density, and specific heat
to be the same as those of Ge2 Sb2 Te5 . When the resistivity
of an additional heating layer is below 105 cm, the temperature profiles at xx crit are much lower than the value T m
required for a reset operation. This indicates that the Joule
heating is still insufficient to increase the temperature above
T m in the Ge2 Sb2 Te5 layer. However, with a heater-layer
resistivity of 105 cm, the temperature at the interface
between the heater and Ge2 Sb2 Te5 layer reaches T m and it
rapidly increases as the resistivity is increased further.

FIG. 5. Schematic cross section of the memory cell when an additional


heating layer is inserted between the TiN heater and Ge2 Sb2 Te5 layers.

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3540

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J. Appl. Phys., Vol. 94, No. 5, 1 September 2003

Next, by fixing the electrical resistivity at 105 cm,


the temperature profiles were calculated for additional heating layers with various thermal conductivities in order to find
the optimum range; these are plotted in Fig. 6b. In this
case, the mass density and specific heat are assumed to be the
same as for Ge2 Sb2 Te5 . The temperature at xx crit fails to
exceed T m when the thermal conductivity of an additional
heating layer is higher than that of Ge2 Sb2 Te5 0.46 W/m K.
However, the temperature at the top (x0.555 m) of the
additional heating layer starts to rise above T m when the
thermal conductivity is equal to or lower than that of
Ge2 Sb2 Te5 . As is seen in Fig. 6c, the effect of the specific
heat on the temperature profiles is the same as that of thermal
conductivity. That is, the temperature at xx crit is higher
than T m when the specific heat is equal to or lower than that
of Ge2 Sb2 Te5 0.202 J/g K. In contrast, the temperature profile was not affected by the change of density.
From these results, it is concluded that the electrical resistivity of an additional heating layer should be higher than
105 cm and its thermal conductivity and specific heat
should be as low as that of Ge2 Sb2 Te5 for a 2 mA reset
operation for the memory cell structure of Fig. 5. In practice,
it is difficult to find a material satisfying these requirements
simultaneously because electrical conductors generally have
a high thermal conductivity. Nonetheless, amorphous carbon
(a-C) can be considered as an additional heater layer since it
is reported to have a low thermal conductivity range 0.22.2
W/m K16 and an intermediate electrical resistivity range
(104 106 cm), 17,18 depending on its composition, bonding structure, or on the deposition techniques. The reported
physical properties of a-C are summarized in Table II. Its
specific heat is assumed to be the average value of the two
crystalline allotropes diamond and graphite.
Figure 7a shows temperature profiles at 2 mA when
a-C with different thermal conductivities16 is used as an additional heating layer. For convenience, its electrical resistivity is fixed at 106 cm. It is clear that the temperature at
the interface between the a-C and Ge2 Sb2 Te5 layers is
higher than T m . Furthermore, it is shown in Fig. 7b that a
reset operation at a low current of 1 mA can be realized in a
0.15 m 8F 2 memory cell when a-C ( 0.2 W/m K and
elec106 cm) is used. Therefore, it is believed that a-C
is a good candidate for a resistive heater material for a low
operating-current PCRAM device.
IV. DISCUSSION

FIG. 6. Temperature profiles vs distance x from the active region of the Si


substrate in a memory cell with a TiN-heater/additional heating layer
(5 nm)/Ge2 Sb2 Te5 structure for heating layers with different values of a
electrical resistivity, b thermal conductivity, and c specific heat, where
current I F is fixed at 2 mA.

Contemplating the results in Sec. III, it is believed that


three factors should be taken into account when selecting a
resistive heating layer for low-current PCRAM device operation. The first one is that the Joule resistive heat should be
efficiently generated by a low current. For this, a material
with high electrical resistivity and low specific heat is preferable, as shown in Figs. 6a and 6c, respectively. The
higher the electrical resistivity, the larger the amount of Joule
heat generated by the term in Eq. 1. In addition, the lower
the specific heat, the higher the temperature for the same
Joule heating rate because less heat is required to increase
the temperature. However, there is an upper limit for the

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Kang et al.

J. Appl. Phys., Vol. 94, No. 5, 1 September 2003

3541

TABLE II. Reported physical properties of amorphous carbon at 25 C.

a-C

Melting
temperature
T m C

Mass density
(106 g/m3 )

Specific heat
C J/g K

Thermal conductivity
W/m K

Electrical resistivity
elec cm

36523697

1.8 2.1

0.617a

0.22.2b

104 106c

Assumed to be the average value of graphite 0.714 J/g K and diamond 0.521 J/g K.
See Ref. 16.
c
See Refs. 17 and 18.

FIG. 7. Temperature profiles of TiN-heater/a-C (5 nm)/Ge2 Sb2 Te5 structure with various thermal conductivities from Ref. 16 for a-C at a I F
2 mA and b I F 1 mA. For convenience, the electrical resistivity of a-C
is fixed at 106 cm.

resistivity, since if it is too high, the read operation on the


memory cell fails due to its high resistance. Simple calculations for the memory cell in Fig. 5 show that the electrical
resistivity of an additional heating layer should not be greater
than 106 cm so that its resistance does not exceed the
total circuit resistance (R c ). The second factor is that it is
important to prevent the generated Joule heat from being
dissipated through the contact plug region by making a resistive heating layer with a thermal conductivity as low as
Ge2 Sb2 Te5 , as shown in Fig. 6b. Third, the resistive heater
should have a higher melting temperature than that of
Ge2 Sb2 Te5 632 C, since it should not melt during device
operation.
a-C is a good candidate for a resistive heater satisfying
the aforementioned requirements, as shown in Fig. 7. Some
oxynitrides such as TiOx Ny Ref. 19 and thin films of oxides
such as Al2 O3 , 20 in which current flows due to quantummechanical tunneling, may also be considered as materials
satisfying these requirements, since they are likely to have
thermal conductivities in a range as low as 12 W/m K and
an electrical resistivity range of 104 106 cm.
It is also important to investigate the temperature profile
under actual device operation conditions. In an actual reset
operation, a current pulse is applied to the memory cell instead of the constant current used in Figs. 4, 6, and 7. For
example, consider a current pulse, shown in Fig. 8a, for
which the on- and off-current periods are 50 ns. Figure 8b
shows the resulting temperature profile versus distance x and
time t at 1 mA from our heat conduction model when such a
current pulse is applied to the memory cell in Fig. 5 with a
TiN-heater/a-C ( 0.2 W/m K and elec106 cm)/
Ge2 Sb2 Te5 structure. It is notable that the temperature in the
Ge2 Sb2 Te5 layer rises above 1000 C after a short time 20
ns. In addition, the temperature drops abruptly from near
1000 C to below 80 C within 20 ns as soon as the current
goes to zero; this is due to the rapid heat dissipation through
the TiN and W layers which have high thermal conductivities. Such fast heating and cooling rates in the range
109 1010 C/s is the key to achieving a reset state during
PCRAM device operation by melting the crystalline phase
and quenching the liquid phase to form a solid amorphous
Ge2 Sb2 Te5 phase; this is why the heat conduction modeling
is important. However, it is not clear why the temperature of
the Ge2 Sb2 Te5 layer is not constant but fluctuates somewhat
during the current-on period, as seen in Fig. 8b.
Finally, it should be noted that the temperature profiles
in Figs. 4, 6, 7, and 8 were calculated from the onedimensional heat conduction equation so that they are somewhat different from the actual ones. A multidimensional heat

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3542

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J. Appl. Phys., Vol. 94, No. 5, 1 September 2003

By introducing an additional heater layer of 5 nm thickness between the TiN heater and the Ge2 Sb2 Te5 layers, it has
been shown that a reset operation is possible at the required
current level of 2 mA. Moreover, the model predicts that a
low-current operation of 1 mA can be realized in a 0.15 m
8F 2 memory cell when the thermal conductivity of an additional heating layer is lower than that of Ge2 Sb2 Te5 and its
electrical resistivity is as high as 106 cm. It is thought
that such a memory cell with a heater layer with low- and
medium- elec values is a good candidate for a low-current
high-density PCRAM device. Finally, it is believed that the
model is a useful tool for estimating the operation characteristics of PCRAM devices with various plug structures.

FIG. 8. a A current pulse of 50 ns width and b the resulting temperature


profile vs current-flow time t, and distance x for the memory cell of Fig. 5
with a TiN-heater/a-C ( 0.2 W/m K and elec106 cm)/Ge2 Sb2 Te5
structure with a 1 mA current.

conduction model is being developed to obtain more realistic


temperature profiles. Furthermore, the reset currents for various resistive heating materials will be experimentally measured and compared with the model.
V. CONCLUSION

A one-dimensional heat conduction model has been developed for a PCRAM device with a 0.15 m 8F 2 memory
cell structure in order to evaluate the required current level
for a reset operation. When a TiN heater only is considered
with a 0.15 m contact hole, the temperature at the interface
between the TiN and Ge2 Sb2 Te5 layers is far lower than the
melting temperature of Ge2 Sb2 Te5 632 C even with a resistivity of 1000 cm and thermal conductivity of 0.44
W/m K, making the write operation impossible. This is so
because the TiN is a good electrical and thermal conductor.

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