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ESE-2015 : TEST SERIES

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UPSC Engineering Services Examination

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Subjectwise Test No. 6 (Conventional) : Elec. Machines & Microprocessors

EXPLANATIONS
1. (a)
At 300 V, e.m.f.

E1 =

V IR

= V I(Ra + Rse) = 300 (90) (0.1 + 0.05)

= 300 13.5 = 286.5 V
the equivalent resistance,

R =

I1

(0.2)(0.05)
= 0.04
(0.2) + (0.05)

0.2

=
I = 0.8 I
0.2 + 0.05

For constant load torque,

Ia1 1

= Ia2 2

(90)2

= (Ia2) (0.8 Ia2)

1 Ia1 and 2 0.8 Ia2

(90)2
0.8

Ia22

Ia 2

= 100.62 A

E2 = Ia 2 (Ra + R) = 300 100.62 (0.1 + 0.04) = 285.9 V

E1
E2
and new speed,

Ia1 n1
1 n1
=
2 n2 0.8 Ia 2 n2

ESE-2015 : TEST SERIES

ELELCTRICAL ENGINEERING

n2 =

(285.9 90 900)
(286.5 0.8 100.62)

= 1004 rpm
1. (b)
Rotor emf makes 120 complete cycles per minute, hence the frequency of the rotor emf and current

f2 =

120
= 2 Hz
60

stator current frequency = f = 50 Hz

f2 = sf

slip

= s=

f2
2
=
= 0.04
50
f

synchronous speed,

Ns =

120f 120 50
=
= 1000 rpm
P
6

rotor speed,

N = (1 s)Ns = (1 0.04) 1000 = 960 rpm

=

2N 2 960
=
= 100.53 rad/s
60
60

shaft power output

= T = 160 100.53 = 16.085 kW
Mechanical power developed

Pm = (160 + 10) 100.53 = 17.09 kW

Rotor copper loss,
0.04
s
17.09
Pm =
Pcu =

1 0.04
1 s

= 0.712 kW
(i) Input to the motor,

Pin = Pm + Pcu + stator loss = 17.09 + 0.712 + 0.8

= 18.602 kW
(ii) Efficiency of the motor,

shaft power
100 = 16.085 100
motor input
18.602

= 86.47%
2. (a)

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= 1

Losses
Output + Losses

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Test 6 (Conventional) : Electrical Machines & Microprocessors

At full load,

or

0.98

= 1

Pc + Psc =

Pc + Psc
(2,00,000) (1 ) + Pc + Psc

4000
= 4081.63 W
0.98

... (i)

At half full load,

2

0.98

or

Pc +

1
P
4 sc

= 1

1
Pc + Psc
2
2

1
1
(2,00,000) (1) + Pc + Psc
2
2

2000
= 2040.81 W
0.98

... (ii)

From equation (i) and (ii),

Pc = 1360.54 W
Psc = 2721.09 W

and

Voltage regulation at full load = r cos 2 + x sin 2

or
Given,

0 .04

= r 0.8 + x 0.6

cos 2

= 0.8

sin 2

= 0.6

r (re)p.u.
r

... (iii)

2721.09
Ohmic loss at rated current
=
200,000
Rated VA

= 0.0136

Put the value of r in equation (iii)

0.04
x

= 0.0136 0.8 + x 0.6

= 0.0485 p.u.

reL() = re p.u.
xeL()

RcL =

0.0485 (384)2
= 0.035
200,000

(VL )2
(384)2
=
= 108.38
Pc
1360.54
384
VL
=
= 3.54 A
108.38
RcL

Ic

Ic

= Ie cos 0

3.54

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0.0136 147456
(384)2
=
= 0.010027
200,000
200,000

= Ie 0.2

Ie

= 17.7

Im

= Ie sin 0 = 17.7 0.979 = 17.34 A

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ESE-2015 : TEST SERIES

ELELCTRICAL ENGINEERING

XmL =

VL
384
=
= 22.14
Im
17.34

equivalent circuit referred to L.V side

j0.036

3.54 A = Ie

0.01

Im = 17.34 A

108.38

j22.14

2. (b)
(i) Motor operation:
Ia

Vt E a
128 125
=
= 150 A
0.02
Ra

in the motor direction, and the power input at the motor terminal is

Vt Ia = 128 150 = 19.20 kW

The electromagnetic power is given by

Ea Ia = 125 150 = 18.75 kW

The electromagnetic torque

Tmech =

Ea Ia
m

18.75 103
100

= 59.7 N-m
(ii) Generator operation:
Ia

E a Vt 125 124
=
= 50 A
0.02
Ra

the terminal power is

VtIa = 124 50 = 6.20 kW

The electromagnetic power is

EaIa = 125 50 = 6.25 kW

the electromagnetic torque is

Tmech =

6.25 103
= 19.9 N-m
100
j Xs

3. (a)

Ia
+

Ia

(i)
pf angle,

10 103
3 400

= 14.43 A

= cos1(0.8) = 36.9 lag

+
Ef

Vt 0

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Test 6 (Conventional) : Electrical Machines & Microprocessors

Vt =

400
0 = 2310 V
3

Ia

= 14.4336.9 A

Ef

= V t + (j Xs ) (Ia )
= 231 0+ j16 (14.43 36.9) = 413.2 26.5 V

Ef

= 413.2 V and = 26.5

Pe = Power supplied

(ii)

= 10 0.8 = 8 kW
excitation emf is raised by 20%

Ef = 1.2 413.2 496 V

Pe =

8 103
3

Torque angle

Ef Vt
sin
Xs
496 231
sin
16

= = 21.9

Ef Vt 0
49621.9 2310
=
jX s
j16

Ia

Ia

= 18.4 51 A

Stator current
Power factor

Ia = 18.4 A

= cos51 = 0.63 lagging

3. (b)

Pi = Iron-loss
Pc = copper-loss
at maximum efficiency,

Pi = Pc
max

P0
100
P0 + Pi + Pc

P0 = 15 1 = 15 kW [upf]

max

P0
P0 + 2Pi

0.98

15
15 + 2Pi

Pi = 0.153 kW

Full-load copper loss,

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2

(Pc)f l

20
20
= Pi = 0.153
15
15
= 0.272 kW

Iron loss remains constant

W i = Pi 24 = 24 0.153

so,

= 3.672 kWh
(i) Full-load for 4 hours, upf

P0 = 20 1 = 20 kW (output)
(W0)1

= 20 4 = 80 kWh

Pc = (Pc)f l = 0.272 kW
(Wc)1

= 0.272 4 = 1.088 kWh

(ii) 0.4 full-load, at upf for 20 hour

P0 = 0.4 20 1 = 8 kW
(W0)2

= 8 20 = 160 kWh

Pc = (0.4)2 (Pc)f l = 0.16 0.272

= 0.0435 kWh
(Wc)2

= 20 0.0435
= 0.87 kWh

W0 = (W0)1 + (W0)2
= 80 + 160 = 240 kWh

Wc = (Wc)1 + (Wc)2 = 1.088 + 0.87

= 1.958 kWh

W i = 3.672 kWh
Winput = W0 + Wi + Wc = 240 + 3.672 + 1.958
= 245.63 kWh
all-day efficiency
=

240
W0
100
100 =
245.63
Winput

= 97.7%
4. (a)
Special purpose registers:
PC - program counter: Contains address of next instruction to be executed. Takes care of program control.
In execution of a program it increments according to length of instruction.
SP - Stack pointer: Contains the address of data present at top of the stack. Decrements when data is
stored in to stack and increments when accessed from stack.
IR - Instruction register: Contains opcode of present instruction.
FR - Flag register: has 5 flags to give status after execution of an ALU instruction. Sign, Zero, Auxiliary
Carry, Parity and carry flag.

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Test 6 (Conventional) : Electrical Machines & Microprocessors

Temporary registers: W & Z 8 bit registers

Only processor uses them.
Sum of E9 & 8B = 74H
74H = 01110100, flags - S-0, Z-0, AC-1, P-1, CY-1.
4. (b)
Interrupt is an internal or external signal which may alter the sequence of execution of a program.
1. Hardware and software
2. Maskable and non Maskable
3. Vectored and non vectored.
In 8085 there are 5 hardware and 8 software interrupts.
Hardware: TRAP, RST 7.5, RST 6.5, RST 5.5, INTR. Highest priority is TRAP, least priority is INTR.
Software interrupts:
RST 0 to RST 7
Except INTR, all are vectored interrupts, TRAP is the only non-Maskable interrupt. It is used for highly
prioritised event in practical applications.
Ex: any application of interrupts can be include.
5. (a)
Given instruction is MOV M, D
i.e. move the content of D register to memory (at the address of HL register pair)
[D ]

= 75 H ; [HL] = 9000 H

fCLK = 3 MHz.
Instruction is at 8000 H : MOV M, D.
It is 1 byte and requires 2 machine cycles or 7 T - states.

The first machine cycle is opcode fetch, and second is memory write operation.

The following is the required timing diagram, with control, status and timing signal.

PC program counter initially contains the address instruction i.e. 8000 H. It increments after opcode
fetch. In the second cycle / operation [HL] pair content, i.e. address is latched on to bus and D register
content is transferred to 9000 A.
Mocroprocessor
IR
XX
PC
8000
8001

H L
90 00

75

Memory
8000H

XX

9000H

75

Opcode
fetch

M/M write
D
75

IR = Instruction Register
PC = Program Counter

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ELELCTRICAL ENGINEERING

The above diagram shows the operation of MOV M, D in processor and memory.
Instruction cycle
Opcode Fetch
T1

T2

T3

T4

Memory write

T5

T6

T7

CLK
0.33 s

ALE
A15 A8

80H

Ad7 AD0

XX

00H

I0/M, s1, s0

90H

Unknown

75H

00H

IO/ M = 0; s1 = 0; s0 = 1

IO/ M = 0: s1 = s0 = 1

RD
WR

5.

(b)
Given,

Capacity
M/M to be designed

= 1024 8 = 1 KB
= 4 KB

M/M, a[ given as 6000 H 6 FFFH]

No. of 1KB chips required to design
4 KB
Required decoder

M / M to be designed 4 KB
=
=4
Available capacity
1KB

= 2:4
RD WR

A15

A0

A14
A13

CS0
1 KB
RAM

A12

A9

E
y0
A11

2:4
Decoder
A

CS1
1 KB
RAM

B
y1

A10

A0
A9

y2
y3

A0

CS2
1 KB
RAM

A9

A0

CS3
1 KB
RAM

A9
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Test 6 (Conventional) : Electrical Machines & Microprocessors

For 1 KB, 10 lines are required.

2n

= N

n No. of address line

N No. of address/ memory location
2n

= 1 KB = 210

n = 10
nx = y
n Total address lines of processor
x No. of lines required according to capacity of memory.

y Lines for decoding logic

n = 16 for 8085

Here,

2n

For 4 KB ;

= 4 KB = 22 (210) = 212

n = 12 = x

16 12

= 4

Decoding logic i.e. for 2 : 4 decoder

i /p

o/p

B A
A11 A10
0
0
1
1

CS/CE

0
1
0
1

y0 - CS0
y1 - CS1
y2 - CS2
y3 - CS3

chip select / stable - To select a memory chip.

A15 A14 A13 A12 A11 A10
0 1

0 0

0 1

0 1

0 1

1 0

0 1

1 1

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
1
6000 H - 63FF H
0 0 0
1 1 1
6400 H - 67FF H
0
1
6800 H - 6BFF H
0
1
6C00 H - 6FFF H

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