FPGA Based Sliding Mode Control for High Frequency Power Converters

S. Lentijo, S. Pytel, A. Monti, J. Hudgins, E. Santi, and G. Simin

Department of Electrical Engineering
University of South Carolina
Columbia, SC, 29208, USA
Email: [lentijo,pytel,monti,hudgins,santi,simin]@engr.sc.edu

Abstract Virtual prototyping is essentially the process of

incremental substitution of real hardware for simulation
models as the individual parts of hardware become available.
In this paper a standard, wide-bandwidth electrical power
interface is presented. The interface will use high-switchingspeed power switches, ultra fast ADC converters and a FPGA
platform. The high switching speed of the power switches
makes it possible to achieve extremely high closed-loop
bandwidth, but it requires additional effort in control
development. For this reason a discrete-time version of the
sliding mode control algorithm is implemented and tested.

I.

The simulation model defines the Rest Of the

System (ROS).
The simulation/hardware interface lies between the
two subsystems, acting as the power transducer
between the virtual and real worlds.

INTRODUCTION

Real-time HIL simulation replaces the emulated hardware

under test or control logic in the simulation model with real
hardware that interacts with the computer models. This
increases the realism of the simulation and provides access
to hardware features currently not available in software-only
simulation models. Advances in microprocessor technology
now make real-time simulation with HIL feasible for many
applications. Many experiments have been proposed in the
literature but most of them involve just signal
interconnections between systems.
In this paper we want to address a more challenging case
where the simulation/hardware interface occurs at a
connection where real power can be virtually exchanged
between the simulation and hardware. The significant
challenge in creating such an interface is to provide the wide
dynamic range and low latency that are required to track not
just a sinusoidal power waveform, but rather a heavily
distorted waveform having all of the warts and bumps
associated with a harmonic rich environment. These are the
extreme conditions under which real hardware is prone to
fail, and these are the conditions under which the
assumptions in simulation models most often collapse to
reveal deficiencies in the system design.
Figure 1, shows a mixed simulation/hardware system in
which the system under study is split into two subsystems,
one composed of a simulation model and the other
composed of real hardware. The simulation/hardware
interface links these two halves.
The real equipment constitutes the HardwareUnder-Test (HUT).

Figure 1. The scenario for Hardware in the Loop

The requirement that the interface must seamlessly link the

real and virtual worlds at the power interface introduces a
set of problems related to: sampling rate, delay and
quantization.
The unavoidable limitations of sampling rate and delay
define the stability envelope of the hybrid system. In order
to explore real power system issues (e.g. stability, response
to harmonics, impact of active power quality controls), it is
necessary to ensure very high bandwidth of the
simulation/hardware interface. This is straightforward with
respect to sensing because very fast digitizers with low
latency are readily available and high performance
computers can ensure sufficiently short computing delay.
But it is generally very difficult to implement the power
transducer because very fast power switches are not
generally available. Silicon technology is incapable of
meeting the extreme switching demands of such a power
interface. Since Gallium nitride (GaN) technology is best
suited for this application, the final version of this new
interface will use a GaN power cell, in the form of an
integrated H-bridge power block. . This GaN power cell will
take advantage of the III-V semiconductor material
properties. All the details related to this device are presented
in [1]. In this paper all the experimental results were
obtained with the first prototype of the interface that
consists of a silicon H-Bridge inverter.

To capitalize on the ultra-high switching bandwidth of the

GaN devices will require additional effort in control
development. The improvement in switching frequency
must be supported by an equivalent improvement in timeaccuracy to guarantee a good resolution of the output signal.
The risk is to increase the quantization effect due to the
PWM action on the current and voltage control. The sliding
mode control was selected as control algorithm because it
does not require a dedicated PWM unit: the output of the
algorithm is directly the switching command, and
theoretically it is not limited in bandwidth.
In order to meet the requirements the platform is mostly
digital and comprises a limited analog section based on a
fast analog to digital converter (ADC) and a signal
conditioning stage based on high speed operational
amplifiers. The rest of the system is fully digital. A PXI
embedded controller is used for interface and monitoring;
data acquisition and the fast control loop are implemented
with an FPGA. Figure 2 shows the general concept of the
entire platform.

to be controlled. The state space representation of the

system is:

x = Ax + Bu

y = Cx

(2)

where:

R
A= L
1

1
LC
0

1
B=
LC

C = [0 1]

By applying the discrete-time state space transformation [2],

the above continuous time system can be transformed into
the following discrete time system:

x(k + 1) = Az x(k ) + B z u (k )

y (k ) = Cx (k )

(3)

where:

A z = e ATs

Bz =

Ts

e
0

Bd

and Ts is the

sampling time.

Figure 3. Basic diagram of the H-Bridge Inverter

Figure 2. General scheme of the proposed platform

II.

III.

MODELING THE H-BRIDGE INVERTER

A full bridge inverter with an RLC output filter is shown in

Figure 3. Assuming ideal components, the power circuit is
modeled as a second order system and the equations of the
system are:

dit
u = Rit + L dt + v c

it = il + ic

dv c

ic = C
dt

DISCRETE-TIME SLIDING MODE CONTROL

The designed control operates with state feedback. The

controller design was originally reported in [3] and it has
been extended to a digital version in this paper. Figure 4
shows the control system block diagram.

(1)

The capacitor voltage vc and it derivative vc are chosen as

state variables, the system state vector is defined as
T
x = [vc vc ] and the capacitor voltage is the output quantity y
Figure 4. Control system block diagram

The state vector x of the system to be controlled is easily

measured and compared with the state vector of the
reference model. Then the reference state of x(k) can be
defined as follows:

x (k ) V sin( 2f 0 kTs )
x r = r1 = 0

x r 2 (k ) 2f 0V0 cos(2f 0 kTs )

(4)

a time step equal to 400ns, which emulates the real sampling

time of the FPGA. Part a) of Figure 6 shows the same
simulation mentioned above using a sampling time equal to
1s and part b) of the same figure shows the simulation
result using a sampling time equal to 0.1s. In part b of the
figure the ringing in the waveform was minimized, because
the sampling time was reduced.

where V0 and f0 are the amplitude and the frequency of the

reference sinusoidal output voltage respectively. The state
vector of the desired error can be defined
as x e ( k ) = x r ( k ) x ( k ) .
A switching law corresponding to a weighted mean of the
state errors is selected

s ( xe ) = (VREF VC ) + (VREF VC )

(5)

The control quantity depends on this expression according

to the following relationship

u = U max for s ( xe ) > 0

u = U min for s ( x e ) < 0

Figure 5. Power converter voltage with a 60 Hz sinusoidal waveform as

reference

(6)

The switching manifold is defined as:

s ( xe ) = 0

(7)

Now discretizing equation (5) with a sampling time Ts

s( xe ) = (VREF (k ) VC (k )) + (

VREF (k ) VREF (k 1) VC (k ) VC (k 1)
)

Ts
Ts

(8)

)(V REF ( k 1) VC ( k 1))

Ts

(9)

Figure 6. Output voltage under the sliding mode control

a) Ts = 1s, b) Ts = 0.1 s

Rearranging terms
s ( x e ) = ( +

Ts

)(V REF ( k ) VC ( k )) + (

Defining C1 and C2

C1 = +

Ts

V.

C2 =
Ts

we obtain the discretize version of the equation (5)

s ( xe ) = C1 * e(k ) + C 2 * e(k 1)
IV.

(10)

SIMULATION RESULTS

The system shown in Figure 4 is simulated using Virtual

Test Bed (VTB) [4]. The parameters of the H-Bridge
inverter are Vs=10V, L=0.5mH, C=10F. For the
simulation the hysteresis bandwidth is 0.01, and the time
step in the simulation emulates the sampling time of the
FPGA. The simulation response of the output voltage with a
nominal load of 51 under the sliding mode control
algorithm is show in Figure 5. This simulation is done with

EXPERIMENTAL RESULTS

The experiment uses a National Instruments PXI platform,

composed of a PXI-8176 Pentium III Embedded Controller,
and a PXI-7831 FPGA module. The power converter is an
H-Bridge inverter (Texas Instruments DRV592); the filter
parameters are L=10 H, C=10 F, and the DC link voltage
is 5V. The analog section of the experimental setup consists
of a fast ADC converter provided by Analog Devices (the
AD9218, a dual 10-bit 105-MSPS ADC), and a rescaling
circuit that uses the LT1364, a high gain-bandwidth product
operational amplifier (70MHZ) from Linear Technology.
The DRV592 is an H-bridge with gate drive circuitry
integrated into a small, surface-mount package. Figure 7 is a
modulation scheme of the DRV592. It takes a TTLcompatible logic level PWM input and provides current
gain. An LC output filter then averages the PWM output.
The input signal can range in frequency from dc to 1 MHz.
[8]

Figure 7. H-Bridge (TI DRV592) Modulation Scheme

The discrete sliding mode controller is programmed in

LabVIEW 7.0 using its FPGA module. In the scheme of the
overall controller there are two digital inputs, the reference
voltage and the measured voltage across the load, coming
from the 10 bit ADC. After this stage, the discrete sliding
mode controller is implemented as shown in Figure 4, and
finally the output command is sent to a digital output that
drives the power converter in the configuration shown in
Figure 7.
Several tests have been performed on the development
experimental system. The following figures present the
results obtained, using a sinusoidal reference with different
frequencies. The objectives of this test are ensuring the
correctness and robustness of the sliding mode algorithm.

a) Reference: 60 Hz sinusoidal

b) Reference: 500 Hz sinusoidal

c) Reference: 3 KHz sinusoidal

Figure 8. Power converter voltage under resistive load using a sinusoidal
reference with different frequencies

From Figure 8, we can conclude that the voltage across the

resistive load is properly following the sinusoidal reference
as expected, but it exhibits significant high frequency noise.
To reduce this noise, a high frequency filter is being added
to the output voltage measurement.
Applying the Fourier analysis to the experimental
waveforms shown in Figure 8, we obtained the following
figures that show that the distortion is widely spread all over
the spectrum so that there are no significant peaks apart
from the fundamental. (Figure 9)
However, from the energy standpoint, calculating the Total
Harmonic Distortion (THD) factor we get a value of about
30%. This value shows that there is still space for a
significant improvement in the quality of the waveform. On
the other hand the THD does not change with the frequency,
and this can be considered a significant achievement of the
sliding mode approach. It should also be pointed out that for
the experiment we adopted the 10 H inductance available
with the TI board. Simulation results show that increasing
the inductance the THD can be significantly improved
without any change to the control structure. As a
confirmation of that, a new simulation analysis has been
performed by using a filter inductance of 1mH and keeping
the rest of the system and the control unchanged. The results
of the Matlab post-processing shows for this case a THD of
4%. As Figure 6 shows the other option is to work on the
FPGA design to get an execution period of at least 100 ns.
Another interesting feature added in the control scheme is
the management of a digital output pin, which gives a
precise measurement of the computational time that the
FPGA needs to perform one cycle of the control algorithm.
In this case the computational time is 400ns as shown in
Figure 10. This means that the sliding mode controller is
taking a switching decision with a frequency equal to 2.5
MHz.

to the more challenging case of a GaN power cell, in the

form of an integrated H-bridge power block.
It is shown that using a FPGA to perform the control
algorithm gives some advantages related to execution time
that would be very difficult to achieve with a
microcontroller. This is very critical for an approach such as
sliding mode where a switching decision has to be taken at
every step. In previous experiment with PowerPC board it
was impossible to reach even 1 s of execution time.

a) Reference: 60 Hz sinusoidal

Figure 10. Computational time during one cycle in the FPGA

ACKNOWLEDGMENT

b) Reference: 500 Hz sinusoidal

This work was supported by the US Office of Naval

Research (ONR) under grant N00014-03-1-0940.
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c) Reference: 3KHz sinusoidal

Figure 9. Spectrum analysis from the waveforms shown in figure 8

VI.

[6]

CONCLUSION

The discrete-time sliding mode control approach reported in

this paper shows a successful implementation of this kind of
control algorithms for controlling a high-bandwidth power
converter, specifically an H-Bridge inverter, using and
FPGA. The high dynamics and the robustness of the
implemented system, demonstrated by simulation and
experimental results, represent a promising step towards the
final goal of applying the discrete-time sliding mode control

[7]
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