3818

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 7, JULY 2014

Universal Digital Controller for Boost CCM Power

Factor Correction Stages Based on Current
Rebuilding Concept
Victor M. Lopez, Student Member, IEEE, Francisco J. Azcondo, Senior Member, IEEE,
Angel de Castro, Member, IEEE, and Regan Zane, Senior Member, IEEE

AbstractContinuous conduction mode power factor correction

(PFC) without input current measurement is a step forward with
respect to previously proposed PFC digital controllers. Inductor
volt-second (vsL ) measurement in each switching period enables
digital estimation of the input current; however, an accurate compensation of the small errors in the measured vsL is required for
the estimation to match the actual current. Otherwise, they are accumulated every switching period over the half-line cycle, leading
to an appreciable current distortion. A vsL estimation method is
proposed, measuring the input (vg ) and output voltage (vo ). Discontinuous conduction mode (DCM) occurs near input line zero
crossings and is detected by measuring the drain-to-source MOSFET voltage vd s . Parasitic elements cause a small difference between the estimated voltage across the inductor based on input and
output voltage measurements and the actual one, which must be
taken into account to estimate the input current in the proposed
sensorless PFC digital controller. This paper analyzes the current
estimation error caused by errors in the ON-time estimation, voltage measurements, and the parasitic elements. A new digital feedback control with high resolution is also proposed. It cancels the
difference between DCM operation time of the real input current,
(TDg C M ) and the estimated DCM time (TDreCbM ). Therefore, the
current estimation is calibrated using digital signals during operation in DCM. A fast feedforward coarse time error compensation is
carried out with the measured delay of the drive signal, and a fine
compensation is achieved with a feedback loop that matches the
estimated and real DCM time. The digital controller can be used in
universal applications due to the ability of the DCM time feedback
loop to autotune based on the operation conditions (power level,
input voltage, output voltage. . .), which improves the operation
range in comparison with previous solutions. Experimental results
are shown for a 1-kW boost PFC converter over a wide power and
voltage range.

Fig 1. (a) Traditional PFC converter with current sensor. (b) Thermal image
at full load.

Fig. 2 (a) Typical PFC scheme with digital control and a current sensor.
(b) Analog to digital conversion circuit of the input current.

Index TermsBoost converter, continuous conduction mode,

digital control, digital error compensation, power factor correction, sensorless controller.

I. INTRODUCTION

Manuscript received December 20, 2012; revised March 10, 2013, May 10,
2013, and August 11, 2013; accepted August 16, 2013. Date of current version
February 18, 2014. Recommended for publication by Associate Editor S. K.
Mazumdar.
V. M. Lopez and F. J. Azcondo are with the Universidad de Cantabria, Santander 39005, Spain (e-mail: lopezvm@unican.es; azcondo@ieee.org).
A. de Castro is with the Universidad Autonoma de Madrid, Madrid 28049,
Spain (e-mail: angel.decastro@uam.es).
R. Zane is with the Department of Electrical Communication Engineering, Utah State University. Logan, UT 84322-4120 USA (e-mail: regan.zane@
usu.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2013.2280077

OME advantages that motivate the use of digital control in

PFC stages include: reduction of discrete components, reduction of size, reduction of sensitivity to parameter tolerances,
ease of controller implementation, and extension of its performance limits. A resistive sensor is the most commonly used
solution for current sampling. The power dissipated by this resistor causes a hot spot in the converter, as shown in Fig. 1. The
first criterion to determine the value of the resistor is often the
gain of the amplifier stage (see Fig. 2) [1]. Furthermore, the current analog-to-digital converter (ADC) must have a wide bandwidth, increasing the cost in comparison with voltage ADCs.
Current estimation techniques to reduce cost and maintain performance based on voltage measurements are presented in [2],
[5] for single-phase and multiphase converter applications,

0885-8993 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

LOPEZ et al.: UNIVERSAL DIGITAL CONTROLLER FOR BOOST CCM POWER FACTOR CORRECTION STAGES

3819

Fig. 3. Input voltage and power range of the recent works in sensorless PFC
controllers. The green area represents the goal of this study.

respectively. For PFC applications, several works have been

presented to avoid sensors or ADC chips in the converter, simplifying the control circuit. Approaches such as [6], [7] eliminate
the voltage sensor in the input or output voltage, [8] uses the
diode current as a variable to compute the duty cycle, and [9]
and [10] avoid the use of an ADC chip in the current acquisition,
but a current sensor is used. In [11], the current sensor is avoided
to detect zero current in a critical mode (CRM) boost converter.
In continuous conduction mode (CCM) boost PFC converters, the most recent works with current sensorless solutions to
obtain power factor correction are [12][17]. A digital PFC using analog comparators and no ADC is presented in [12], while
a predictive duty-cycle is presented in [13] and [14] with an
implementation in a DSP and in an FPGA, respectively. In [15]
and [16], the current loop is avoided with a sinusoidal input
voltage, while the same approach is improved in [17] under
distorted input voltage.
With the aforementioned controllers, high power factor value
and low THD of the input current (THDi) are achieved in the
voltage and power ranges presented for each reference in Fig 3
(according to the experimental results presented in each work).
Furthermore, the influence of the parasitic elements and the
effects of the nonidealities are not analyzed in detail. The green
area represents the goal of this study, which corresponds with
the typical range of commercial analog ICs [18] for CCM PFC
controllers (universal input voltage range and wide output power
range).
This study is based on the input current rebuilding concept [19][22]. The variable volt-seconds (vsL ) across the inductor is estimated in each switching period, and the small error
(current estimation error) accumulated per switching period over
the half-line cycle causes current distortion. The effect of the
switching delays is presented in [19]. One of the aims of this
study is to find a good tradeoff between resolution and speed, in
which the current estimation error is cancelled using a twofold
strategy:
1) a fast and coarse feedforward control to compensate automatically the effect of the switching delays, presented

Fig 4. (a) Basic model of the boost converter and (b) Boost converter current
estimator.

in the previous work [19], measuring these delays every

switching period;
2) a fine low-frequency feedback control, with high resolution, to compensate automatically the current estimation
error.
The error compensation strategy is found in the study and
modeling of the influence of the different sources of current
estimation error such as the parasitic elements and errors in the
voltage acquisition data. This analysis is the second objective
of the study.
This paper is organized as follows. In Section II, a brief
overview on input current estimation without a current sensor
is provided. Section III shows the estimation mismatch due to
errors in the capture of voltage data, which are due to tolerances
and offsets in the voltage measurement circuits (resistors, ADC,
etc.), the differences between the estimated inductance and the
real one, the influence of the parasitic elements, and delay in the
drive signal. The digital compensation technique of the errors is
described in Section IV, supported with simulation results. An
auxiliary circuit for DCM detection is presented in Section V
and applied to a novel feedback corrector of the estimation error
in Section VI. Experimental results are presented in Section VII
for a 1-kW boost converter operating over a wide range of input
voltage and load power.
II. DIGITAL CURRENT ESTIMATION WITHOUT
CURRENT SENSOR
Fig. 4(b) shows the simulation block diagram of the current
estimator implemented in a digital device, which represents a
behavioral model of the boost converter illustrated in Fig. 4(a).
The input and output voltages of the converter (vg and vo ) are applied to the inductance L, and define the real input current (ig ),
so they have to be measured and quantized to estimate the current value in the digital controller. The hardware scheme of the

3820

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 7, JULY 2014

TABLE I
LIST OF CORRESPONDENCE BETWEEN THE ANALOG
AND THE DIGITAL VARIABLES

TABLE II
EXPRESSION OF THE CURRENT RIPPLE FOR THE REAL
AND REBUILT INPUT CURRENT

Fig. 5. Digital signal ire b [k], compared with the analog real input current ig ,
under ideal conditions. The on-off signal is the output of the digital device and
v L the analog inductor voltage.

current estimator is presented in [19]. Digital input and output

voltage data (vg and vo ) have an LSB resolution (expressed in
volts per bit) represented by qg and qo , respectively, and given by
 
 
vg V
vo V
qg =
; qo =
.
(1)
vg bit
vo bit
The voltage across the inductor is defined by the power converter states (ON-state and OFF-state), designated in the current
estimator by the onoff signal that drives the power switch Q.
The result is in an estimated inductor voltage vL and a quantized rebuilt inductor voltage vL ,reb . The ON and OFF times
are initially known because they are generated by the controller.
The bin q represents the LSB resolution defined by the designer.
Ideally, qg = qo = q, but a real analog-to-digital conversion
causes a small difference between them
qg = q (1 g ) ;

qo = q (1 o )

(2)

where g and o are the per unit error of the input and output
analog-to-digital conversions, respectively.
Theoretically, the inductance L is known, but tolerances, temperature, switching frequency, and the inductor current cause a
difference between the estimated inductance (Lest ) and the real
one that depends on the core material. The inductor is modeled
as an integrator with a gain equal to the inverse of its inductance, whose output is the digitally rebuilt (estimated) input
current ireb . This signal ireb is used in the PFC current loop
instead of the real ig .
Table I shows the correspondence between the analog variables (actual variables in the converter) and their corresponding
digitally estimated variables expressed in the same units. These
variables define ig and ireb according to the expressions presented in Table II, where ig and ireb are the peak-to-peak
current ripple of the real and rebuilt input current, respectively.
If the analog and digital variables are equivalent, with vg =
vg q, vo = vo q, being q = qg = qo , L = Lest and ton = ton , then
both currents agree (ireb = ig ) when neglecting quantization
effects. The waveforms are as depicted in Fig. 5, where ireb [k]
represents the estimated current in the clock cycle k, and i
reb [j]

and i
g (jTsw ) are the estimated and real current at the end
of the switching cycle j (valley values), respectively. In this
situation, there is no current estimation error, defined as the
difference between ig and ireb , ierror = ig ireb , and therefore
ireb corresponds with an accurate quantization of ig .
At the beginning of the line voltage semicycle, ireb = ig = 0.
Since the input current is not measured, the line zero crossings
are the only points where the real current is known. Small errors
in the digital variables compared with the analog (see Table I)
cause a current estimation error in each switching period j. The
dominant current estimation errors are due to:
1) voltage data errors due to the tolerances of the voltage
dividers, noise, offset, quantization process, or nonlinearity of the ADCs (vg = vg q and/or vo = vo q and/or
qg = qo = q);
2) the difference between the estimated inductance (Lest )
and the real one (L);
3) the influence of the parasitic elements (RL , Ron , RD ,
VD );
4) delays in the drive signals (ton = ton ).
All of these errors are described separately in Section III,
where the current estimation error caused by these different
situations is modeled.
III. MODELING THE CURRENT ESTIMATION ERRORS
To simulate the effect of the different causes of error and
perform a first validation of the model, the system has been
modeled with the switching converter in PLECS and the behavioral control algorithm in Simulink as shown in Fig. 6.
The real input current ig and estimated input current ireb are
solved for CCM operation according to Fig. 7 and the current
estimator presented in Figs. 4 and 6. Analytical expressions

at the end of each switching period j, i

g (jTsw ) and ireb [j]
respectively, are given by

i
g (jTsw ) = ig ((j 1) Tsw ) +

i
reb

[j] =

i
reb

Tsw
[j 1] +
L

Tsw
{vg [j] vo [j] d [j]}
L
(3)

vg [j] q vo [j] q 

d [j]
qg
qo


(4)

LOPEZ et al.: UNIVERSAL DIGITAL CONTROLLER FOR BOOST CCM POWER FACTOR CORRECTION STAGES

3821

Fig. 6. Simulations Blocks in Simulink with PLECS toolbox. (Bottom)

PLECS subcircuit in Simulink with the current estimator. (Top) Boost converter
in PLECS with a block to simulate the drive signal delays.

Fig. 8. Steady-state simulated waveforms with the Simulink/PLECs model of

the system with V g = 230 V rm s , V o = 400 V d c , P o = 640 W, fsw = 72 kHz,
L = 1 mH, and C = 220 F, when q = 0.4617 V/bit, qg = 0.4620 V/bit,
qo = 0.4624 V/bit (Top) Real and estimated currents. (Bottom) current error
obtained from the model and from (6).

Fig. 7. Digital estimated current ire b [k] compared with the analog real input
current ig under errors in data capture voltage across the inductance when
qg = qo = q. The on-off signal is the output of the digital device and v L the
analog inductance voltage.

Fig. 9. Digital estimated current ire b compared with the analog real input
current ig , when the estimated inductance value L e st is higher than the real
L. The on-off signal is the output of the digital device, and v L the inductance
voltage.

where (1 d[j]) is notated as d [j], and constant voltage values

are assumed over each switching period j. The current estimation error, defined as ierror = ig ireb , is evaluated after n
switching periods, as the accumulation of the difference between
(3) and (4)

ierror [n] =






j =n 
Tsw 
q
q
vg [j] 1
vo [j] 1
d [j] .
L j =0
qg
qo
(5)

The error from (5) can be expressed as a function of ireb


qg
1
ierror [n] = ireb [n]
q


j =n 
qg
Tsw 

+
1
vo [j]d [j]
L j =0
qo


(6)

and it is possible to calculate the value of the real input current

after n switching periods as


j =n 
qg
Tsw 
qg

+
1 .
ig [n] = ireb [n]
vo [j]d [j]
q
L j =0
qo
(7)
Expressions (6) and (7) have two different terms. The first
term defines a current proportional to ireb , which is the variable
controlled by the PFC controller and ideally has a sinusoidal
shape. Therefore, the first term does not create distortion (harmonics) in ig . The second term is not sinusoidal and nonzero
when qg = qo , causing current distortion and decreasing the
power factor. Fig. 8 shows the simulation of ireb and ig at
the top of the figure, and the simulated current error ierror,sim
compared with the modeled error defined by (6), ierror , when
qg = qo = q, at the bottom.
The second cause of error analyzed in this study is due to the
difference between the real inductance (L) and the estimated
one Lest . The behavior of the sensorless boost converter is illustrated in Fig. 9 in the switching periods j and j + 1 when L

3822

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 7, JULY 2014

Fig. 10. Steady-state simulated waveforms with the Simulink/PLECS model of the system with V g = 230 V rm s , V o = 400 V d c , P o = 640 W, fsw =72 kHz,
and C = 220 F, when q =qg =qo for (a) L = 1 mH and L e st = 1.8 mH, and (b) nonlinear inductance L = 1.50.147ig [mH], L e st = 1.0 mH.

= Lest and qg = qo = q, i.e., considering the inductance error

only.
According to Fig. 9, the current values are defined at the end
of the switching period j by

i
g (jTsw ) = ig ((j 1) Tsw ) +

i
reb [j] = ireb [j 1] +

Tsw
{vg [j] vo [j] d [j]} (8)
L

Tsw
{vg [j] vo [j] d [j]} .
Lest

(9)

Comparing (8) and (9), the relation between ireb and ig yields
to expressions (10) and (11) for ig and ierror , respectively. As it
has been addressed before, ireb is the variable controlled by the
PFC control algorithm, so it has a sinusoidal shape (proportional
to the input voltage). Considering L constant over the line cycle,
ig is sinusoidal too, and no current distortion appears despite the
current estimation error, as it is presented in Fig. 10(a). Fig. 10(b)
shows the current waveforms with a nonlinear current dependent
inductance L(i) [23], as is the case of one of the inductors built
with a soft-saturation core used in the experimental results. The
model of soft-saturation inductor used in this study is presented
in [24], which considers the permeability dependence on the
magnetizing force
Lest
L


Lest
1 .

ig = ireb
ierror = ireb

Fig. 11.

Boost converter diagram with parasitic elements.

The last cause of current distortion analyzed in this study is

the influence of the parasitic elements. Fig. 11 shows the model
of the boost converter with parasitic elements, RL being the
effective series resistor of the inductor, VD and RD the forward
voltage at zero current and the ON-state resistor of the power
diode, and Ron the MOSFET ON-resistance.
The controller varies the duty cycle d such that the average
input current over the switching period is ig  = vg /Re , where
the emulated resistance Re is chosen by the controller to obtain
the desired dc output voltage. By solving the volt-second balance
in L, assuming the small-ripple approximation
vg  vo  (1 d) = RL ig  + Ron ig  d
+ RD ig  (1 d) + VD (1 d). (13)

(10)
(11)

Substitutingig  = vg /Re in (13), it is possible to solve the

command d given by the PFC controller to obtain a sinusoidal
current [25]
v

Up to this point, it can be seen that the difference between

qo and qg causes current distortion and decreases the PF value
because it means a difference between the V/bit resolution in the
ON-state and in the OFF-state, and consequently, a difference
in the A/bit also. To analyze the behavior of the PFC controller
with the current estimator, it is assumed that q = qg and Lest =
L, and the current error accumulated in n switching periods is
defined by


j =n 
qg
Tsw 

ierror [n] =
1 .
vo [j]d [j]
L j =0
qo

(12)

d=

vg (RL + RD ) Rge VD vo
v

(Ron RD ) Rge VD vo

(14)

Defining vpar as the average voltage drop across the parasitic
elements, in each switching period
vpar  = RL ig  Ron ig  d RD ig  (1 d)
VD (1 d) = vo (1 d) vg

(15)

and substituting (14) into (15), we get



vo (Ron + RL Re )
vpar  = vg
1 . (16)
vg (Ron RD ) (VD + vo ) Re

LOPEZ et al.: UNIVERSAL DIGITAL CONTROLLER FOR BOOST CCM POWER FACTOR CORRECTION STAGES

3823

Fig. 14. Auxiliary circuit used to adapt the drain-to-source voltage as a digital
signal. Comparison with the on-off signal and the drive signals delays to n -o
and to n -o .

on-time modification in the switching period j

ierror [n] =
Fig. 12. Simulated current waveforms without consideration of the parasitic
elements influence. (Top) Real and rebuilt input current. (Bottom) Simulated
current estimation error.

j
=n
j =1

vo [j]
ton [j] .
L

(17)

IV. DIGITAL CORRECTION OF THE CURRENT

ESTIMATION ERRORS

Fig. 13. Digital signals estimated current ire b [k] compared with the analog
real input current ig , with on-time modification to n for the switching periods
j and j+1. The on-off signal is the output of the digital device and the inductor
voltage, v L .

Fig. 12 shows ig  and ireb  waveforms when the estimated volt-seconds across the inductor is lower than the actual
one due to the noncompensation of the parasitic effects with
Vg = 230 Vrm s , Vo = 400 Vdc , Po = 640 W, fsw = 72 kHz
and reactive components L = 1 mH and C = 220 F. The parasitic elements are RL = 0.3 , RD = 0.2 , VD = 0.6 V, and
Ron = 0.18 . These values are obtained from the datasheets
of the RHRP860 Fairchild Power Diode and the IRFP27N60K
International Rectifier Power MOSFET, the switching devices
used in the laboratory prototype. It can be observed that the
current estimation error, ig is not sinusoidal, with PF = 0.770
and THDi = 44%.
An additional error in the estimated volt-seconds applied to
the inductor is caused by time errors and is addressed in [19],
where it is concluded that they are mainly due to the difference
between the ON-time applied in the real converter (ton ) and
the estimated ON-time, ton . The effect of this time-error is
illustrated in Fig. 13, defining ton [j] = ton [j] ton [j] as the

Two compensation strategies, working at the same time,

are presented in this section. The first one is time compensation, meaning an improvement in comparison with the previous work [19]. The ON-time error ton [j] is measured every
switching period, and it is compensated by accounting for it
when the digital circuit calculates the required on-time in every switching period. In this case, as is presented in [20], an
auxiliary circuit, which includes a resistor divider and a signal
diode, is used to detect the drain-to-source voltage drop across

) which
the power MOSFET and obtain the digital signal (vds
indicates the real ONOFF transitions in the boost converter, as
is presented in Fig. 14.

The digital controller compares the onoff signal with vds

to measure the ON-time modification every switching period
(ton [j] = tono [j] to on [j]) in terms of clock periods of the digital circuit.
This strategy constitutes a coarse and fast feedforward compensation of the volt-seconds error caused by a time error.
The resolution of the ton measurement depends on the clockperiod of the digital device and the minimum error is Tclk /2
[22]. For the boost parameters presented before and a 10 ns
(Tclk /2 = 5 ns) clock period, the current error accumulated
in half line cycle, i.e., nu switching periods, is ierror [nu ] =
1.40 A, where nu =fsw /(2fu ). The clock-frequency is a bottleneck in this controller because it fixes the minimum ton
value. Higher fsw leads to higher current estimation error [19].
A second error compensation strategy is proposed, based on
the modification of the current estimator block presented in
Fig. 4. The new approach is presented in Fig. 15. It consists of
introducing a new digital signal vdig , which modifies the output
voltage signal vo in the current rebuilding algorithm.
Assuming q = qg , the signal vdig means a modification of vL
in each switching period given by (18)
vdig  = vdig qg (1 d) .

(18)

3824

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 7, JULY 2014

Fig. 15.

Behavioral model of the modified current estimator.

Fig. 16. Simulation results with the proposed compensation setting v d ig =

/qg with V g = 230 Vrm s , V o = 400 Vd c , P o = 640 W, fsw = 72 kHz and
reactive components L = 1 mH, and C = 220 F. The values of the parasitic
elements are R L = 0.3 , R D = 0.2 , V D = 0.6 V, R o n = 0.18 .

If it is considered only the effect of the parasitic elements, the

value of vdig that compensates this effect is obtained comparing
(16) and (18) to assure vpar  = vdig , resulting in

vdig =
=

1 vo (Ron + RL ) + VD Re vg (Ron RD )
qg
Re (Ron + RL )

(19)

Vo (Ron + RL ) + VD Re Vg (Ron RD )
.
Re (Ron + RL )

(20)

Expression (19) describes a waveform almost constant over

the line cycle. Neglecting the output voltage ripple vo Vo , and
considering Ron RD , the new signal can be approximated as
vdig = /qg , where is a constant defined by (20). Fig. 16
shows the simulation of the error compensation using vdig with
Vg = 230 Vrm s , Vo = 400 Vdc , Po = 640 W, fsw = 72 kHz
and reactive components L = 1 mH, and C = 220 F. The
parasitic elements are RL = 0.3 , RD = 0.2 , VD = 0.6 V,
and Ron = 0.18 . The resulting power factor is 0.997 with
THDi = 1.78%, improving the results obtained in Fig. 12.
With the vdig signal added to the current estimator, not only
the influence of the parasitic elements is compensated but also
the current error due to qg = qo . Note that both sources of error
cause equivalent ierror shape.

Fig. 17. Auxiliary circuit for the actual DCM detection and waveforms.
(a) Hardware architecture. (b) Circuit waveforms.

V. DISCONTINUOUS CONDUCTION AUXILIARY

DETECTION CIRCUIT
Accumulated current estimation error over the half-line cycle
causes input current distortion, decreasing the power factor. As
it has been shown in Figs. 8 and 12, when it happens the time
in which discontinuous conduction mode (DCM) occurs is a
parameter that enables the detection of discrepancy between
ireb and ig .
An auxiliary circuit, capable of detecting the converter mode
of operation (CCM or DCM) is presented in this study. Fig. 17
shows the hardware architecture(see Fig. 17(a)) and the circuit
behavior (see Fig. 17(b)). A digital signal DCMig , indicates the
converter operation mode by its logic level (e.g., DCMig = 0
for CCM operation and DCMig = 1 for DCM operation). This
circuit, similar to the one described in [26] and [27], compares
the output voltage vo , with the MOSFET drain-to-source voltage
vds (previously used to measure the drive signal delays), adapted
with two equal resistor dividers (Rds1 = Ra , Rds2 = Rb ). In
CCM operation, vds > vo (due to the influence of the parasitic
elements) during the whole OFF-time, but this is not true in
DCM operation. Drain-to-source voltage vds , adopts a value
close to the input voltage as soon as input current ig reaches
zero. But the inherited parasitic elements of the power switches
cause oscillations in the drain-to-source voltage around vg [28].

LOPEZ et al.: UNIVERSAL DIGITAL CONTROLLER FOR BOOST CCM POWER FACTOR CORRECTION STAGES

Fig. 19.

Fig. 18. Experimental waveforms. Input voltage v g , real input current ig

waveforms and digital signals DCMig and DCMire b for: (a) eD C M < 0, then
ire b > ig , and (b) for eD C M > 0and then ire b < ig .

The comparator output signal x1 , is registered at the beginning

of the switching period using the onoff signal rising edge,
which is internally available in the digital device. If x1 is high
at this sample instant, the boost converter is operating in DCM
(DCMig = 1). Conversely, if sampled x1 is low, the converter
is operating in CCM (DCMig = 0).
In the case of the digitally rebuilt input current ireb , the
signal DCMireb , indicates whether ireb = 0 at the beginning
of the switching period. DCM operation is estimated when
DCMireb = 1 and CCM operation is estimated when
DCMireb = 0.
VI. HIGH RESOLUTION FEEDBACK LOOP
ANALYSIS AND STABILITY

g
reb
TDCM
.
eDCM = TDCM

Block diagram of the proposed controller.

situation with eDCM > 0 is shown with ig > ireb , where it is

necessary to decrease vdig .
To obtain a universal PFC controller that compensates all the
current estimation errors, the proposed the new feedback loop
g
reb
= TDCM
. A block diagram of the
adjusts vdig to match TDCM
proposed control loop is presented in Fig. 19. The DCM time
error eDCM is the input of a compensator, which modifies its
output signal, vdig , until the DCM times match, i.e., eDCM = 0.
At the same time, this new feedback loop compensates with
high resolution for the estimation errors not compensated by the
feedforward strategy, due to the Tclk /2 resolution of the ton
measurement (addressed in Section IV). In this study, 10-bit
ADCs are used and vdig is a 14-bit signal. Therefore, the output

in Fig. 15)
voltage signal used to estimate the input current (vo2
has 14 bits (4 LSB added). The current error for a given vdig is
defined by
ierror [n] =

Recent works [12][17], [19] avoid the input current measurement and propose a PFC digital control that includes the
measurement of the parasitic elements (RL , VD , RD , Ron ) and
applies a duty cycle command d, according to these elements, or
simply neglects their influence. But parasitic elements influence
change with the temperature, frequency, and the components
used in the PFC converter. It can be observed that in these
previously proposed solutions for sensorless PFCs use high inductance values and low switching frequencies in comparison
with the state-of-the-art of CCM PFCs that include a current
sensor.
reb
,
The estimated input current ireb , presents a DCM time, TDCM
g
while ig has a different DCM time, TDCM . A distortion in ig
g
reb
leads to TDCM
= TDCM
reducing the power factor. The compensator for current estimation error captures DCMig and DCMireb
g
reb
and measures and compares TDCM
with TDCM
to obtain the
DCM time error eDCM ,
(21)

Thus, an indirect measurement of the current estimation error is obtained by eDCM . The output voltage loop assures the
desired output voltage vo , and depending on the vdig value, two
different situations, shown in Fig. 18, can occur. If eDCM < 0
(see Fig. 18(a)), then ig < ireb, and it is necessary to increase
vdig to match DCM times. On the other hand, in Fig. 18(b), the

3825

j =n
Tsw 
{(qg vdig ) d [j]}
L j =0

(22)

which is zero if vdig = /qg . Due to the finite resolution, the digital controller sets a value vdig = /qg 1 LSB. This 1 LSB
uncertainty in vdig represents an accumulated current error in the
last switching period nu of the half line cycle of, ierror [nu ] =
0.15 A, with the parameters previously presented. The new
feedback loop has a resolution of one order magnitude higher
that the feedforward compensation, resulting in ierror [nu ] =
1.40 A, limited by the digital device clock-period as presented
in detail in [22].
The output voltage loop in a PFC controller has a typical
bandwidth around fc = 510 Hz to set vo according to a reference. To not interfere with this, the DCM time compensation
loop has a lower bandwidth, using a sample period equal to Ts =
1/fc . With this assumption, a complete derivation of the model
is presented in detail in [30], where the model of the system
(plant) is given by

2
1

Mg2
K
(23)

and Mg = Vg 2 Vo and K = 2fsw L/R. Using a PI compensator, KPI /(z 1), the Jury stability criterion defines the range
of values of KPI for a stable system as
g
(s)
TDCM
1
Vo L (fu )2
= z 1 with =
vdig (s)

0 > KPI >

(24)

3826

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 7, JULY 2014

Fig. 22. Experimental results for the DCM condition detection circuit for the
real input current.

Fig. 20. (a) Schematic diagram of the Boost PFC Converter. (b) Laboratory
prototype.
Fig. 23. Comparison of the harmonic content with the limits defined by the
Standard IEC 61000-3-2 for Classes A, C, and D.
TABLE III
POWER FACTOR AND THDI FOR DIFFERENT CONDITIONS

Fig. 21. Experimental results: ON-time (top) and the duty cycle modification
(to n ) due to the drive signal delays acquisition (bottom) over the half line
cycle.

VII. EXPERIMENTAL RESULTS

A 1-kW boost converter with the proposed digital feedback
loop and feedforward time compensation has been built and
tested to illustrate the behavior of the auxiliary circuit that captures the drain-to-source voltage and the performance of the

error compensation. The circuit scheme and a picture, which

correspond to the experimental prototype, are shown in Fig. 20.
In comparison with traditional digital PFC controllers, the current sensing circuit is replaced here by two resistor dividers, a
signal diode and a comparator. The output voltage reference is
400 Vdc with an input voltage rangingfrom 85 to 250 Vrm s

LOPEZ et al.: UNIVERSAL DIGITAL CONTROLLER FOR BOOST CCM POWER FACTOR CORRECTION STAGES

3827

Fig. 24. Experimental results. (a) V o = 400 Vd c , L1 = 1 mH and R L 1 = 0.25 . Left: V g = 230 V rm s (50 Hz), Pg = 970 W. Right: V g = 85 Vrm s (60 Hz),
Pg = 320 W. (b) V o = 400 V d c , L2 = 1.5 mH and R L 2 = 0.35 . Left: V g = 230 Vrm s (50 Hz), Pg = 970 W. Right: Vg = 85 Vrm s (60 Hz), Pg = 320 W.

Fig. 25. Experimental results. eD C M time evolution under a 970 to 640 W

load step down.

(universal input voltage range). The switching frequency is

72 kHz. To demonstrate the universal nature of the proposed
approach, two different inductors were built and the results were
achieved without modifying any parameter of the digital controller. The first inductor was built with an RM12-3C90 core, resulting in inductance L1 = 1 mH and RL 1 = 0.25 . The second
inductor was built with a soft saturation Kool m core 77071.
In this case, the inductance L2 = 1.5 mH and RL 2 = 0.35 .
Both inductors were measured with a HP 4284A precision LCR
meter at 75 kHz and 5 A DC bias current. The output capacitor
C = 220 F, the MOSFET, and diode used to built the prototype
are IRFP27N60K from International Rectified with Ron = 0.18

and RHRP860 Power Diode from Fairchild with VD = 0.6 V

and RD = 0.2 . The laboratory prototype was built to work
under wide voltage and current ranges and shows the behavior
of the controller under different operating conditions without
changing the components. The digital PFC controller and the
feedback loop were described in VHDL and implemented in a
Xilinx XC3S200E field programmable gate array (FPGA). A
nonlinear-carrier (NLC) controller [29] was used in this case
as PFC controller technique, controlling the rebuilt input current
ireb . A second order ad hoc sigma delta ADC [19] was used to
sample the output voltage and a commercial TLV1572 serial
10-bit ADC was used for the input voltage.
The ON-time and the ON-time modification (ton ) due to the
drive signal delays over the half-line cycle are shown in Fig. 21
for different loads (320, 480, and 970 W). The delay is a function
of the MOSFET gate resistance, drain current, and the MOSFET
parasitic elements. With the auxiliary circuit shown in Fig. 14,
ton is measured each switching period and the active time of
the drive signal is compensated instantaneously [19], [20].
Fig. 22 shows the main waveforms of the DCM condition
detection circuit for the real input current with Rds1 = Ra =
1.2 M and Rds2 = Rb = 9.31 k. The digital signal, DCMig
changes to 1 when the first DCM oscillation in the drain-tosource voltage occurs. Experimental and simulated waveforms
are in good agreement as shown in Fig. 17.
The experimental results in steady-state operation are shown
in the waveforms of Fig. 23 for different input voltages (85
Vrm s 60 Hz and 230 Vrm s 50 Hz), output power and both
inductances (L1 and L2 ). It is observed that DCM times are
matched and sinusoidal input current is achieved. Power factor

3828

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 7, JULY 2014

and total harmonic distortion of the input current (THDi) values

are listed in Table III for input voltage ranging from 85 Vrm s
60 Hz to 250 Vrm s 50 Hz at different output power, fulfilling
the goal set in Fig. 3. A comparison of the harmonic content at
nominal conditions (230 Vrm s 50 Hz, 1 kW) with the limits
defined by IEC 61000-3-2 for Classes A, D, and C is shown in
Fig. 23.
Measured THDi values are a little lower with L1 than with
L2 . This is caused by the current dependent inductance of the
inductor built with a soft saturation core [23]. The aim of using
this inductance in the proposed controller is to show the behavior
of the controller under two different conditions. The use of
L2 on one hand introduces a nonlinear behavior that produces
higher current distortion as the current increases and on the
other hand keeps the CCM operation for a higher load range.
Despite this aspect, the experimental results demonstrate high
power factor for all the tested conditions. It is important to note
that the digital controller has not been re-tuned to operate under
the different conditions. This shows the universal nature of the
approach presented in this study with switching frequency and
inductance similar to traditional and commercial analog PFC
designs.
The time evolution of the eDCM value under a load step
down (970640 W) is shown in Fig. 24. After the error value
peak which occurs when the load step is applied, the fine error
feedback loop modifies vdig , compensating the DCM times error
reaching a steady-state condition with eDCM = 0 in around
6 s. During the transient time with eDCM = 0 not excessive
deterioration of the power factor occurs due to the feedforward
compensation of the estimation error. The value of = 60.3
and gain of the PI controller has been settled to KPI = 1.
VIII. CONCLUSION
A universal current sensorless controller for Boost PFC stages
operating in CCM has been presented. The current is digitally
rebuilt in a digital device and this digital signal is used in the PFC
current loop. Making the most of the digital control capabilities,
the traditional current sensing analog circuit is substituted by
a simpler circuit (two resistor dividers and a comparator) that
detects the DCM condition in the input current by translating
the pulsated drain-to-source voltage into a digital signal, searching for the best tradeoff between the circuit complexity versus
resolution and speed response. With this circuit, an indirect measurement of the current distortion is obtained by comparing the
actual and estimated DCM times.
The effect of the parasitic elements in the input current estimation for sensorless PFC boost digital controllers operating
in CCM has been analyzed. In this case, the current estimation
is carried out by measuring the input, output, and MOSFET
drain-to-source voltages.
The error between the estimated and actual DCM periods
close to the zero crossing of the input voltage is a key variable
to accurately correct the error in the estimation of the input current and the consequent distortion. An auxiliary circuit detects
DCM condition in the input current comparing drain-to-source
voltage with the output voltage during the MOSFET OFF-time.

The single digital signal acquired from the MOSFET drain-tosource voltage drop is used by both the feedforward and feedback compensators. The feedforward one represents a coarse
compensation of current estimation errors due to time delays.
And the new feedback loop generates a constant digital signal
to compensate current estimation errors, modifying the output
voltage measurement used to estimate the input current, and
minimizes this DCM time error. This feedback loop autotunes
the value of the digital signal when the converter operates in a
wide load or voltage range with a high resolution, resulting in
an average real input current proportional to the input voltage
in each switching period. A universal Boost PFC digital controller is achieved without current measurement, so in the point
of view of the designer the complexity of the PFC controller
decreases. With this feedback loop, parasitic element values do
not need to be measured and are compensated for automatically,
representing a step forward in comparison with the previous
works about PFC sensorless controllers. The prototype has been
tested with two different inductors (linear and nonlinear), and
the experimental results show, in both cases, high power factor with reliable performance under different load and voltage
conditions.
REFERENCES
[1] B. Mammano, Current sensing solutions for power supply designer, in
Proc. Unitrode Power Supply Seminar SEM-1200, 1997.
[2] P. Midya, P. Klein, and M. F. Greuel, Sensorless current mode controlAn observer-based technique for DCDC converters, IEEE Trans. Power
Electron., vol. 16, no. 4, pp. 522526, Jul. 2001.
[3] Y. Qiu, X. Chen, and H. Liu, Digital average current digital average
current-mode control using current estimation and capacitor charge balance principle for DC-DC converters operating in DCM, IEEE Trans.
Power Electron., vol. 25, no. 6, pp. 15371545, Jun. 2010.
[4] M. Rodriguez, J. Sebastian, and D. Maksimovic, Average inductor current
sensor for digitally-controlled switched-mode power supplies, in Proc.
Energy Convers. Cong. Expo., 2010, pp. 780787.
[5] Z. Lukic, Z. Zhenyu, S. M. Ahsanuzzaman, and A. Prodic, Self-tuning
digital current estimator for low-power switching converters, in Proc.
Appl. Power Electron. Conf., Feb. 2008, pp. 529534.
[6] B. A. Mather and D. Maksimovic, A simple digital power-factor correction rectifier controller, IEEE Trans. Power Electron., vol. 26, no. 11,
pp. 919, Jan. 2011.
[7] S. M. Park, Y. D. Lee, and S. Y. Park, Voltage sensorless feedforward
control of a dual boost PFC converter for battery charger applications, in
Proc. Energy Convers. Cong. Expo., 2011, pp. 13761380.
[8] Z. Yang and C. Paresh, A novel technique to achieve unity power factor
and fact transient response in AC-to-DC converters, IEEE Trans. Power
Electron., vol. 16, no. 6, pp. 764775, Nov. 2001.
[9] M. Rodriguez, M. V. M. Lopez, F. J. Azcondo, J. Sebastian, and
D. Maksimovic, Average inductor current sensor for digitally controlled
switched-mode power supplies, IEEE Trans. Power Electron., vol. 27,
no. 8, pp. 37953806, Aug. 2012.
[10] J. W. Shin, B. H. Cho, and J. H. Lee, Average current mode control
in digitally controlled discontinuous-conduction-mode PFC rectifier for
improved line current distortion, in Proc. Appl. Power Electron. Conf.
Expo., 2011, pp. 7177.
[11] Y. S. Roh, Y. J. Moon, J. C. Gong, and C. Yoo, Active power factor
correction (PFC) circuit with resistor-free zero-current detection, IEEE
Trans. Power Electron., vol. 26, no. 2, pp. 630637, Feb. 2011.
[12] K. I. Hwu, H.W. Chen, and Y. T. Yau, Fully digitalized implementation
of PFC rectifier in CCM without ADC, IEEE Trans. Power Electron.,
vol. 27, no. 9, pp. 40214029, Sep. 2012.
[13] W. Zhang, G. Feng, Yan-Fei Liu, and B. Wu, A digital power factor
correction (PFC) control strategy optimized for DSP, IEEE Trans. Power
Electron., vol. 19, no. 9, pp. 14741485, Nov. 2004.
[14] W. Zhang, G. Feng, Yan-Fei Liu, and B. Wu, A digital power factor
correction (PFC) control strategy for power factor correction and FPGA

LOPEZ et al.: UNIVERSAL DIGITAL CONTROLLER FOR BOOST CCM POWER FACTOR CORRECTION STAGES

[15]
[16]
[17]
[18]
[19]
[20]

[21]

[22]

[23]
[24]

[25]
[26]

[27]

[28]

[29]
[30]

implementation, IEEE Trans. Ind. Electron., vol. 21, no. 6, pp. 1745
1753, Nov. 2006.
H.-C. Chen, Duty phase control for single-phase boost-type SMR, IEEE
Trans. Power Electron., vol. 23, no. 4, pp. 19271934, Jul. 2008.
H-C Chen, Single-loop current sensorless control for single-phase boosttype SMR, IEEE Trans. Power Electron., vol. 24, no. 1, pp. 163171,
Jan. 2009.
H-C Chen, C-C Lin, and J-Y Liao, Modified single-loop current sensorless control for single-phase boost-type SMR with distorted input voltage,
IEEE Trans. Power Electron., vol. 26, no. 5, pp. 13221328, May 2011.
Fairchild Semiconductor. (2012, Dec. 5). Power factor correction. [Online]. Available: Internet: http://www.fairchildsemi.com/products/pfc/
F. J. Azcondo, A. de Castro, V. M. Lopez, and O. Garcia, Power factor
correction without current sensor based on digital current rebuilding,
IEEE Trans. Power Electron., vol. 25, no. 6, pp. 15271536, Jun. 2010.
V. M. Lopez, F. J. Azcondo, F. J. Diaz, and A. de Castro, Autotuning
digital controller for current sensorless power factor corrector stage in
continuous conduction mode, in Proc. Control and Modeling for Power
Electron., 2010, pp. 18.
V. M. Lopez-Martin, F. J. Azcondo, and A. de Castro, Current error compensation for current-sensorless power factor corrector stage in continuous
conduction mode, in Proc. Control and Modeling for Power Electron.,
2012, pp. 18.
V. M. Lopez-Martin, F. J. Azcondo, and A. de Castro, High-resolution error compensation in continuous conduction mode power factor correction
stage without current sensor, in Proc. Power Electron. Motion Control
Conf., 2012, pp. 18.
Magnetics powder core catalog. (2011). [Online]. Available http://www.
mag-inc.com/File%20Library/Product%20Literature/Powder%20Core%
20Literature/2011-Magnetics-Powder-Core-Catalog-2012-Update-.pdf
V. M. Lopez, A. Navarro-Crespin, R-Schnell, C. Branas, F. J. Azcondo,
and R. Zane, Current phase surveillance in resonant converters for electric discharge applications to assure operation in zero-voltage-switching
mode, IEEE Trans. Power Electron., vol. 27, no. 6, pp. 29252935, Jun.
2012.
R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics,
2nd ed. Berlin, Germany: Springer Science + Business Media Inc, 2001.
J. Morroni, L. Corradini, R. Zane, and D. Maksimovic, Adaptive tuning
of switched-mode power supplies operating in discontinuous and continuous conduction modes, IEEE Trans. Power Electron., vol. 24, no. 11,
pp. 26032611, Nov. 2009.
Fu-Zen Chen and D. Maksimovic, Digital control for improved efficiency
and reduced harmonic distortion over wide load range in boost PFC rectifiers, IEEE Trans. Power Electron., vol. 25, no. 10, pp. 26832692, Oct.
2010.
K. De Gusseme, D. M. Van de Sype, K. De Gusseme, D. M. Van de
Sype, A. P. M. Van den Bossche, and J. A. Melkebeek, Input-current
distortion of CCM boost PFC converters operated in DCM, IEEE Trans.
Ind. Electron., vol. 54, no. 2, pp. 858865, Apr. 2007.
D. Maksimovic, Y. Jang, and R. Erickson, Nonlinear-carrier control for
high-power boost rectifiers, IEEE Trans. Power Electron., vol. 11, no. 4,
pp. 578584, Jul. 1996.
V. M. Lopez-Martn and F. J. Azcondo, Modeling of a high resolution
DCM times feedback loop for sensorless boost PFC stages, in Proc.
Control and Modeling for Power Electron., 2013, pp. 16.

Victor Manuel Lopez (S10) was born in Torrelavega, Cantabria, Spain, in 1985. He received the
Electronics and Control Engineering degree from
the University of Cantabria, Santander, Spain, in
2009, where since then he has been working toward
the Ph.D. degree in the Department of Electronics
Technology, Systems and Automation Engineering
(TEISA).
From June to September 2012, he was a Visiting Scholar in the Colorado Power Electronics Center (CoPEC), University of Colorado at Boulder, and
from September to December 2012 in the Utah State University Power Laboratory, at Logan, Utah. Both periods with the Prof. Regan Zane as advisor. His
research interests include design, modeling, and digital control of topologies for
acdc converters and for resonant inverters.
Mr. Lopez received the IEEE/IEL Electronic Library Award in 2009.

3829

Francisco J. Azcondo (S90M92SM00) received the electrical engineering degree from the Universidad Politecnica de Madrid, Madrid, Spain, in
1989, and the Ph.D. from the University of Cantabria,
Spain, in 1993.
From 1995 to 2012, he has been an Associate
Professor in the TEISA Department, ETS II y T, University of Cantabria, Cantabria, Spain, where he has
been a Professor since 2012. He has been a Visiting
Researcher at the Department of Electrical, Computer, and Energy Engineering, University of Colorado, Boulder, CO, USA, from Feberuary to August 2004 and 2010, the Department of Electrical Communication Engineering, the University of Toronto,
ON, Canada, during the summer 2006, and the Power Electronics Lab (UPEL)
at Deptartment Electrical Communication Engineering, Utah State University,
Logan, UT, USA, from June to September 2013. Since Feberuary 2004, he is
Special Member (appointed as graduate faculty) at the Department of Electrical,
Computer, and Energy Engineering, University of Colorado Boulder, renovated
until spring 2017. He has been the Chair of the IEEE IES PELS Spanish
Joint Chapter from September 2008 to June 2011. His research interests include
modeling and control of switch-mode power converters and resonant converters,
digital control capabilities for SMPS, current sensorless control for power factor
correction stages and applications such as outdoor lighting, electrical discharge
machining, and arc welding.

Angel de Castro ( M08) was born in Madrid, Spain,

in 1975. He received the M.Sc. and the Ph.D. degrees in electrical engineering from the Universidad
Politecnica de Madrid, Madrid, Spain, in 1999 and
2004, respectively.
He has been an Associate Professor in the Universidad Autonoma de Madrid since 2010, and as
Assistant Professor from 2006 to 2010. Previously,
he was an Assistant Professor in the Universidad Politecnica de Madrid since 2003. His research interests
include digital control of switching mode power supplies, power factor correction, and field programmable gate arrays.

Regan Zane (SM07) received the Ph.D. degree in

electrical engineering from the University of Colorado, Boulder, CO, USA, in 1999.
He is currently a USTAR Professor in the Department of Electrical and Computer Engineering
at Utah State University (USU), Logan, UT, USA.
Prior to joining USU, he was a faculty member at
the Colorado Power Electronics Center, University of
Colorado-Boulder, from 2001 to 2012, and Research
Engineer at GE Global Research Center, Niskayuna,
NY, USA, from 1999 to 2001. He has recent and ongoing projects in bidirectional power converters for dc and ac micro-grids, high
step-down power converters for dc distribution systems such as high efficiency
data centers, advanced battery management systems (BMS) for electric vehicles,
LED drivers for lighting systems and low power energy harvesting for wireless
sensors.
Dr. Zane received the NSF Career Award in 2004 for his work in energy
efficient lighting systems, the 2005 IEEE Microwave Best Paper Prize for his
work on recycling microwave energy, the 2007 and 2009 IEEE Power Electronics Society Transactions Prize Letter Awards for his work on modeling of
digital control of power converters and the 2008 IEEE Power Electronics Society Richard M. Bass Outstanding Young Power Electronics Engineer Award.
He received the 2006 Inventor of the Year, 2006 Provost Faculty Achievement,
2008 John and Mercedes Peebles Innovation in Teaching, and the 2011 Holland
Teaching Awards from the University of Colorado. He currently serves as Associate Editor for the IEEE Transactions on Power Electronics, Letters, and as
the Publicity Chair for the IEEE Power Electronics Society.