Format: QP09

KCE/DEPT.OF ECE

UNIT-I MINIMIZATION TECHNIQUES AND LOGIC GATES

PART A (2 MARKS)
1. Prove the boolean theorems: x+x=x , x.x=x .
x + x = (x + x) 1
= (x + x)(x + x)
= x + xx
=x+0
=x
xx = x by duality.

(AU AM 2015)

2. What are the dont care minterms.

(AU AM 2015)
In some applications, the Boolean function for certain combinations of the input
variables is not specified. The corresponding minterms (maxterms) are called don't care
minterms (maxterms).In K-map , the don't care minterms/maxterms are represented
by d.
3. Draw the CMOS inverter circuit

4. Convert 0.35 to equivalent Hexa Decimal number

Solution:
0.35 x 16= 5.6 | 5
0.6 x 16= 9.6 | 9
0.6 x 16= 9.6 | 9
=(59)16

(AU ND 2014)

(AU MJ 2014)

5. State De Morgans theorem.

(AU MJ 2014)-3
De Morgans theorem is nothing but ,it suggests two theorems that form important
part of Boolean algebra. They are,
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Theorem 1: the complement of a product is equal to the sum of the complements.

Theorem 2: The complement of a sum term is equal to the product of the complements.
.
6. Apply De Morgans theorem to [(A+B)+C]
De Morgans theorem:

(AU MJ 2014)

Solution: [(A+B)+C] = [(A+B).C]

= [(A.B).C]
= A.B.C
7. What are Dont care terms?
(AU MJ 2013)
In some logic circuits certain input conditions never occur, therefore the
corresponding output never appears. In such cases the output level is not defined, it can be
either high or low. These output levels are indicated by X or d in the truth tables and are
called dont care conditions or incompletely specified functions.
8. What are the advantages of CMOS?
The advantages of CMOS is,
Reduce the complexity of the circuit
Low static power consumption
High noise immunity
High density of logic functions on a chip

(AU MJ 2013)

9. List the names of universal gates. What are its advantages?

The NAND and NOR gates are called as the universal gates.
The advantages of universal gates is,
These gates are used to perform any type of logic application.

(AU ND 2013)-2

10. What is Prime Implicant?

(AU ND 2013)-2
A prime implicant is a product term obtained by combining the maximum possible
number of adjacent squares in the map,so it can not be conbined with any other minterm or
group, so it is called as Prime Implicant.
11. State Distributive Law.
(AU ND 2013)
The distributive property states that AND ing several variables and OR ing the result
with single variable is equivalent to OR ing the single variable with each of the several
variables and then AND ing the sums. This distributive property is

12. Simplify the given Boolean expression F =x+xy+xz+xyz

F = x+x(y+ z+zy)
= x+(y+ z+yz)
(A+AB=A+B)
= x+y+z(1+y)
= x+y+z
(1+A=1)
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(AU ND 2012)

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13. Implementation the given function using NAND gates F(

KCE/DEPT.OF ECE

) = m(0,6)
(AU ND 2012)

14. What is a totem output?

(AU ND 2011)
A pushpull output is a type of electronic circuit that uses a pair of active devices that
alternately supply current to, or absorb current from a connected load, so it is called as
totem output.
15. Define fan in and fan out characteristics of digital logic families.
(AU AM 2011)
Fan in: It is defined as, the number of inputs connected to the gate without any
degradation in the voltage level.
Fan out: It is defined as, the maximum number of inputs of the same family that the
gate can drive maintaining its output levels within the specified limits.
16. Convert : (a) (520)10 (b) (1101.1101)2.
Solution:
(a) (100001000)2 (b) (13.13)10.

(AU ND 2010)

17. Draw an active-high tri-state buffer and write its truth table.

(AU AM 2010)

18. Prove that the logical sum of all minterms of a Boolean function of 2 variables is 1.
(AU ND 2009)
ab+ab'+a'b+a'b'
= a(b+b')+a'(b+b')
=a+a'=1
You know that x+ x' =1
19. What is syndrome?
(AU ND 2009)
If the check bits do not match the stored parity, they generate the unique pattern,
called a syndrome that can be used to identify the bit that is in error,so it is called as
Syndrome.
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20. Show that a positive logic NAND gate is a negative logic NOR gate.
Positive NAND
Input
Output
0,0
1
0,1
1
1,0
1
1,1
0
Negative NOR
Input
Output
0,0
1
0,1
1
1,0
1
1,1
0
Output is the same.
PART B

(AU MJ 2009)

1. (i) With suitable examples, explain the conversion of standards forms to canonical forms of
Boolean expression.
(5) (AU AM 2015)
Answer Key:
Simplification of the Boolean Expression
(3)
Boolean Law
(2)
(ii) Implement the given Boolean function F=xy+xy+yz using with NAND gate and inverter
gates.
(6)
Answer Key:
Simplification of the Boolean Expression
(3)
Boolean Law
(3)
(iii) Verify, whether or not EXOR operation is commutative and assosiative.(5)
Answer Key:
Simplification of the Boolean Expression
(3)
Boolean Law
(2)
2. (i) Show the five variable Karnaugh map and explain the minimization technique.
Answer Key:
(8) (AU AM 2015)
K-map Implementation
(5)
Simplify the Boolean Expression
(5)
(ii) Simplify the following expression using K-map method.
F(A,B,C,D) = (0,2,3,5,7,8,9,10,11,13,15).
Answer Key:
K-map Implementation
Simplify the Boolean Expression
3. (i) Convert the following function into Product of Maxterms
F(A,B,C)=(A+B)(B+C) (A+C)
Answer Key:
Simplification of the Boolean Expression
Boolean Law
(ii) Using quine mcclusky method simplify the given function
F(A,B,C,D)=m(0,2,3,5,7,,11,13,14)
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(8)

(4)
(4)
(8)

(AU ND 2014)

(4)
(4)

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4.

5.

6.

7.

8.

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Answer Key:
Arrange all minterms according to the number of 1s &
Combine the minterms into a group of two.
(2)
Combine the minterm pairs into groups of four
(2)
Collect all non checked form
(2)
Prepare the PI table and obtain the EPIs.
(2)
(i) Draw the multiple level two input NAND circuit for the following expression
F=(AB+CD)E+B(A+B)
(4)
(AU ND 2014)
Answer Key:
Simplification of the Boolean Expression
(2)
Boolean Law
(2)
(ii) Draw and explain tri-state TTL inverter circuit diagram and explain its operation
Answer Key:
(12)
Explanation
(6)
Circuit Diagram
(6)
(i) Given Y(A,B,C,D)=m(0,1,3,5,6,7,10,14,15), draw the K map and obtain the simplified
expression. Relize the minimum expression using basic gates.
(8)
(AU MJ 2014)
Answer Key:
K-map Implementation
(4)
Simplification of the Boolean Expression
(4)
(ii) Implement the expression Y(A,B,C)=m(0,2,4,5,6), Using only NOR-NOR logic.
Answer Key:
(4)
K-map Implementation
(2)
Simplification of the Boolean Expression
using NOR-NOR logic
(2)
(iii) Implement EXOR gate using only NAND gates.
Answer Key:
(4)
Explanation
(2)
Circuit Diagram
(2)
Simplify
the
following
function
using
Tabulation
method
Y(A,B,C,D)=
m(0,1,2,5,6,7,8,9,10,14) and implement using only nand gates.
(16) (AU MJ 2014)
Answer Key:
Arrange all minterms according to the number of 1s
(2)
Combine the minterms into a group of two.
(4)
Combine the minterm pairs into groups of four
(2)
Collect all non checked form
(4)
Prepare the PI table and obtain the EPIs.
(4)
(i) Simplify xy + x z + yz.
(6)
(AU ND 2013)
Answer Key:
Simplification of the Boolean Expression
(3)
Boolean Law
(3)
(ii) Simplify the following expression using K-map method.
Y = (7,9,10,i 1,12,13,14,15).
(10)
Answer Key:
K-map Implementation
(6)
Simplification of the Boolean Expression
(4)
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KCE/DEPT.OF ECE

9. (i) Write short notes on dont care conditions

(6)
(AU ND 2013)
Answer Key:
Explanation
(4)
Example
(2)
(ii) Explain about NAND and NOR implementations
(10)
Answer Key:
Explanation
(6)
Logic Diagram
(4)
10. Simplify the given Boolean function intoProduct of sum form and implement if using basic
gates.
F(A,B,C,D)=(0,1,2,5,8,9,10)
(16) (AU MJ 2013)
Answer Key:
K-map & Simplification
(8)
Logic Diagram
(8)
11. Minimize the given switching function Quine-Mcclusky method.
f(x1, x2, x3, x4 )=(0,5,7,8,9,10,11,14,15).
(16) (AU MJ 2013)
Answer Key:
Arrange all minterms according to the number of 1s
(2)
Combine the minterms into a group of two.
(4)
Combine the minterm pairs into groups of four
(2)
Collect all non checked form
(4)
Prepare the PI table and obtain the EPIs.
(4)
12. (i) Express the Boolean function as
(1) POS form
(2) SOP form
D = (A + B) (B + C)
(4) (AU AM 2010)
Answer Key:
Change POS form
(2)
Change SOP form
(2)
(ii) Minimize the given terms M (0, 1, 4, 11, 13, 15) + d (5, 7, 8) using Quine-McClusky
methods and verify the results using K-map methods
(12)
Answer Key:
Minimization using K-map
(2)
Arrange all minterms according to the number of 1s
(2)
Combine the minterms into a group of two
(2)
Combine the minterm pairs into groups of four
(2)
Collect all non checked form
(2)
Prepare the PI table and obtain the EPIs
(2)
13. (i)Implement the following function using NOR gates. Output = 1 when the inputs are
m(0,1,2,3,4) = 0 when the inputs are m(5,6,7)
(8) (AU AM 2010)
Answer Key:
K-map Implementation
(3)
Simplify the Boolean Expression
(2)
Logic Diagram
(3)
(ii) Discuss the general characteristic of TTL and CMOS logic families (8)
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Answer Key:
TTL Characteristiscs
(4)
CMOS logic Characteristics
(4)
14. (i) Express the Boolean function F = XY + XZ in product of Maxterm. (6)
(AU ND 2009)
Answer Key:
General form
(2)
Simplification
(4)
(ii)Reduce the following function using K-map technique )
f (A, B, C, D) = (0, 3, 4, 7, 8, 10, 12, 14) + d (2, 6) .
(10)
Answer Key:
K-map
(6)
Simplification
(4)
15. Simplify the following Boolean function by using Quine Mcclusky method
F(A,B,C,D)= (0, 2, 3, 6, 7, 8, 10, 12, 13).
(16) (AU ND 2009)
Answer Key:
Arrange all minterms according to the number of 1s
(2)
Combine the minterms into a group of two
(4)
Combine the minterm pairs into groups of four
(2)
Collect all non checked form
(4)
Prepare the PI table and obtain the EPIs
(4)

16. (i)Express the Boolean function F=A+B C in a sum of minterms

(06) (AU AM 2011)
Answer Key:
Simplification of Boolean Expression
(3)
Boolean Law
(3)
(ii)Simplify the Boolean function using K-map F(w,x,y,z)= (0,1,2,4,5,6,8,9,12,13,14)
(10) (AU AM 2011)
Answer Key:
K-map Implementation
(5)
Simplify the Boolean Expression
(5)
17. (i)Simplify the following Boolean function by using a Quine-McCluskey method. F(A,B,C,D) m(0,2,3,6,7,8,10,12,13)
(08) (AU AM 2011)
Answer Key:
Arrange all minterms according to the number of 1s
(2)
Combine the minterms into a group of two
(2)
Combine the minterm pairs into groups of four
(2)
Prepare the PI table and obtain the EPIs
(2)
(ii)Draw the schematic and explain the operation of a CMOS inverter.Also explain its
characteristics.
(08)
Answer Key:
Circuit diagram
(3)
Explanation
(3)
Characteristics
(2)

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KCE/DEPT.OF ECE

UNIT-II COMBINATIONAL CIRCUITS

PART A (2 MARKS)
1. What do you mean by weighted code ?
(AU AM 2015)
In weighed codes, each digit position of the number reperents a specific weight for
example in decimal code, if number is 567 the weight of 5 is 100, weight of 6 is 10 and
weight of 7 is 1. In weighed binary codes each digit has weight 8,4,2 or 1, so it s called as
weighted codes.
2. Draw the symbol and truth table for JK flip flop.

0
0
1
1

0
1
0
1

(AU AM 2015)

Qn+1
Qn
0
1
Qn

3. Draw the logic circuit for a 2bit comparator.

(AU MJ 2014)

4. What is priority encoder?

(AU MJ 2014)
A priority encoder is a circuit or algorithm that compresses multiple binary inputs into
a smaller number of outputs. The output of a priority encoder is the binary representation
of the original number starting from zero of the most significant input bit so it is called as
priority encoder.
5. Enumerate some of the combinational circuits.
The list of the combinational circuits are
1. Encoder
5. Adder
2. Decoder
6. Substractor
3. Multiplexer
7. Code converters
4. Demultiplexer
8. Comparator
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(AU ND 2013)

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KCE/DEPT.OF ECE

6. List out various applications of Multiplexer.

Some of the applications of multiplexer are as follows:
1. It is used as selector to select one out of many data inputs.
2. They are used in A/D and D/A converter.
3. They are in Time and Frequency multiplexing systems.
4. They are used in data acquisition systems.

(AU ND 2013)

7. Design Half substractor using basic gates.

(AU MJ 2013)

8. Draw the logic diagram of a 4 line to 1 line Multiplexer.

(AU MJ 2013)

9. Draw the logic diagram of serial adder.

(AU ND 2012)

10. Design a three bit even parity generator.

Logic diagram:

(AU ND 2012)

Truth table:
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Sl.No.
1
2
3
4
5
6
7
8

0
0
0
0
1
1
1
1

Message
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Parity
0
1
1
0
1
0
0
1

11. Implement the following function using a multiplexer F(A,B,C)=(1,3,5,6)

Form the above given problem, n=3 i.e., number of variables 3.
(AU ND 2011)
n-1
Total no.of inputs = 2
= 23-1 = 4

A
A

I0
0
4
0

I1
1
5
1

I2
2
6
A

I3
3
7
A

12. Write down the truth table of a full subtractor.

D=Bin +(A+B);
Bout =B+Bin +B Bin
INPUTS
OUTPUTS
A
B
Bin
D
Bout
0
0
0
0
0
0
0
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
1
1
1
1

(AU ND 2011)

13. Write the logic expression for the difference and borrow of a half subtractor.
Logic equations are:
(AU AM 2011)

14. Design a single bit magnitude comparator to compare two words A and B.
(AU AM 2011)

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15. Distinguish between a decoder and demux.

(AU ND2010)
Decoder
Demultiplexer
1. Decoder has many inputs to many
1. Demultiplexer has one input to
output devices.
many output devices.
2. There are no selection lines
2. The selection of specific output line
is controlled by the value of
selection lines.
16. Write an expression for borrow and difference in a full Subtractor circuit.
Logic equations are:
(AU AM 2010)

17. Draw the circuits diagram for 4 bit Odd parity generator.
The function of the 4 bit odd parity generator is P= (AB)(CD)

(AU AM 2010)

18. Suggest a solution to overcome the limitations on the speed of an Adder.(AU ND 2009)
It is possible to increase speed of adder by eliminating inter-stage carry delay. This
method utilizes logic gates to look at the lower-order bits of the augend and addend to see if
a higher-order carry is to be generated.
19. What is the difference between half adder and full adder?
Half adder

HA

2 inputs & 2 outputs

(AU MJ 2009)

Full adder
FA

3 inputs & 2 outputs

It performs half addition. So the It performs three inputs double the half
output is 22
adder.
Sum=AB+AB=A+B
Sum=C in+ (A + B)
Carry=AB
Carry=AB+BCin+CinA

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20. Differentiate a decoder from a demultiplexer.

(AU ND 2009)
Decoder
Demuliplexer
Many inputs to many outputs One input to many outputs device.
device.
They are no selection lines
Selection of specific output line is
controlled by the value of selection line.

1.

2.

3.

4.

5.

DE20

PART B
(i) Deisgn and implement an 8x1 multiplexer using suitable gates.
(16) (AU AM 2015)
Answer Key:
Explanation
(4)
Block Diagram
(4)
Explanation
(4)
Block Diagram
(4)
(i) Design a 4 bit decimal adder using 4 bit binary adders.
(8)
(AU ND 2014)
Answer Key:
Explanation
(4)
Block Diagram of 4 bit decimal adder
(4)
(ii) Implement the following boolean functions using multiplexers
(8)
F(A,B,C,D)=m(0,1,3,4,8,9,15)
Answer Key:
K-map Implementation
(4)
Simplify the Boolean Expression using multiplexers
(4)
(i) Design a 4bit magnitude comparator with 3 outputs : A>B,A=B,A<B.(8)
(AU ND 2014)
Answer Key:
Truth Table
(4)
Explanation
(2)
Logic Diagram
(2)
(ii) Construct a 4bit even parity generator circuit using gates.
(8)
Answer Key:
Truth Table
(4)
Explanation
(2)
Logic Diagram
(2)
(i)Design a 3:8 decoder using basic gates.
(8)
(AU MJ 2014)
Answer Key:
Truth Table
(4)
Explanation
(2)
Logic Diagram
(2)
(ii)Design a binary to gray code converter.
(8)
Answer Key:
Truth Table
(4)
Explanation
(2)
Logic Diagram
(2)
(i)Design a full subtractor using Demultiplexer.
(8)
(AU MJ 2014)
Answer Key:
K-map Implementation
(4)
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KCE/DEPT.OF ECE

Simplify the Boolean Expression using multiplexers

(4)
(ii)Explain the working of Carry look ahead adder.
(8)
Answer Key:
Explanation
(4)
Logic Diagram
(4)
6. Draw the logic diagram of BCD to Decimal decoder and explain its operations.
(16) (AU ND 2013)
Answer Key:
Truth Table
(4)
Explanation
(6)
Logic Diagram
(6)
7. Draw the block schematic of Magnitude Comparator and explain its operations.
(16) (AU ND 2013)
Answer Key:
Explanation
(8)
Block Diagram
(8)
8. Design a BCD adder and explain its working with necessary circuit diagram.
(16) (AU MJ 2013)
Answer Key:
Explanation
(8)
Block Diagram
(8)
9. Design a 4 bit magnitude comparator and draw the circuit.
(16) (AU MJ 2013)
Answer Key:
Explanation
(4)
Block Diagram
(8)
Circuit Diagram
(8)
10. (i)Draw the logic diagram of a 2-bit by 2-bit binary multiplier and explain its operation.
(8) (AU AM 2011)
Answer Key:
Explanation
(4)
Logic Diagram
(4)
(ii) Implement the following function using suitable multiplexer.
F(A,B,C,D)- (1,3,4,11,12,13,14,15)
(8) (AU AM 2011)
Answer Key:
K-Map Implementation
(4)
Logic Diagram
(4)
11. (i) Design a full Adder using two half adders and an OR gate.
(6) (AU AM 2011)
Answer Key:
Boolean Equation
(2)
Logic Diagram
(4)
(ii) Explain the operation of a BCD Adder.
(10) (AU AM 2011)
Answer Key:
Boolean Equation
(4)
Logic Diagram
(6)

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12. (i)Derive the equation for a 4-bit look ahead carry adder circuit.
(6) (AU AM 2010)
Answer Key:
Derivation
(3)
Logic Diagram
(3)
(ii)Draw and explain the block diagram of a 4-bit serial adder to add the contents of two
registers.
(10)
Answer Key:
Block Diagram
(5)
Explanation
(5)
13. (i)Multiply (1011)2 by (1101)2 using addition and shifting operation so draw block diagram
of the 4-bit by 4 bit parallel multiplier.
(8) (AU AM 2010)
Answer Key:
Block Diagram
(4)
Manipulation
(4)
(ii)Design and implement the conversion circuits for Binary code to gray code.
(8) (AU AM 2010)
Answer Key:
Truth Table
(4)
Logic Diagram
(4)
14. Design a carry look ahead adder with necessary diagrams.
(16) (AU ND 2009)
Answer Key:
Boolean Simplification
(6)
Boolean Expression
(4)
Logic Diagram
(6)
15. (i) Implement full subtractor using demultiplexer.
(10) (AU ND 2009)
Answer Key:
Boolean Expression
(4)
Logic Diagram
(6)
(ii) Implement the given Boolean function using 8 : 1 multiplexer
F(A, B, C) = (1, 3, 5, 6) .
(6)
Answer Key:
K-Map Implementation
(4)
Block Diagram
(4)

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UNIT-III SEQUENTIAL CIRCUITS

PART A (2 MARKS)
1. Draw the logic diagram of D flip flop using NAND gates.

KCE/DEPT.OF ECE

(AU AM 2015)

2. Realize JK flip flop.

(AU ND 2014)
There are two indeterminante states in SR flip flop. These conditions are defined in JK
flip flop. Like SR flip flop,JK flip flop J is set and K is for clear. When inputs are applied to
both J and K simultaneously, the flip flop switches to its complements state, that is, 1+Q(t)
and then switches to Q=0,and vice-versa.
3. Compare the logics of synchronus counter and ripple counter.
(AU ND,MJ 2014)
Synchronus counter
Ripple counter
It consists of 4 edge triggered JK flip flop
All the flip flops are clocked together.
The triggering occurs when CLK input gets a All the flip flops are clocked together, the
negative edge.
delay time is less.
4. Sketch the logic diagram of cocked SR flip flop.

(AU MJ 2014)

5. Define: Latches.
(AU ND 2013)
A flip-flop or latch is defined as a circuit that has two stable states and can be used to
store state information. A latch is an example of a bistable multivibrator, that is, a device
with exactly two stable states.
6. Write short notes on Digital Clock.
(AU ND 2013)
A digital clock is a type of clock that displays the time digitally (i.e. in numerals or
other symbols), as opposed to an analog clock, where the time is indicated by the positions
of rotating hands.
7. Convert D flip flop to T flip flop.

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(AU MJ 2013,ND 2012)

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8. How many flip flops are required to build a binary counter that counts 0 to 1023?
(AU MJ 2013)
10 Flip flops are required to build a binary counter that counts 0 to 1023.
The formula for finding the flipflop is 2n = 210 = Total counts =1024.
9. How many flip flops are required to design mod 25 counter?
2n N
Here N=25;
25 25.
So, 5 flip flops are required to design mod 25 counter.

(AU MJ 2013)

10. Design a 4 bit ring counter and find the mod of the designed counter.
Circuit diagram:

(AU ND 2012)

Truth table:
Clock

QA

QB

QC

11. What is lockout? How it is avoided?

(AU ND 2012)
In a counter if the next state of some unused state is again an unused state and if by
chance the counter happens to find itself in the unused states and never arrived at a used
state then the counter is said to be in the lockout conditions.
To avoid it:
(a)To ensure that the lockout does not occur, the counter should be designed by
forcing the next state to be the initial state from unused states.
(b)It is not always necessary to force all unused states into an initial state. Because
from unused states which are not forced, the circuit may eventually arrive at a forced
unused state. This frees the circuit from the lockout condition.

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12. What is race around condition in Flipflops?

(AU MJ 2012)
In the JK latch, the output is feedback to the input, and therefore changes in the output
results change in the input. Due to this in the positive half of the clock pulse if J and K are
both high then output toggles continuously. This condition is known as race around
condition.
13. What is a self starting counter?
(AU ND 2011)
The self starting counter is defined as, In a counter if the next state of some unused state
is again an unused state and if by chance the counter happens to find itself in the unused
states and never arrived at a used state then the counter is said to be in the lockout
conditions. The counter which never goes in lockout condition,so it is called as self starting
counter.
14. Write the characteristic equation of a JK flip flop.
The characteristic equation of the JK flip-flop is:

(AU AM 2011, ND 2009)

15. State the differences between Mealy and Moore State Machines.
(AU AM 2011)
Moore circuit
Mealy circuit
Its output is a function of present Its output is a function of present state as
state only.
well as present input.
Input change does not affect the Input changes may affect the output of
output.
the circuit.
Moore circuit requires more number It requires less number of states for
of states for implementing same implementing same function.
function.
16. Write the excitation table for JK flipflop.

(AU AM 2011)

Qn

Qn+1

0
0
1
1

0
1
0
1

0
1
X
X

X
X
1
0

17. What is meant by programmable counter? Mention its Application.

(AU AM 2010)
A counter that divides an input frequency by a number which can be programmed , is
called Programmable counter.
Applications of programmable counter:
Frequency division
Digital clock
Stop watch
Programmable logic controllers.
18. Mention any two differences between the edge triggering and level triggering.
Level Trigger:
(AU AM 2010)
The input signal is sampled when the clock signal is either HIGH or LOW.
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It is sensitive to Glitches. Example: Latch.

Edge Trigger:
The input signal is sampled at the RISING EDGE or FALLING EDGE of the
clock signal.
It is non-sensitive to Glitches. Example: Flip flop.
19. What is a state?
(AU ND 2009)
The information stored in the memory elements is known as state. It consists of two
states (i.e) Present state, Next state.
Present state: The information stored in the memory elements at any given time.
Next state: The present state and external inputs determine the outputs.
20. What is the difference between flow table and transition table?
(AU MJ 2009)
Flow table: In order to construct flow table, these are the tabular forms of state
diagram. This table is constructed using present and next state.
Transition table: It is constructed in such a way that replacing the value by
parameters. In order to represent state transition table state variable state are
identified.
PART B
1. Explain the different modes of operation of asynchronous circuits.
(16) (AU AM2015)
Answer Key:
Block Diagram
(8)
Explanation
(8)
2. (i)Design a 3 bit synchronous counter using JK flip-flop
(12) (AU MJ 2014)
Answer Key:
Block Diagram
(4)
Truth table
(4)
Explanation
(4)
(ii) Explain the difference between state table, characteristic table and excitation table
Answer Key:
(4)
Differention table
(2)
Explanation
(2)
3. Design a Moore type sequence detector to detect a serial input sequence of 101.
(16) (AU MJ 2014)
Answer Key:
Block Diagram
(5)
Explanation
(5)
4. (i) Draw the block diagram of SR-FF and explain.
(6)
(AU ND 2013)
Answer Key:
Explanation
(3)
Diagram
(3)
(ii) Explain about triggering of flip-flops.
(10)
Answer Key:
Explanation
(5)
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Diagram
(5)
5. Draw the block schematic of up-down counter and explain its operation.
(16) (AU ND 2013)
Answer Key:
Explanation
(4)
Truth Table
(6)
Block Diagram
(6)
6. Design a counter to count the sequence 0,1,2,4,5,6 using SRFFs.
(16) (AU MJ 2013)
Answer Key:
Explanation
(4)
Truth Table
(6)
Block Diagram
(6)
7. Design a 4 bit Asynchronous Ripple counter and explain its operation with timing
diagrams.
(16) (AU MJ 2013)
Answer Key:
Explanation
(4)
Truth Table
(4)
Timing Diagram
(2)
Block Diagram
(6)
8. Construct reduced state diagram for the following state diagram.

Answer Key:
State Table
State Diagram
9. (i)Realize SR flip-flop using NOR gates and explain its operation.
Answer Key:
Explanation
Diagram
(ii) Convert a SR flip-flop into JK flip-flop.
Answer Key:
Truth table
Diagram
10. (i)Explain the operation of a BCD ripple counter with JK flip flops.
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(16)

(AU MJ 2012)

(8)
(8)
(8)

(AU MJ 2012)

(4)
(4)

(4)
(4)
(16) (AU AM 2011)
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Answer Key:
Explanation
(8)
Diagram
(8)
11. Design a clocked sequential machine using T flip-flops for the following state diagram.(use
straight binary assignment).
(16) (AU AM 2011)

Answer Key:
State Table
State Diagram

(8)
(8)

12. (i) Construct a clocked JK flip flop which is triggered at the positive edge of the clock pulse
from a clocked SR flip flop consisting of NOR gates.
(4)
(AU MJ 2010)
Answer Key:
Diagram
(2)
Explanation
(2)
(ii) Design a synchronous up/down counter that will count up from zero to one to two to
three, and will repeat whenever an external input x is logic 0, and will count down from
three to two to one to zero, and will repeat whenever the external input x is logic 1.
Implement your circuit with one TTL SN74LS76 device and one TTL SN74LS00 device.
(12)
Answer Key:
Explanation
(4)
Expression
(2)
Circuit Diagram
(6)
13. (i)Write down the Characteristic table for the JK flip flop with NOR gates.(4) (AU AM 2010)
Answer Key:
Block Diagram
(2)
Explanation
(2)
(ii)What is meant by Universal Shift Register? Explain the principle of Operation of
4-bit Universal Shift Register.
(12)
Answer Key:
Explanation
(4)
Expression
(2)
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Circuit Diagram
14. (i) How will you convert a D flipflop into JK flipflop?
Answer Key:
Explanation
State Table
(ii)Explain the operation of a JK master slave flipflop.
Answer Key:
Explanation
Diagram

(6)
(8)

15. Explain in detail the operation of a 4 bit binary ripple counter.

Answer Key:
Explanation
Diagram

(16)

DE29

(AU ND 2009)

(4)
(4)
(8)
(4)
(4)
(AU ND 2009)

(8)
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UNIT-IV MEMORY DEVICES

PART A (2 MARKS)
1. Enumrate the types of ROMs.
ROM - Read Only Memory.

(AU AM 2015)

PROM - Programmable Read Only Memory.

EPROM - Erasable Programmable Read Only Memory.

EEPROM - Electrically Erasable Programmable Read Only Memory.

Flash EEPROM memory.

2. What is FPGA?
(AU ND2014)
The Field Programmable Gate Array is the ability of the gate array to be programmed
for a particular function by the user instead of by the manufacturer of device so it is called
as FPGA.
3. Draw the logic diagram of static RAM cell

(AU MJ 2014)

4. List the advantages of PLDs.

(AU MJ 2014)
The advantages of PLD is,
It will be used to implement both combinational and sequential circuits
It can replace a large number of integrated circuits(IC)
The design can be changed by attending the program.
5. What is Volatile and Non-Volatile memory?
(AU ND 2013)
Volatile memory is the RAM memory that is lost when your system is rebooted, so it
is clled as Volatile memory.
Nonvolatile memory is the data that gets saved to your ROM memory even when not
powered, so it is clled as Non- Volatile memory.
6. Give the advantages of RAM.
(AU ND 2013)
The advantages of RAM is,
We can "write" to RAM at any time, and the erase the RAM at any time an "rewrite"
over it.
Used to increase the capacity of the memory of the system.
7. What are the different types of programmable logic devices?
They are three types, 1. Programmable Logic Array PLA
2. Programmable Array Logic PAL
3. Field Programmable Gate Array FPGA
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8. Distinguish between PLA and PAL.

(AU MJ 2013)
PLA is most flexible PLD where Both AND and OR arrays can be programmed.
PAL is a programmable logic device with a fixed OR array and Programmable AND
array.
9. How the Memories are classified?
The memories are classified,
Volatile memory Example: RAM
Non-Volatile memory Example: ROM,PROM,EPROM,EEPROM

(AU ND 2012)

10. Draw the logic diagram of Bipolar RAM cell.

(AU ND 2012)

11. What is a PLA?

(AU MJ 2012)
PLA is Programmable Logic Array (PLA). The PLA is a PLD that consists of a
Programmable AND array and a programmable OR array, so it is called as PLA.
12. Why the input variables to a PAL are buffered?
(AU ND 2011)
The input variables to a PAL are buffered to prevent loading by the large number of
AND gate inputs to which available or its complement can be connected.
13. What is the difference between PAL and PLA?
PLA
In PLA both the AND and OR array are In PAL only
programmable.
programmable.

(AU AM 2011)
PAL
the AND

array

is

In PLA only combinational circuits are In PAL both combinational and sequential
designed.
devices can be programmed due to the
presence of flip flops.
14. Implement the Exclusive-OR function using ROM.
Block diagram:

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Truth table:
A
0
0
1
1

B
0
1
0
1

Y
0
1
1
0

15. What is the difference between PROM and EPROM?

(AU ND 2010)
PROM
EPROM
PROM is Programmable Read Only Memory EPROM is Erasable Programmable Read
Only Memory.
It consists of a set of fixed AND gates
It consists of MOS circuitry, so they store 1s
Connected
to
a
decoder
and
a and 0s as a packet of charge in a buried
programmable OR array.
layer of the IC chip.
The PROMs are one time programmable. It is not possible to erase selective
Once programmed, the information is stored information.
The
chip
can
be
permanent.
reprogrammed.
16. What is meant by memory expansion? Mention its limit.
(AU AM 2010)
The memory expansion is the process to increase the memory capacity by either in
terms of increasing the word size or increasing the number of memory locations.We can
expand memory word size upto 16 and capacity upto 224 = 16Mbyte when a system has 24
address lines and 16 data lines, so it is called as memory expansion.
17. What are the advantages of static RAM compared to dynamic RAM?
The advantages of static RAM compared to dynamic RAM is,
Each cell is a flip flop.
Refress is not required.
Access time is less than DRAM.
These are faster memory than DRAM.

(AU AM 2010)

18. Compare and contrast static RAM and dynamic RAM.

(AU ND 2009)
SI.No.
Parameters
SRAM
DRAM
1
Circuit
Each cell is a flip flop.
Each unit consist of one
configuration
MOSFET and a capacitor
2
Refressing
Not required
Required
3
Cost
More
Less
4
Access time
Less. So these are faster More. So these are slower
memory.
memory.

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19. What are the different types of RAM?

The different types of RAM is,
NMOS RAM
CMOS RAM
Schottky TTL RAM
ELL RAM

(AU AM 2009)

20. What is PAL? How does it differ from PLA?

(AU ND 2009)
The Programmable Logic Array is,In some cases the number of dont care conditions is
excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is
similar to a ROM in concept; however it does not provide full decoding of the variables and does
not generates all the minterms as in the ROM, so it is called as PAL.
PART B
1. (i)Write short notes on EAPROM and static RAM cell using MOSFET. (6)
(AU ND 2014)
Answer Key:
Explanation
(4)
Diagram
(2)
(ii) Using eight 64x8 ROM chips with an enable input and decoder construct a 512x 8 ROM
Answer Key:
(10)
Explanation
(6)
Diagram
(4)
2. (i) Use PLA with 3 inputs ,4 AND terms and two outputs to implement the following two
Boolean functions F1(A,B,C)=m(3,5,6,7) and F2(A,B,C,)=m(1,2,3,4)(12) (AU ND 2014)
Answer Key:
Truth Table
(6)
Logic Diagram
(6)
(ii) Compare and contrast PLA and PAL
(4)
Answer Key:
Comparison Explanation
(4)
3. (i)Explain the read and write cycle timing parameters of RAM with the
diagram.
(8)
Answer Key:
Explanation
(4)
Diagram
(4)
(ii) Draw the Dynamic RAM cell and explain its operation.
(8)
Answer Key:
Explanation
(4)
Diagram
(4)
4. Design a BCD to Excess 3 Convertor using PLA.
(16)
Answer Key:
Truth Table
(8)
Logic Diagram
(8)
5. Discuss in detail about the classifications of memories.
(16)
Answer Key:
Explanation
(8)
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(AU MJ 2014)

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Diagram

(8)

6. Discuss in detail about the FPGA with suitable diagrams.

Answer Key:
Explanation
Logic Diagram

(16)

7. Design and Explain a 32 x 8 ROM.

Answer Key:
Truth Table
Logic Diagram

(16)

8. Design using PAL the following Boolean functions

W(A,B,C,D)= (2,12,13)
X(A,B,C,D)= (7,8,9,10,11,12,13,14,15)
Y(A,B,C,D)= (0,2,3,4,5,6,7,8,10,11,15)
Z(A,B,C,D)= (1,2,8,12,13)
Answer Key :
Block Diagram
Calculation

(16)

(AU ND 2013)

(8)
(8)
(AU MJ 2013)

(8)
(8)
(AU MJ 2013)

(8)
(8)

9. (i)Implement a 3 bit up/down counter using PAL devices.

(8)
(AU ND 2012)
Answer Key:
Truth Table
(4)
Logic Diagram
(4)
(ii) Implement binary to Gray code converter using PROM devices.
(8)
Answer Key:
Truth Table
(4)
Logic Diagram
(4)
10. Write short notes on :
(i)Memory decoding
(8)
(AU ND 2012)
Answer Key:
Truth Table
(4)
Logic Diagram
(4)
(ii)Memory Expansion.
(8)
Answer Key:
Truth Table
(4)
Logic Diagram
(4)
11. (i) We can expand the word size of a RAM by combining two or more RAM chips. For
instance, we can use two 32 8 memory chips where the number 32 represents the number
of words and 8 represents the number of bits per word, to obtain a 32 16 RAM. In this case
the number of words remains the same but the length of each word will two bytes long.
Draw a block diagram to show how we can use two 16 4 memory chips to obtain a 16 8
RAM
(8) (AU AM 2010)
Answer Key :

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Block Diagram
Calculation

(4)
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(ii) Explain the principle of operation of Bipolar SRAM cell.

(8) (AU AM 2010)
Answer Key:
Diagram
(4)
Explanation
(4)
12. (i) A combinational circuit is defined as the functions
F1 = ABC+ABC+ABC
F2 = ABC+ABC+ABC
Implement the digital circuit with a PLA having 3 inputs, 3 product terms, and 2 outputs.
Answer Key:
(8) (AU AM 2010)
K-Map & Truth Table
(4)
Logic Diagram
(4)
(ii) Write a note on SRAM based FPGA.
(8)
Answer Key:
Diagram
(3)
Explanation
(5)
13. Implement the following Boolean functions with a PLA
F1(A ,B ,C ) = (0, 1, 2, 4)
F2( A,B ,C ) = (0, 5, 6, 7)
F3(A ,B , C) = (0, 3, 5, 7) .
(16) (AU ND 2009)
Answer Key:
K-Map
(4)
Truth Table
(6)
Logic Diagram
(6)
14. Design a combinational circuit using a ROM. The circuit accepts a three bit number and
outputs a binary number equal to the square of the input number.
(16) (AU ND 2009)
Answer Key:
Block Diagram
(4)
Calculation
(4)
Design
(8)
15. Design a negative-edge triggered T flipflop.
(16) (AU ND 2009)
Answer Key :
Logic Diagram
(8)
Truth Table
(8)

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UNIT-V
SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS
PART A (2 MARKS)
1. What is a critical race condition in asynchronous sequential circuits?
(AU ND 2014)
A critical race condition is, When 2 or more binary state variables change their
value in response to a change in an input variable, race condition occurs in an asynchronous
sequential circuit. In case of unequal delays, a race condition may cause the state variables to
change in an unpredictable manner, so t is called as critial race.
2. Define ASM chart.List its elements.
(AU ND 2014)
The Algorithmic State Machine (ASM) method is defined as, it is a method for designing
finite state machines. It is used to represent diagrams of digital integrated circuits. The ASM
diagram is like a state diagram but less formal and thus easier to understand. An ASM chart is a
method of describing the sequential operations of a digital system. An ASM chart consists of an
interconnection of four types of basic elements: state names, states, condition checks and
conditional outputs.
3. What is a state diagram?
(AU MJ 2013)
A state diagram is a type of diagram used in computer science and related fields to
describe the behavior of systems. State diagrams require that the system described is
composed of a finite number of states; sometimes, this is indeed the case, while at other times
this is a reasonable abstraction, so it is called as state diagram.
4. Write the VHDL code for half adder.
module half_adder(A,B,Cout,Sum);
input A;
input B;
output Sum;
output Cout;
reg Sum, Cout;
always@(A,B)
begin
Sum=a^b;
Cout=a&b;
End
End module

(AU MJ 2013)

5. What is Synchronous Sequential Circuit?

(AU ND 2013)
Synchronous Sequential Circuit can be defined as ,In synchronous sequential circuits,
signals can affect the memory elements only at discrete instant of time.
6. Write short notes on Hazards.
(AU ND 2013)
A hazard is the actual or potential malfunction of a logic network during the
transition between two input states when single variable changes. In combinational circuits,
the hazard will result in false output value.

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7. What are Hazards?

(AU MJ 2013),(AU ND 2009)
The Hazards are the Unwanted switching transients are that may appear at the
output of the circuit are called Hazards.The two types are static hazard and dynamic hazard.
8. Distinguish between a flowchart and a ASM chart.
(AU MJ 2013)
A conventional flow chart describes the sequence of procedural steps and decision
paths for an algorithm without concern for their time relationship.
An ASM schart describes the sequence of events as well as the timing relationship
between the states of a sequential controller and the events that occur while going
from one state to the nexrt.
9. Differentiate fundamental mode and pulse mode asynchronous sequential circuits.
(AU ND 2012)
Sl. no.
Fundamental Mode
Pulse Mode
Input variables changes if the circuit Inputs are pulses.
1
is stable.
Inputs are levels, not pulses.
Width of pulses are long for circuit to
2
respond to the input.
Only one input can change at a given Pulse width must not be so long that it is
3
time.
still present after the new state is
reached.
10. What is entity ?
(AU ND 2012)
Entity is defined as ,it gives the specification of input/output signals to external circuitry. It
gives interfacing between device and the other peripherals. An entity usully has one or more
ports, which are analogous to the pins on a schematic symbol.
11. Design a 3 input AND gate using Verilog.
module andgate (x1, x2, x3, y);
input x1, x2, x3;
output y;
and (y, x1, x2,x3);
endmodule

(AU ND 2012)

12. What is subprogram ?

(AU MJ 2012)
A Subprogram is a sequential algorithm that performs partculr task.Two types of the
subprograms are procedure and functions. Procedures and functions are directly analogous to
functions and procedures in a high level programming language, so it is called as subprogram.
13. Write HDL behavior model of D flipflop.
Module D_ff (D,CLK,Q);
input D,CLK;
output Q;
reg Q;
always@(posedge CLK)
Q=D;
End module
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14. Define flow table in asynchronous sequential circuits.

(AU ND 2011)
The flow table is defined as,For the design of sequential counters we have to relate present
states and next states. The table, which represents the relationship between present states and
next states, is called flow table.
15. What are the basic building blocks of a Algorithmic state machine chart?
An ASM chart is composed of three basic bulding blocks,

The state box

The decision box and

The conditional box

(AU AM 2011)

16. What are the two types of Asynchronous sequential circuits?

There are two types,

Fundamental Mode

Pulse Mode

(AU AM 2011)

17. What are the various modeling techniques in HDL ?

The various modeling techniques in HDL is,

Gate level /Structural modeling

Data flow modeling

Behavioral modeling

(AU ND 2010)

18. Draw the block diagram for Moore model.

(AU AM 2010)

19. How is package represented ?

It can be represented by,

Package declaration

Package body

(AU ND 2010)

20. What are hazard free digital circuits?

(AU AM 2010)
The free of static and dynamic hazard in combinational circuit is called hazard free
digital circuits.
PART B
1.

Explain the following terms :

(i)
Critical race
(ii)
Hazard
(iii) Flow table and Flow table reduction
(iv) Non critical race

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(4)
(4)
(4)
(4)

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2.

3.

4.

5.

6.

7.

8.

9.

KCE/DEPT.OF ECE

Answer Key: (for each)

Block Diagram
(2)

Explanation
(2)
What is a hazard in asynchronous sequential circuts ? Define static hazard, dynmic hazard and
essential hazard.
(16) (AU ND 2014)
Answer Key :

Block Diagram
(8)

Explanation
(8)
Write and verify the HDL structural description of the four bit register with parallel load. Use a
2x1 multiplexer for the flip flop inputs. Include an asynchronous clear input.
Answer Key :
(16) (AU ND 2014)

Block Diagram
(8)

Coding
(8)
Design a T flip flop using logic gates. Derive the state table, state diagram, primitive flow table,
transition table and Merger graph.Draw the logic circuit.
(16) (AU MJ 2014)
Answer Key :

K-Map Implementation
(6)

Boolean Expression
(4)

Logic Diagram
(6)
Design a asynchronous sequential circuit that has 2 inputs x1 and x2 and one output z. When x1
=0, output is 0. The change in x2 that occurs while x1 is 1 will cause output z=0. The output z
will remain 1 until x1 returns to 0.
(16) (AU MJ 2014)
Answer Key :

K-Map Implementation
(6)

Boolean Expression
(4)

Logic Diagram
(6)
Design a hazard-free asynchronous circuit that changes state whenever the input goes from
logic 1 to logic 0.
(16) (AU MJ 2013)
Answer Key :

K-Map Implementation
(6)

Boolean Expression
(4)

Logic Diagram
(6)
(i)Design a full adder using two half adders by writing verilog program. (10) (AU MJ 2013)
Answer Key :

Block Diagram
(4)

Coding
(6)
(ii)Write Explanatory notes on Algorithmic State Machines.
(6)
Answer Key :

Block Diagram
(3)

Explanation
(3)
Design a serial binary adder using delay flip-flop.
(16) (AU ND 2013)
Answer Key :

Block Diagram
(6)

Truth Table
(4)

Logic Diagram
(6)
List out various problems arises in asynchronous circuits. Explain any two problems in detail.
(16) (AU ND 2013)

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Answer Key :

Explanation
(8)

State Diagram
(8)
10. Design a three bit binary counter using T flipflops
(16) (AU ND 2009)
Answer Key :

Logic Diagram
(8)

Explanation
(8)
11. Design a negative-edge triggered T flipflop
(16) (AU ND 2009)
Answer Key :

Truth Table
(8)

Logic Diagram
(8)
12. Design the following circuits using verilog
(i)4 to 1 multiplexer
(8)
(AU ND 2012)
Answer Key :

Block Diagram
(4)

Coding
(4)
(ii)2 bit up/down counter.
(8)
Answer Key :

Block Diagram
(4)

Coding
(4)
13. Write short notes on races and hazards that occur in asynchronous circuits.Discuss a method
used for race free assignment with example
(16) (AU ND 2012)
Answer Key :

Explanation
(8)

Example
(8)
14. What are called as essential hazards? How does the hazard occur in sequential circuits?How
can the same be eliminated using SR latches?Give an example.
(16) (AU AM 2010)
Answer Key :

Explanation
(8)

Example
(8)
15. Design a three bit binary counter using T flipflops.
(16) (AU ND 2009)
Answer Key :

Logic Diagram
(8)

Truth Table
(8)

DE40

KCE/ECE/QB/II YR/DE

Format: QP09

KCE/DEPT.OF ECE

SUMMARY:
UNIT NO.

NO. OF QUESTIONS
IN 2 MARKS

NO. OF QUESTIONS

20

17

II

20

15

III

20

15

IV

20

15

20

15

TOTAL

100

77

IN 16 MARKS

No. of sample university question Papers: 3

STAFF INCHARGE

HOD/ECE

Ms.K.Vinu Priya, AP/ECE

DE41

KCE/ECE/QB/II YR/DE