Mux and Flipflops - Opt

MUX AND FLIPFLOPS/LATCHES
Compiled by: Suresh S. Balpande

contact:sbalpande@yahoo.com
BY: SURESH BALPANDE
Multiplexers
2:1 multiplexer chooses between two inputs
S
S
0
D1
D0
Compiled
Balpande
X
0 by: 0Suresh S.D0
0
@BALPANDECircuits and
Layout
Y
1
1
D1 1
X
Slide 2
Gate-Level Mux Design

Y SD1 SD0 (too many transistors)
How many transistors are needed? 20

D1
S
Compiled
D0
by: SureshY S. Balpande
D1
S
D0
Layout
2
4
Slide 3
Transmission Gate Mux

Nonrestoring mux uses two transmission gates
mux uses two transmission gates
Only 4 transistors

D0
S
D1
S
Layout
Slide 4
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two
selects
S1S0 S1S0 S1S0 S1S0
Two levels of 2:1 muxes
by: Suresh S. Balpande
OrCompiled
four tristates
D0
S1
S0
D0
0
D1
D1
0
Y
Y
D2
D3
1
D2
D3
Layout
Slide 5
D Latch
When CLK = 1, latch is transparent
D flows through to Q like a buffer
When CLK = 0, the latch is opaque

Suresh
S. Balpande
Q Compiled
holds its oldby:
value
independent
of D
a.k.a. transparent latch or level-sensitive latch

CLK
D
Layout
Latch
CLK
Q
Q
Slide 6
D Latch Design
Multiplexer chooses D or old Q
CLK
D
CLK
CLK CLK
CLK
Layout
Slide 7
D Latch Operation
Q
D
CLK = 1
Q
D
CLK = 0

CLK
D
Q
Layout
Slide 8
D Flip-flop
When CLK rises, D is copied to Q
At all other times, Q holds its value
a.k.a. positive edge-triggered flip-flop, masterCompiled
by:
Suresh
S.
Balpande
slave flip-flop
CLK
CLK
D
Flop
Q
Q
Layout
Slide 9
D Flip-flop Design
Built from master and slave D latches
CLK
CLK
CLK
QM
CLK
CLK Suresh
Compiled by:
S. Balpande
CLK CLK
QM
Latch
Latch
CLK
Q
CLK
Layout
Slide 10
CLK
D Flip-flop Operation
QM
CLK = 0
QM
Q
CLK = 1
CLK
D
Q
Layout
Slide 11
CMOS SR Latch: NOR Gate Version
The NOR-based SR Latch contains the basic

memory cell (back-to-back inverters) built
into two NOR gates to allow setting the state
of the latch.
If Set goes high, M1 is turned on forcing Q
low which, in turn, pulls Q high
S=1 Q = 1
If Reset goes high, M4 is turned on, Q is

pulled low, and Q is then pulled high
R=1 Q = 1
Compiled by: Suresh
S. Balpande
If both Set and Reset are low, both M1 and
M4 are off, and the latch holds its existing

state indefinitely
If both Set and Reset go high, both Q and Q
are pulled low, giving an indefinite state.
Therefore, R=S=1 is not allowed
The gate-level symbol and truth table for the

NOR-based SR latch are given at left
To estimate Set time, add time to discharge
Q + time to charge Q (pessimistic result)
R. W. Knepper
SC571, page 5-30
CMOS SR Latch: NAND Gate Version
A CMOS SR latch built with two 2-input

NAND gates is shown at left
The basic memory cell comprised of two
back-to-back CMOS inverters is seen
The circuit responds to active low S and R

inputs
If S goes to 0 (while R = 1), Q goes high,
pulling Q low and the latch enters Set state
S=0 Q = 1 (if R = 1)
to 0 (while S = 1), Q goes high,

Compiled by: Suresh If RS.goesBalpande
pulling Q low and the latch is Reset
R=0 Q = 1 (if S = 1)
Hold state requires both S and R to be high

S = R = 0 if not allowed, as it would result in
an indeterminate state
R. W. Knepper
SC571, page 5-32
Clocked CMOS JK Latch: NAND Version
The SR latch has a problem in that when both S

and R are high, its state becomes
indeterminate
The JK latch shown at left eliminates this
problem by using feedback from output to
input, such all states in the truth table are
allowable
If J = K = 0, the latch will hold its present state

If J = 1 and K = 0, the latch will set on the next
positive-going clock edge, i.e. Q = 1, Q = 0
If J = 0 and K = 1, the latch will reset on the next
positive-going clock edge, i.e. Q = 1 and Q = 0
If J = K = 1, the latch will toggle on the next
positive-going clock edge
Note that in order to prevent the JK Latch above

from oscillating continuously during the clock
active time, the clock width must be kept smaller
than the switching delay time of the latch.
Otherwise, several oscillations may occur before
the clock goes low again. In practice this may be
difficult to achieve.
R. W. Knepper
SC571, page 5-35
CMOS D-Latch Implementation
A D-latch is implemented, at the gate level, by

simply utilizing a NOR-based S-R latch,
connecting D to input S, and connecting D to
input R with an inverter.
When CLK goes high, D is transmitted to output
Q (and D to Q)
When CLK goes low, the latch retains its previous
state
The D latch is normally implemented with

transmission gate (TG) switches, as shown at
the left

The input TG is activated with CLK while the

latch feedback loop TG is activated with CLK
Input D is accepted when CLK is high
When CLK goes low, the input is open-circuited
and the latch is set with the prior data D
R. W. Knepper
SC571, page 5-37
Alternate CMOS D-Latch Implementation
An alternate (preferred) version of the CMOS

D-Latch (shown at left) is implemented with
two tri-state inverters and a normal CMOS
inverter.
Functionally it is similar to the previous chart
D-Latch
When CLK is high, the first tri-state inverter
sends the inverted input through to the
second inverter, while the second tri-state is in
its high Z state.
Output Q is following input D

When CLK is low, the first tri-state goes into its

high Z state, while the second tri-state inverter
closes the feedback loop, holding the data Q
and Q in the latch.
R. W. Knepper
SC571, page 5-39

Mux and Flipflops - Opt

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MUX AND FLIPFLOPS/LATCHES

Compiled by: Suresh S. Balpande

BY: SURESH BALPANDE

Gate-Level Mux Design

How many transistors are needed? 20

by: SureshY S. Balpande

Transmission Gate Mux

Compiled by: Suresh S. Balpande

When CLK = 0, the latch is opaque

a.k.a. transparent latch or level-sensitive latch

Compiled by: Suresh S. Balpande

Compiled by: Suresh S. Balpande

CMOS SR Latch: NOR Gate Version

The NOR-based SR Latch contains the basic

If Reset goes high, M4 is turned on, Q is

M4 are off, and the latch holds its existing

The gate-level symbol and truth table for the

CMOS SR Latch: NAND Gate Version

A CMOS SR latch built with two 2-input

The circuit responds to active low S and R

to 0 (while S = 1), Q goes high,

Hold state requires both S and R to be high

Clocked CMOS JK Latch: NAND Version

The SR latch has a problem in that when both S

If J = K = 0, the latch will hold its present state

Compiled by: Suresh S. Balpande

Note that in order to prevent the JK Latch above

CMOS D-Latch Implementation

A D-latch is implemented, at the gate level, by

The D latch is normally implemented with

Compiled by: Suresh S. Balpande

The input TG is activated with CLK while the

Alternate CMOS D-Latch Implementation

An alternate (preferred) version of the CMOS

Compiled by: Suresh S. Balpande

Output Q is following input D

When CLK is low, the first tri-state goes into its

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