Proceedings

19th International
Conference on VLSI Design
held jointly with
5th International Conference on Embedded Systems Design

3-7 January 2006

Hyderabad, India
Technical Co-Sponsorship
IEEE Circuits and Systems Society
ACM Special Interest Group on Design Automation
IEEE Solid State Circuits Society
IEEE Electron Devices Society

Sponsored by
VLSI Society of India

Sister Conference
IEEE/ACM Design Automation Conference

Los Alamitos, California

Washington

Tokyo

TABLE OF CONTENTS

TUTORIALS
Low-Power Design Strategies for Mobile Computing......................................................................................1
A. Prasad, J. Mathews, N. Naganathan

Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies.................................3

R. Puri, T. Karnik, R. Joshi

Beyond RTL: Advanced Digital System Design ...............................................................................................6

S. Tasker, R. Nikhil

System Aspects of Analog to Digital Converter Designs..................................................................................8

S. Pavan, P. Easwaran, C. Srinivasan

Interconnect Process Variations: Theory and Practice ...................................................................................9

N. S. Nagaraj

Design Challenges for High Performance Nano-technology .........................................................................10

G. Debnath, P. Thadikaran

DFM, DFT, Silicon Debug and Diagnosis The Loop to Ensure Product Yield.......................................12
D. Abercrombie, B. Koenemann, N. Tamarapalli, S. Venkataraman

A Comprehensive SoC Design Methodology for Nanometer Design Challenges ........................................13

R. Kumar, R. Bedi, R. Rajagopal, N. Guruprasad, K. Subbarangaiah, T. Abbasi, D. Murthy, P.
Prasad, D. Gude

Sequential Equivalence Checking....................................................................................................................16

A. Mathur, M. Fujita, M. Balakrishnan, R. Mitra

Embedded Systems Design Using FPGA.........................................................................................................18

P. Patel

Design of Embedded Systems with Novel Applications .................................................................................19

R. Lacovara, D. Vaman

INAUGURAL KEYNOTE ADDRESS

Small, Smart, Intelligent and Interactive Handheld Devices ........................................................................21
D. Orton

KEYNOTES
We Want It All, and We Want It Now! ...........................................................................................................22
R. Miller

Keynote Address................................................................................................................................................23
M. Rhodes

IC/FPGA-Package-PCB Design Collaboration ..............................................................................................24

H. Potts

BANQUET SPEECHES
The Technological and Geographical Migration of the Semiconductor Industry.......................................25
J. Hu

Future FPGA Technologies, in Partnership with Universities ......................................................................26

R. Sevcik

PLENARY SESSIONS
UNUM: A Tinker-Toy Approach to Building Multicore PowerPC Microarchitectures ............................27
Arvind

SoC The Road Ahead...................................................................................................................................28

M. Mehendale

Integrated Design Flows A Battered EDA Slogan or True Challenge for Tool
Development and Algorithmic Research.........................................................................................................29
A. Kuehlman

SESSION 1A: ANALOG AND MIXED-SIGNAL DESIGN I

CHAIRS: G. VISWESWARAN AND A. PRASAD
Embedded Tutorial: Analog Circuit Performance Issues with Aggressively Scaled Gate
Oxide CMOS Technologies ..............................................................................................................................30
K. Narasimhulu, V. Rao

Extrinsic Analog Synthesis Using Piecewise Linear Current-Mode Circuits ..............................................36

M. Bhat, S. Rekha, H. Jamadagni

Design of a 1 V Low Power 900 MHz QVCO .................................................................................................42

P. Saha, A. Dutta, A. Patra, T. Bhattacharyya

16-Bit Segmented Type Current Steering DAC for Video Applications ......................................................48
G. Raja, B. Bhaumik

A Low Power 1.8 V 4-Bit 400-MHz Flash ADC in 0.18? Digital CMOS......................................................54
S. Banik, D. Gangopadhyay, T. Bhattacharyya

A Low Power 6-Bit A/D Converter Achieving 10-Bit Resolution for MEMS Sensor
Interface Using Time-Interleaved Delta Modulation .....................................................................................60
K. De, S. Kal

SESSION 1B: VLSI TECHNOLOGY I

CHAIRS: M. KUMAR AND G. DEBNATH
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS
Circuits...............................................................................................................................................................66
S. Mohanty, E. Kougianos

Wide Limited Switch Dynamic Logic Circuit Implementations ...................................................................72

J. Sivagnaname, H. Ngo, K. Nowka, R. Montoye, R. Brown

A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity ....................................................78

T. Rejimon, S. Bhanja

Phase Change Memory Faults .........................................................................................................................86

M. Mohammad, L. Terkawi, M. Albasman

Gate-induced Barrier Field Effect Transistor (GBFET)- A New Thin Film Transistor for
Active Matrix Liquid Crystal Display Systems ..............................................................................................92
M. Jagadesh Kumar, A.A. Orouji

SESSION 1C: INTERCONNECT DESIGN I

CHAIRS: S. BATTERYWALA AND R. JOSHI
A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency....................................................97
P. Caputa, C. Svensson

Optimization of Global Interconnects in High Performance VLSI Circuits..............................................103

M. Tang, J.-F. Mao

A Statistical Method for Fast and Accurate Capacitance Extraction in the Presence of
Floating Dummy Fills .....................................................................................................................................109
S. Batterywala, R. Ananthakrishna, Y. Luo, A. Gyure

MoM A Process Variation Aware Statistical Capacitance Extractor....................................................115

R. Ananthakrishna, S. Batterywala

Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics.......................121
A. Bhaduri, R. Vemuri

Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven

Global Routing ................................................................................................................................................127
J.-T. Yan, C.-F. Lee, Y.-H. Chen

SESSION 1D: TEST AND DIAGNOSIS

CHAIRS: A. BARUA AND S. REDDY
A New Device Level Digital Simulator for Simulation and Functional Verification of Large
Semiconductor Memories ...............................................................................................................................133
T. Dastidar, P. Ray

An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip...............................................139

H. Venkatanarayanan, M. Bushnell

Test Cost Reduction Using Partitioned Grid Random Access Scan ...........................................................147
D. Baik, K. Saluja

An Efficient Scan Tree Design for Compact Test Pattern Set.....................................................................153

S. Banerjee, D. Chowdhury, B. Bhattacharya

On Methods to Improve Location Based Logic Diagnosis...........................................................................159

W. Zou, W.-T. Cheng, S. Reddy, H. Tang

Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and

Circuits.............................................................................................................................................................166
P. Jain, D. Kumar, J. Vasi, M. Patil

SESSION 2A: COMMUNICATIONS MODULE ARCHITECTURE

CHAIR: R. MAHAPATRA
A Wide-Range, High-Resolution, Compact CMOS, Time to Digital Converter .......................................172
V. Ramakrishnan, P. Balsara

Programmable LDPC Decoder Based on the Bubble-Sort Algorithm .......................................................178

R. Singhal, G. Choi, R. Mahapatra

An Asynchronous Interconnect Architecture for Device Security Enhancement .....................................184

S. Hollis, S. Moore

A Pipelined Switched-Current Chaotic System for the High-Speed Truly Random Number
Generation in Crypto Processor ....................................................................................................................191
T. Zhou, M. Yu, Y. Ye

SESSION 2B: FORMAL VERIFICATION

CHAIR: R. MITRA
Checking Nested Properties Using Bounded Model Checking and Sequential ATPG .............................197
Q. Qiang, D. Saab, J. Abraham

Apriori Formal Coverage Analysis for Protocol Properties........................................................................203

P. Tiwari, S. Biswas, R. Mitra

An Integrated Approach for Combining BDD and SAT Provers...............................................................209

R. Drechsler, G. Fey, S. Kinder

Reducing Design Verification Cycle Time through Testbench Redundancy .............................................215

A. Kokrady, R. Mehrotra, T. Powell, S. Ramakrishnan

SESSION 2C: VLSI ARCHITECTURE AND FPGAS

CHAIR: S. SRINIVASAN AND D. MEHTA
CAD Tools for a Globally Asynchronous Locally Synchronous FPGA Architecture...............................221
X. Jia, R. Vemuri

Heterogeneous Floorplanning for FPGAs.....................................................................................................227

Y. Feng, D. Mehta

A Novel Architecture Using the Decorrelating Transform for Low Power Adaptive Filters...................233
M. Tennant, A. Erdogan, T. Arslan, J. Thompson

SESSION 2D: CROSSTALK ANALYSIS

CHAIRS: V. VISVANATHAN AND S. MAJUMDER
Active Crosstalk Cancel for High-Density Inductive Inter-chip Wireless Communication .....................239
A. Kumar, N. Miura, M. Muqsith, T. Kuroda

A Comprehensive Solution for True Hierarchical Timing and Crosstalk Delay Signoff .........................245
K. Rajagopal, R. Sivakumar, N. Arvind, C. Sreeram, V. Visvanathan, S. Dhuri, R. Chander, P.
Fortner, S. Sripada, Q. Wu

A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect
Delay and Crosstalk Noise..............................................................................................................................251
N. Hanchate, N. Ranganathan

SESSION 3A: HIGH-LEVEL AND LOGIC SYNTHESIS

CHAIRS: A. KUMAR AND R. GUPTA
Instruction-Set-Extension Exploration Using Decomposable Heuristic Search ........................................259
S. Das, P. Chakrabarti, P. Dasgupta

Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded

Processors ........................................................................................................................................................265
N. Potlapally, S. Ravi, A. Raghunathan, R. Lee, N. Jha

Handling Constraints in Multi-objective GA for Embedded System Design.............................................271

B. Chakraborty, T. Chen, T. Mitra, A. Roychoudhury

A New Approach to Synthesize Multiple-Output Functions Using Reversible

Programmable Logic Array ...........................................................................................................................277
A. Chowdhury, R. Nazmul, H. Babu

State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based
Implementations with Application to Nanotechnologies .............................................................................283
R. Zhang, N. Jha

Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing
Analysis ............................................................................................................................................................289
J. Sridharan, T. Chen

SESSION 3B: DISTRIBUTION AND NOISE MODELING

CHAIRS: S. SUR-KOLAY AND K. ROY
An On-Chip Voltage Regulator with Improved Load Regulation and Light Load Power
Efficiency..........................................................................................................................................................295
R. Raghavendra, P. Mandal

Efficient Design and Analysis of Robust Power Distribution Meshes ........................................................301

P. Gupta, A. Kahng

Test Pattern Generation for Power Supply Droop Faults ...........................................................................307

D. Mitra, S. Bhattacharjee, S. Sur-Kolay, B. Bhattacharya, S. Zachariah, S. Kundu

Bounding Supply Noise Induced Path Delay Variation Using a Relaxation Approach ............................313
B. Wang, P. Mazumder

Accurate Substrate Noise Analysis Based on Library Module Characterization......................................319

S. Reddy, R. Murgai

Efficient Techniques for Noise Characterization of Sequential Cells and Macros....................................327

V. Vallapenani, R. Chevuri, B. Xu, L. Ye, K. Chakraborty

SESSION 3C: MULTIMEDIA AND ARITHMETIC ARCHITECTURE

CHAIRS: A. BASU AND M. SRINIVAS
An Approach to Architectural Enhancement for Embedded Speech Applications ..................................333
S. Dey, S. Biswas, A. Mukhopadhyay, A. Basu

A Low Power ROM-less Direct Digital Frequency Synthesizer with Preset Value Pipelined
Accumulator ....................................................................................................................................................339
J. Chen, R. Luo, H. Yang, H. Wang

Performance Optimization with Scalable Reconfigurable Computing Systems........................................343

R. Sangireddy, P. Rajamani, S. Gaddam

Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format........................349
H. Thapliyal, S. Kotiyal, M. Srinivas

An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition...........................355

V. Mahalingam, N. Ranganathan

Partial Product Reduction Based on Look-Up Tables .................................................................................361

H. Mora, J. Pascual, J. Romero, F. Lpez

SESSION 3D: TEST ALGORITHMS

CHAIRS: I. SENGUPTA AND A. SINGH
Sequential Spectral ATPG Using the Wavelet Transform and Compaction .............................................367
S. Devanathan, M. Bushnell

Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive
Bridges, and Capacitive Crosstalk Delay Faults...........................................................................................373
S. Chary, M. Bushnell

New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant

Logic..... 419 .....................................................................................................................................................379
G. Chen, S. Reddy, I. Pomeranz, J. Rajski

On the Size and Generation of Minimal N-Detection Tests.........................................................................385

K. Kantipudi, V. Agrawal

Improving the Performance of Automatic Sequential Test Generation by Targeting Hardto-Test Faults ...................................................................................................................................................391
L. Lingappan, N. Jha

Low-Cost Production Testing of Wireless Transmitters .............................................................................397

A. Halder, A. Chatterjee

PANEL: VC FORUM
CHAIR: S. ANDRA
SPECIAL SESSION: EMERGING TECHNOLOGIES
CHAIRS: S. BASU AND S. LAHIRI
Double-Gate SOI Devices for Low-Power and High-Performance Applications ......................................403
K. Roy, H. Mahmoodi, S. Mukhopadhyay, H. Ananthan, A. Bansal, T. Cakici

Carbon Nanotube Electronics ........................................................................................................................411

A. Javey, H. Dai

SESSION 4A: SYNTHESIS AND PARTITIONING

CHAIRS: P. CHAKRABARTI AND J. ABRAHAM
Design of Heterogeneous Embedded Systems Using DFCharts Model of Computation ..........................417
I. Radojevic, Z. Salcic, P. Roop

Dynamic Template Generation for Resource Sharing in Control and Data Flow Graphs.......................421
D. Zaretsky, G. Mittal, R. Dick, P. Banerjee

Recovery-Based Real-Time Static Scheduling for Battery Life Optimization...........................................425

A. Lahiri, S. Agarwal, A. Basu, B. Bhattacharya

Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible

Processors ........................................................................................................................................................429
F. Sun, S. Ravi, A. Raghunathan, N. Jha

An Automatic Code Generation Tool for Partitioned Software in Distributed Systems ..........................433
V. Sairaman, N. Ranganathan, N. Singh

A High-Performance VLSI Architecture for Advanced Encryption Standard (AES)

Algorithm.........................................................................................................................................................437
N. Kosaraju, M. Varanasi, S. Mohanty

SESSION 4B: MEMORY AND LOGIC DESIGN

CHAIRS: K. VEEZHINATHAN AND K. SALUJA
Performance Measurement and Improvement of Asymmetric Three-Tr. Cell (ATC)
DRAM toward 0.3V Memory Array Operation ...........................................................................................441
M. Ichihashi, H. Toda

A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling

Scheme for Global Interconnects...................................................................................................................445
A. Narasimhan, B. Srinivasaraghavan, R. Sridhar

A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS
Technology.......................................................................................................................................................449
S. Jain, P. Agarwal

SEAT-LA: A Soft Error Analysis Tool for Combinational Logic ..............................................................453

R. Rajaraman, J. Kim, N. Vijaykrishnan, Y. Xie, M. Irwin

Exceptional ASIC: Through Automatic Timing Exception Generation (ATEG) .....................................457

S. Embanath, R. Venkata

An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing

for FPGAs ........................................................................................................................................................461
V. Garg, V. Chandrasekhar, M. Sashikanth, V. Kamakoti

SESSION 4C: COMMUNICATIONS AND MULTIMEDIA ARCHITECTURE I

CHAIRS: M. BALAKRISHNAN AND D. BHATTACHARYA
Optimized VLIW Architecture for Non-zero IF QAM-Modem Implementations....................................465
A. Pani, R. Kumar

Ultra Folded High-Speed Architectures for Reed-Solomon Decoders .......................................................469

K. Seth, K. Viswajith, S. Srinivasan, V. Kamakoti

A Wideband Frequency-Shift Keying Demodulator for Wireless Neural Stimulation

Microsystems ...................................................................................................................................................473
M. Dong, C. Zhang, S. Mai, Z. Wang, D. Li

Improved Data Compression for Serial Interconnected Network on Chip through Unused
Significant Bit Removal ..................................................................................................................................477
S. Ogg, B. Al-Hashimi

Novel Architecture of EBC for JPEG2000....................................................................................................482

A. Gautam, A. Madhuri, P. Khandelwal, K. Aditya, M. Desai, N. Krishna, M. Dutt, R. Bhatia

Real Time Dynamic Receive Apodization for an Ultrasound Imaging System .........................................486
J. Bhattacharyya, P. Mandal, R. Banerjee, S. Banerjee

SESSION 4D: VLSI TECHNOLOGY II

CHAIRS: N. BHAT AND K. CHAKRABORTY
Design Planning for Uniform Thermal Distribution....................................................................................490
R. Patrikar, O. Peyran

Solving Thermal Problems of Hot Chips Using Voronoi Diagrams ...........................................................494

S. Majumder, B. Bhattacharya

Design of Multi-bit SET Adder and Its Fault Simulation............................................................................498

D. Datta, S. Ganguly

Efficient Analog Performance Macromodeling via Sequential Design Space Decomposition..................502

M. Ding, R. Vemuri

A Single Supply Level Shifter for Multi-Voltage Systems ...........................................................................506

Q. Khan, S. Wadhwa, K. Misri

SESSION 5A: ANALOG AND MIXED-SIGNAL DESIGN II

CHAIRS: D. SHARMA AND H. JAMADAGNI
A Rail-to-Rail I/O Operational Amplifier with 0.5% gm Fluctuation Using Double Pchannel Differential Input Pairs ....................................................................................................................510
Z. Li, M. Yu, J. Ma

High Speed Robust Current Sense Amplifier for Nanoscale Memories: A Winner Take
All Approach ...................................................................................................................................................516
S. Sundaram, P. Elakkumanan, R. Sridhar

ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear FrontEnds: A Power and Performance Perspective ..............................................................................................522
I. Lu, N. Weste, S. Parameswaran

Techniques for On-chip Process Voltage and Temperature Detection and Compensation......................528
Q. Khan, G. Siddhartha, D. Tripathi, S. Wadhwa, K. Misri

Design of Low-Voltage Low-Power Continuous-Time Filter for Hearing Aid Application

Using CMOS Current Conveyor Based Translinear Loop .........................................................................534
D. Dutta, R. Ujjwal, S. Banerjee

An 8-Bit, 3.8GHz Dynamic BiCMOS Comparator for High-Performance ADC......................................540

S. Dey, S. Banerjee

SESSION 5B: LOW POWER / RF DESIGN

CHAIRS: A. CHANDORKAR AND K. MAHARATNA
Using Level Restoring Method for Dual Supply Voltage.............................................................................546
K. Sadeghi, M. Emadi, F. Farbiz

Statistical Estimation of Correlated Leakage Power Variation and Its Application to

Leakage-Aware Design ...................................................................................................................................551
M. Ashouei, A. Chatterjee, A. Singh, V. De, T. Mak

On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder ...............................558

K. Maharatna, A. Troya, M. Krstic, E. Grass

A Wide-Band Lumped Element Compact CAD Model of Si-Based Planar Spiral Inductor
for RFIC Design ..............................................................................................................................................564
S. Mandal, A. De, A. Patra, S. Sural

Generating Scalable Polynomial Models: Key to Low Power High Performance Designs.......................570
G. Girishankar, S. Tiwari

Zero Steady State Current Power on Reset Circuit with Brown-Out Detector.........................................576
S. Wadhwa, G. Siddhartha, A. Gaurav

SESSION 5C: EMBEDDED SYSTEMS

CHAIRS: P. DAS AND S. NAGANATHAN
Using Shiftable Content Addressable Memories to Double Memory Capacity on
Embedded Systems..........................................................................................................................................582
H. Lekatsas, J. Henkel, V. Jakkula, S. Chakradhar

Reinforcement Temporal Difference Learning Scheme for Dynamic Energy Management

in Embedded Systems .....................................................................................................................................588
L. Viswanathan, E. Monie

Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core.........................594
P. Biswas, S. Banerjee, N. Dutt, P. Ienne, L. Pozzi

A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and OnChip Networks.................................................................................................................................................600
T. Richardson, C. Nicopoulos, D. Park, V. Narayanan, Y. Xie, C. Das, V. Degalahal

SESSION 5D: DESIGN TOOLS

CHAIRS: M. DESAI AND S. BOSE
Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by
Scattering Parameters.....................................................................................................................................608
D. Saraswat, R. Achar, M. Nakhla

Efficient and Accurate EMC Analysis of High-Frequency VLSI Subnetworks ........................................613

G. Shinh, N. Nakhla, R. Achar, M. Nakhla, I. Erdin

Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time
Embedded Systems..........................................................................................................................................618
A. Sarkar, P. Chakrabarti, R. Kumar

Improving the Performance of CAD Optimization Algorithms Using On-Line Meta-level

Control .............................................................................................................................................................624
S. Aine, P. Chakrabarti, R. Kumar

Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits

Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction .........................................630
R. Chakraborty, M. Ranjan, R. Vemuri

Fast DC Analysis and Its Application to Combinatorial Optimization Problems.....................................636

G. Trivedi, M. Desai, H. Narayanan

SPECIAL SESSION: EMERGING TECHNOLOGIES

CHAIRS: S. BASU AND S. LAHIRI
Hybrid CMOS/Molecular Electronic Circuits..............................................................................................642
M. Stan, G. Rose, M. Ziegler

All-Printed RFID Tags: Materials, Devices, and Circuit Implications ......................................................648

V. Subramanian, P. Chang, D. Huang, J. Lee, S. Molesa, D. Redinger, S. Volkman

SESSION 6A: ANALOG DESIGN / MEMS

CHAIRS: T. BHATTACHARYYA AND A. CHATTERJEE
Threshold Trimming Based Design of a CMOS Programmable Operational Amplifier .........................654
R. Suri, C. Markan

Development of a Wireless Integrated Toxic and Explosive MEMS Based Gas Sensor...........................658
T. Bhattacharyya, S. Sen, D. Mandal, S. Lahiri

Custom Reconfigurable Architecture for Autonomous Fault-Recovery of MEMS

Vibratory Sensor Electronics .........................................................................................................................662
E. Stefatos, T. Arslan, D. Keymeulen, I. Ferguson

Efficient DNA Sensing with Fabricated Silicon Nanopores: Diagnosis Methodology and
Algorithms .......................................................................................................................................................666
S. Bhattacharya, V. Natarajan, A. Chatterjee, S. Nair

Area and Power Efficient VLSI Architecture for Computing Pseudo Inverse of Channel
Matrix in a MIMO Wireless System..............................................................................................................671
Z. Khan, T. Arslan, J. Thompson, A. Erdogan

CMOS Integrated Circuit for Sensing Applications ....................................................................................675

S. Shanbhag

SESSION 6B: LOW POWER DESIGN I

CHAIRS: A. PAL AND V. AGRAWAL
Semi-Custom Design of Adiabatic Adder Circuits.......................................................................................679
V. Bhaaskaran, S. Salivahanan, D. Emmanuel

Clockless Pipelining for Coarse Grain Datapaths ........................................................................................683

A. Alsharqawi, A. Ejnioui

Exploring Logic Block Granularity in Leakage Tolerant FPGA................................................................688

R. Konar, R. Bharadwaj, D. Bhatia, P. Balsara

High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial

Technologies with Enhanced-Mobility PFET Header .................................................................................692
K. Das, S.-H. Lo, C.-T. Chuang

An Alternative Real-Time Filter Scheme to Block Buffering......................................................................696

Y.-J. Chang

Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic

Analysis of Vth Variation ...............................................................................................................................700
A. Oruganti, N. Ranganathan

SESSION 6C: INTERCONNECT DESIGN II

CHAIRS: P. DASGUPTA AND R. VEMURI
Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM)
Routing.............................................................................................................................................................704
A. Joshi, V. Deodhar, J. Davis

A Progressive Two-Stage Global Routing for Macro-Cell Based Designs .................................................708

C. Alkan, T. Chen

Deterministic Low-Latency Data Transfer across Non-integral Ratio Clock Domains............................712

S. Balasubramanian, N. Natarajan, O. Franza, C. Gianos

SmartExtract: Accurate Capacitance Extraction for SOC Designs ...........................................................717

U. Narasimha, A. Hill, N. S. Nagaraj

Linear Required-Arrival-Time Trees and their Construction....................................................................721

P. Dasgupta, P. Yadav

A Methodology for Switching Activity Based IO Powerpad Optimisation................................................725

S. Roy, S. Jairam, H. Udayakumar

SESSION 6D: TEST AND DESIGN-FOR-TESTABILITY

CHAIRS: R. PAREKHJI AND P. AGRAWAL
Aliasing Analysis of Spectral Statistical Response Compaction Techniques .............................................729
O. Khan, M. Bushnell

Testing High-Speed IO Links Using On-Die Circuitry................................................................................735

P. Iyer, S. Jain, B. Casper, J. Howard

PIDISC: Pattern Independent Design Independent Seed Compression Technique..................................739

K. Balakrishnan, S. Wang, S. Chakradhar

Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive
Crosstalk Delay Faults ....................................................................................................................................746
S. Chary, M. Bushnell

An On-Chip Diagnosis Methodology for Embedded Cores with Replaceable Modules ...........................752
R. Tekumalla

The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for
Transition Faults .............................................................................................................................................756
I. Pomeranz, S. Reddy

Author Index