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DEPARTMENT
of
ELECTRONICS AND COMMUNICATION ENGINEERING
Regulation 2013
Academic Year: 2014-2015
Faculty In-charge
Mr.S.Rajalingam /AP/ECE
Mr.L.Franklin Telfer/AP/ECE
Mr.V.S.Vignesh/AP/ECE
Lab Assistant
Ms.T.Jeevitha
Semester 03
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SYLLABUS
EC6311 ANALOG AND DIGITAL CIRCUITS LABORATORY
LIST OF EXPERIMENTS
LIST OF ANALOG EXPERIMENTS:
1. Frequency Response of CE / CB / CC amplifier
2. Frequency response of CS Amplifiers
3. Darlington Amplifier
4. Differential Amplifiers- Transfer characteristic.
5. CMRR Measurement
6. Cascode / Cascade amplifier
7. Determination of bandwidth of single stage and multistage amplifiers
8. Spice Simulation of Common Emitter and Common Source amplifiers
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SL NO
LIST OF EXPERIMENTS
1.
2.
3.
4.
5.
6.
7.
8.
13.
14.
15.
Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters
16.
17.
9.
10.
11.
12.
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Date
Experiment Names
Pg No
Faculty Sign
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
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DATE:
1. OBJECTIVE:
To Design and Construct a Common Emitter Amplifier using voltage divider bias and to
determine its:
a. DC Characteristics
b. Maximum Signal Handling Capacity
c. Gain of the amplifier
d. Bandwidth of the amplifier
e. Gain -Bandwidth Product
2. REQUIREMENTS:
S.no
Requirement
Name
Transistor [Active]
Resistor [Passive]
Components
Range
BC 107
61k, 10k, 1k,
4.7k
Quantity
1
1,1,1,2
Capacitor [Passive]
10f, 100f
2,1
Signal Generator
(0-3)MHz
CRO
30MHz
(0-30)V
Equipment
6
supply
7
8
Semester 03
Regulated power
Bread Board
Accessories
Connecting Wires
Department of ECE
Single strand
1
as required
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THEORY:
A common emitter amplifier is type of BJT amplifier which increases the voltage level of the
applied input signal Vin at output of collector.
The CE amplifier typically has a relatively high input resistance (1 - 10 K) and a fairly high
output resistance. Therefore it is generally used to drive medium to high resistance loads. It is
typically used in applications where a small voltage signal needs to be amplified to a large
voltage signal like radio receivers.
The input signal Vin is applied to base emitter junction of the transistor and amplifier output
Vo is taken across collector terminal. Transistor is maintained at the active region by using the
resistors R1,R2 and Rc. A very small change in base current produces a much larger change in
collector current. The output Vo of the common emitter amplifier is 180 degrees out of phase
with the applied the input signal Vin.
4.
PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the CE amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE amplifier using AC analysis.
4. Set the input voltage Vin=V MSH /2 and vary the input signal frequency from 0Hz to 1MHz in
incremental steps and note down the corresponding output voltage Vo for at least 20
different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi) dB
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking
frequency on x-axis and gain in dB on y-axis.,
Bandwidth, BW = f2-f1
where f1 lower cut-off frequency
f2 upper cut-off frequency
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Steps:
i)
Set Vin = 0 by reducing the amplitude of the input signal from signal
generator
ii)
iii)
Set VCC= +10v and measure the voltage drop across the Resistor VRC, voltage
across Collector- Emitter Junction VCE and Voltage drop across base emitter
junction. VBE
iv)
Find the Q-point of the transistor and draw the DC load line.
To verify dc condition
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
Q point analysis:
It is the procedure to choose the opearating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )
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It is the process to find the maximum input voltage that can be handled by the
amplifier, so that it amplifies the input signal without any distortion.
Procedure:
i.
Apply input signal Vin = 20 mV of 1Khz frequency to the amplifier using the
signal generator between base emitter junction of the transistor. Find the
sinusoidal output using CRO across RL.
ii.
By increasing the amplitude of the input signal find maximum input voltage
V
MSH
across VBE at which the sinusoidal signal gets distorted during the
process which can be seen in the CRO. The amplitude obtained at this point
is maximum voltage that can be applied to the transistor for efficient
operating of transistor.
V MSH = _________ volts
MODEL GRAPH:
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S. NO
FREQUENCY [Hz]
in Volts
dB
1.
2.
100
3.
500
4.
600
5.
800
6.
900
7.
1 KHz
8.
100 KHz
9.
500 KHz
10.
600 KHz
11.
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
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FREQUENCY [Hz]
OUTPUT VOLTAGE [
VO] in Volts
1.
0
2.
100
3.
500
4.
600
5.
800
6.
900
7.
1 KHz
8.
100 KHz
9.
500 KHz
10.
600 KHz
11.
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
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WORKSHEET
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6. RESULT:
INFERENCE:
The Common Emitter Amplifier was constructed and the following results were determined:
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
c) Gain-Bandwidth product :
CONCLUSION:
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MODEL GRAPH:
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DATE:
1. OBJECTIVE:
To Design and Construct a Common collector Amplifier and to determine its:
a. DC Characteristics
b. Maximum Signal Handling Capacity
c. Gain of the amplifier
d. Bandwidth of the amplifier
e. Gain -Bandwidth Product using frequency response curve
2.
REQUIREMENTS:
S.No
Requirement
Range
Quantity
BC 107
Signal Generator
0-3MHz
CRO
0-30MHz
0-30 V
Single strand
as required
Name
Transistor [Active]
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
Bread Board
Accessories
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Given specifications:
VCC= 15V, I C=1.2mA, hie = 2.1k hFE= 75 hib= 27.6
(i)
(ii)
Av = _____
3. THEORY:
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junction of transistor the forward bias voltage Vbe is increased, which in turn increases the base
current Ib of transistor. Since emitter current Ie is directly proportional to I b the voltage drop across
the Emitter Ve= IeRe is increased, hence, output voltage Vo is increased, thus, we get positive halfcycle of the output. It means that a positive-going input signal results in a positive going output
signal and, consequently, the input and output signals are in phase with each other. Similarly the
negative half cycle of input signal produces negative going output signal.
Characteristics of a CC Amplifier
1. high input impedance (20-500 K )
2. low output impedance (50-1000 )
3. high current gain of (1 + ) i.e. 50 500
4. voltage gain of less than 1 (unity)
5. power gain of 10 to 20 dB
6. no phase reversal of the input signal
4. PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the CE amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE amplifier using AC analysis.
3. Set the input voltage Vin=V MSH /2 and vary the input signal frequency from 0Hz to 1MHz in
incremental steps and note down the corresponding output voltage Vo for at least 15
different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vin)
7. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking
frequency on x-axis and gain in dB on y-axis.,
Bandwidth, BW = f2-f1
Where
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DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
i)
ii)
iii)
iv)
Set Vin = 0 by reducing the amplitude of the input signal from signal
generator
Open circuit the capacitors since it blocks DC voltage
Set VCC= +10v and measure the voltage drop across the Resistor VRC, voltage
across Collector- Emitter Junction VCE and Voltage drop across base emitter
junction. VBE
Find the Q-point of the transistor and draw the DC load line.
To verify dc condition
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
Procedure:
i.
ii.
Apply input signal Vin = 1 V of 1Khz frequency to the CC amplifier using the
signal generator between base emitter junction of the transistor. Find the
sinusoidal output using CRO across RL.
By increasing the amplitude of the input signal find maximum input voltage
V MSH across VBE at which the sinusoidal signal gets distorted during the
process which can be seen in the CRO. The amplitude obtained at this point
is maximum voltage that can be applied to the transistor for efficient
operating of transistor.
V MSH = _________ volts
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S. NO
FREQUENCY
OUTPUT VOLTAGE
[Hz]
[ VO] in Volts
1.
2.
100
3.
500
4.
600
5.
800
6.
900
7.
1 KHz
8.
100 KHz
9.
500 KHz
10.
600 KHz
11.
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
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6. RESULT:
INFERENCE:
The common collector amplifier was constructed and input resistance and gain were determined.
The results are found to be as given below
a) Gain of the amplifier (in dB) :
b) Bandwidth of the amplifier (in Hz) :
c) Gain-Bandwidth product (GBWP) :
CONCLUSION:
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MODEL GRAPH:
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EXPERIMENT:03
DATE:
1. OBJECTIVE:
To Design and Construct a Common Base Amplifier and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product using frequency response curve
2. REQUIREMENTS:
S.No.
Requirement
Name
Transistor [Active]
Range
Quantity
BC 107
signal Generator
(0-3)MHz
CRO
30MHz
(0-30)V
Bread Board
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
Accessories
8
Semester 03
Connecting Wires
Department of ECE
Single strand
as required
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Semester 03
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The Common base amplifier typically has good voltage gain and relatively high output
impedance. But the Common base amplifier unlike CE amplifier has very low input impedance which
makes it unsuitable for most voltage amplifier. It is typically used used as an active load for a
cascode amplifier and also as a current follower circuit.
Circuit Opeartion:
A positive-going signal voltage at the input of a CB pushes the transistor emitter in a positive
direction while the base voltage remains fixed, hence Vbe reduces. The reduction in VBE results in
reduction in VRC, consequently VCE increases. The rise in collector voltage effectively rises the output
voltage. The positive going pulse at the input produces a positive-going output, hence the there is no
phase shift from input to output in CB circuit. In the same way the negative-going input produces a
negative-going output.
4. PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the CB amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE amplifier using
AC analysis.
4. Set the input voltage Vin=V MSH /2 and vary the input signal frequency from 0Hz to 1MHz in
incremental steps and note down the corresponding output voltage Vo for atleast 20
different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi)
5. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking
frequency on x-axis and gain in dB on y-axis.,
Bandwidth, BW = f2-f1
where f1 lower cut-off frequency
f2 upper cut-off frequency
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DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
i)
Set Vin = 0 by reducing the amplitude of the input signal from signal
generator
Open circuit the capacitors since it blocks DC voltage
Set VCC= +10v and measure the voltage drop across the Resistor VRC, voltage
across Collector- Emitter Junction VCE and Voltage drop across base emitter
junction. VBE
Find the Q-point of the transistor and draw the DC load line.
ii)
iii)
iv)
To verify dc condition
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
ii.
Apply input signal Vin = 20 mV of 1Khz frequency to the amplifier using the
signal generator between base emitter junction of the transistor. Find the
sinusoidal output using CRO across RL.
By increasing the amplitude of the input signal find maximum input voltage
V MSH across VBE at which the sinusoidal signal gets distorted during the
process which can be seen in the CRO. The amplitude obtained at this point
is maximum voltage that can be applied to the transistor for efficient
operating of transistor.
V MSH = _________ volts
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S. NO
FREQUENCY
[Hz]
17.
18.
100
19.
500
20.
600
21.
800
22.
OUTPUT VOLTAGE
[ VO] in Volts
900
23.
1 KHz
24.
100 KHz
25.
500 KHz
26.
600 KHz
27.
700 KHz
28.
800 KHz
29.
900 KHz
30.
1 MHz
31.
1.1 MHz
32.
1.5 MHz
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CONCLUSION:
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MODEL GRAPH:
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EXPERIMENT:04
DATE:
1. OBJECTIVE:
To Design and Construct a BJT amplifier using Darlington pair and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product using frequency response curve
2. REQUIREMENTS:
S.No.
Requirement
Name
Transistor [Active]
Range
Quantity
BC 107
Components
2
Resistor [Passive]
Capacitor [Passive]
signal Generator
(0-3)MHz
CRO
30MHz
(0-30)V
Equipment
Bread Board
Accessories
8
Semester 03
Connecting Wires
Department of ECE
Single strand
as required
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This configuration gives a much higher gain than each transistor taken separately and, in the
case of integrated devices, can take less space than two individual transistors because they can use
a shared collector. The Darlington amplifier typically has a relatively high input resistance (1 - 10 K)
and a fairly high output resistance. Therefore it is generally used to drive medium to high resistance
loads. It is typically used in applications where a small voltage signal needs to be amplified to a large
voltage signal like radio receivers.
4. PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the Darlington amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to Darlington amplifier using AC
analysis.
4. Set the input voltage Vin=V MSH /2 and vary the input signal frequency from 0Hz to 1MHz in
incremental steps and note down the corresponding output voltage Vo for at least 20
different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi)
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking
frequency on x-axis and gain in dB on y-axis.,
Bandwidth, BW = f2-f1
where f1 - lower cut-off frequency
f2 - upper cut-off frequency
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DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
i)
Set Vin = 0 by reducing the amplitude of the input signal from signal
generator
Open circuit the capacitors since it blocks DC voltage
Set VCC= +10v and measure the voltage drop across the Resistor VRC, voltage
across Collector- Emitter Junction VCE and Voltage drop across base emitter
junction. VBE
Find the Q-point of the transistor and draw the DC load line.
ii)
iii)
iv)
To verify dc condition
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
ii.
Apply input signal Vin = 20 mV of 1Khz frequency to the amplifier using the
signal generator between base emitter junction of the transistor. Find the
sinusoidal output using CRO across RL.
By increasing the amplitude of the input signal find maximum input voltage
V MSH across VBE at which the sinusoidal signal gets distorted during the
process which can be seen in the CRO. The amplitude obtained at this point
is maximum voltage that can be applied to the transistor for efficient
operating of transistor.
V MSH = _________ volts
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5. TABULATION
Input voltage (Vin=V MSH/2) =____________ V
S. NO
FREQUENCY
[Hz]
1.
2.
100
3.
500
4.
600
5.
800
6.
OUTPUT VOLTAGE
[ VO] in Volts
dB
900
7.
1 KHz
8.
100 KHz
9.
500 KHz
10.
600 KHz
11.
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
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WORKSHEET
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6. RESULT:
INFERENCE:
The Darlington amplifier was constructed and the results are found to be
a. Gain of the amplifier :
b. Bandwidth of the amplifier :
c. Gain-Bandwidth product :
CONCLUSION:
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MODEL GRAPH:
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DATE:
OBJECTIVE:
To Design and Construct a Common source amplifier using the bootstrapped gate resistance
and to determine its:
a.
b.
c.
d.
e.
2.
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product
REQUIREMENTS:
S.No.
Requirement
Name
Transistor [Active]
Range
Quantity
BFW10
signal Generator
(0-3)MHz
CRO
30MHz
(0-30)V
Bread Board
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
Accessories
8
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impedance :
Zi = RG ; Assume RG = 1M
iv) To Find output impedance :
ZO = RD ||
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Set Vin = 0 by reducing the amplitude of the input signal from signal
generator
Open circuit the capacitors since it blocks DC voltage
Set VCC= +10v and measure the voltage drop across the Resistor VRC, voltage
across Collector- Emitter Junction VCE and Voltage drop across base emitter
junction. VBE
Find the Q-point of the transistor and draw the DC load line.
ii)
iii)
iv)
To verify dc condition
1. VGS :
= ____________
2. VDS
= ____________
3 ID
= _______
ii.
Apply input signal Vin = 1 V of 1Khz frequency to the CS amplifier using the
signal generator between base emitter junction of the transistor. Find the
sinusoidal output using CRO across RL.
By increasing the amplitude of the input signal find maximum input voltage
V MSH across VBE at which the sinusoidal signal gets distorted during the
process which can be seen in the CRO. The amplitude obtained at this point
is maximum voltage that can be applied to the transistor for efficient
operating of transistor.
V MSH = _________ volts
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S. NO
FREQUENCY
[Hz]
1.
2.
100
3.
500
4.
600
5.
800
6.
OUTPUT VOLTAGE [
VO] in Volts
900
7.
1 KHz
8.
100 KHz
9.
500 KHz
10.
600 KHz
11.
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
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6. RESULT:
INFERENCE:
The common Source amplifier was constructed and input resistance and gain were determined. The
results are found to be as given below
a) Gain of the amplifier (in db) :
b) Bandwidth of the amplifier (in HZ) :
c) Gain-Bandwidth product (GBWP) :
CONCLUSION:
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MODEL GRAPH:
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DATE:
OBJECTIVE:
To Design and Construct a Cascade Amplifier and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product
2. REQUIREMENTS:
S.No.
Requirement
Name
Transistor [Active]
Range
Quantity
BC 107
Components
2
Resistor [Passive]
Capacitor [Passive]
signal Generator
(0-3)MHz
CRO
30MHz
(0-30)V
Equipment
Bread Board
Accessories
8
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(i) To calculate R5 :
Assume VE1 = 5V , VCE1 = VCE2 = 3V;
VB2 = VC1 = VE1 + VCE1 = 5V + 3V = 8V
VE2 = VB2 VBE = 8V 0.7V = 7.3V
VR5 = Vcc VE2 VCE2 = 14V 7.3V 3V = 3.7V
Choose R5 = RL / 10 = 40K / 10 = 4K ;
IC2 = ( VR5 / R5 ) = 3.7V / 3.9K = 1000A
(ii) To calculate R6 :
VR6 = VE2 / IC2 = 7.7K;
IC2 = VE2 / R6 = 7.3V / 8.2 K = 890A
(iii) To calculate R1, R2 , R3 & R4:
Voltage across resistor R3 is given by
VR3 = Vcc VC1 = 14V 8V = 6V
R3 = VR3 / IC1 = 6V / 1mA = 6K
R4 = VE1 / IC1 = 5V/ 1mA = 4.7K
Voltage across resistor R2 is given by
VR2 = VE1 VBE = 5V + 0.7V =5.7V
R2 = 10 R4 = 4.7 K
VR1 = VCC VB1 = 14V + 5.7V =8.3V
R1 = [ VR1 x R2 / VR2] = 68.4 K
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4. PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to amplifier using AC analysis.
4. Set the input voltage Vin=V MSH /2 and vary the input signal frequency from 0Hz to 1MHz in
incremental steps and note down the corresponding output voltage Vo for atleast 20
different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi)
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking
frequency on x-axis and gain in dB on y-axis.,
Bandwidth, BW = f2-f1
where f1 - lower cut-off frequency
f2 - upper cut-off frequency
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Set Vin = 0 by reducing the amplitude of the input signal from signal
generator
Open circuit the capacitors since it blocks DC voltage
Set VCC= +10v and measure the voltage drop across the Resistor VRC, voltage
across Collector- Emitter Junction VCE and Voltage drop across base emitter
junction. VBE
Find the Q-point of the transistor and draw the DC load line.
vi)
vii)
viii)
To verify dc condition
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
iv.
Apply input signal Vin = 20 mV of 1Khz frequency to the amplifier using the
signal generator between base emitter junction of the transistor.Find the
sinusoidal output using CRO across RL.
By increasing the amplitude of the input signal find maximum input voltage
V MSH across VBE at which the sinusoidal signal gets distorted during the
processwhich can be seen in the CRO. The amplitude obtained at this point
is maximum voltage that can be applied to the transistor for efficient
operating of transistor.
V MSH = _________ volts
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FREQUENCY
[Hz]
1.
2.
100
3.
500
4.
600
5.
800
6.
OUTPUT VOLTAGE
[ VO] in Volts
900
7.
1 KHz
8.
100 KHz
9.
500 KHz
10.
600 KHz
11.
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
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6. RESULT:
INFERENCE:
The Cascade amplifier was constructed and input resistance and gain were determined. The results
are found to be as given below
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
c) Gain-Bandwidth product :
CONCLUSION:
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MODEL GRAPH:
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DATE:
1. OBJECTIVE:
To Design and Construct a Cascode Amplifier and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product
2. REQUIREMENTS:
S.No.
Requirement
Name
Range
Quantity
Transistor [Active]
BC 107
Resistor [Passive]
61k,
4.7k
Capacitor [Passive]
10f, 100f
signal Generator
(0-3)MHz
CRO
30MHz
(0-30)V
Components
10k,
1k,
1,1,1,2
2,1
Equipment
Bread Board
Accessories
8
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Connecting Wires
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as required
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DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
ix)
Set Vin = 0 by reducing the amplitude of the input signal from signal
generator
x)
Open circuit the capacitors since it blocks DC voltage
xi)
Set VCC= +10v and measure the voltage drop across the Resistor VRC, voltage
across Collector- Emitter Junction VCE and Voltage drop across base emitter
junction. VBE
xii)
Find the Q-point of the transistor and draw the DC load line.
To verify dc condition
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
vi.
Apply input signal Vin = 20 mV of 1Khz frequency to the amplifier using the
signal generator between base emitter junction of the transistor.Find the
sinusoidal output using CRO across RL.
By increasing the amplitude of the input signal find maximum input voltage
V MSH across VBE at which the sinusoidal signal gets distorted during the
processwhich can be seen in the CRO. The amplitude obtained at this point
is maximum voltage that can be applied to the transistor for efficient
operating of transistor.
V MSH = _________ volts
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5. TABULATION
Input voltage (Vin=V MSH/2) =____________ V
S. NO
FREQUENCY
[Hz]
1.
2.
100
3.
500
4.
600
5.
800
6.
OUTPUT VOLTAGE
[ VO] in Volts
dB
900
7.
1 KHz
8.
100 KHz
9.
500 KHz
10.
600 KHz
11.
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
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6. RESULT:
INFERENCE:
The Cascode amplifier was constructed and input resistance and gain were determined. The results
are found to be as given below
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
c) Gain-Bandwidth product :
CONCLUSION:
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Differential Mode :
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DATE:
1. OBJECTIVE:
To Design and Construct a Differential Amplifier using BJT and to determine its:
a.
b.
c.
d.
Transfer Characteristics
Gain of the amplifier in common mode
Gain of the amplifier in differential mode
CMRR (Common Mode Rejection Ratio)
2. REQUIREMENTS:
S.No.
Requirement
Name
Transistor [Active]
Range
Quantity
BC 107
Components
2
Resistor [Passive]
Capacitor [Passive]
signal Generator
(0-3)MHz
CRO
30MHz
(0-30)V
Equipment
Bread Board
Accessories
8
Connecting Wires
Single strand
as required
3. THEORY:
A differential amplifier is a type of electronic amplifier that amplifies the difference
between two voltages but does not amplify the particular voltages. The need for differential
amplifier arises in many physical measurements where response from D.C to many MHZ is
required. It is also used in input stage of integrated amplifier.
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ii)
iii)
4. PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the Differential amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to amplifier using
AC analysis.
4. Determine the Transfer characteristics of Differential amplifier by plotting the graph for
normalized differential input voltage [ (Vb1 Vb2) / VT ] vs. Normalized collector current [ Ic / Io].
5. Calculate the voltage gain of differential amplifier for differential mode
as Ad = 20log (V0/Vi) , Where Vi = V1 V2
6. Calculate the voltage gain of differential amplifier for Common mode
as AC = 20log (V0/Vi) , Where Vi = (V1+ V2 / 2 )
7. Find the Common mode rejection ratio of differential amplifier using the formula given
below.
CMRR= 20 log10 ( Ad/Ac)
Where Ad- Differential mode gain in dB
Ac Common Mode gain in dB
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DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
i)
Set Vin = 0 by reducing the amplitude of the input signal from signal
generator
Open circuit the capacitors since it blocks DC voltage
Set VCC= +10v and measure the voltage drop across the Resistor VRC, voltage
across Collector- Emitter Junction VCE and Voltage drop across base emitter
junction. VBE
Find the Q-point of the transistor and draw the DC load line.
ii)
iii)
iv)
To verify dc condition
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
Q point analysis:
It is the procedure to choose the operating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )
b. Maximum signal handling capacity :
It is the process to find the maximum input voltage that can be handled by the
amplifier, so that it amplifies the input signal without any distortion.
Procedure:
vii.
viii.
Apply input signal Vin = 20 mV of 1Khz frequency to the amplifier using the
signal generator between base emitter junction of the transistor. Find the
sinusoidal output using CRO across RL.
By increasing the amplitude of the input signal find maximum input voltage
V MSH across VBE at which the sinusoidal signal gets distorted during the
process which can be seen in the CRO. The amplitude obtained at this point
is maximum voltage that can be applied to the transistor for efficient
operating of transistor.
V MSH = _________ volts
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Input Voltage
Vi = (Vb1 Vb2) in Volts
Output Current
Ic2 in Ampere
1.
2.
3.
4.
5.
6.
b. CMRR Calculation:
To Find Differential Gain (Ad ) :
S. NO
INPUT
VOLTAGE
in volts
Differntial gain in dB
Ad = 20log (V0/Vi)
Where Vi = Vi1 Vi2
33.
Vi1
34.
Vi2
INPUT
VOLTAGE
in volts
1.
Vi1
2.
Vi2
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6. RESULT:
INFERENCE:
The Differential amplifier was constructed and input resistance and gain were determined. The
results are found to be as given below
d) Trans-Conductance of Differential amplifier ( in millisiemens) :
e) Differential mode gain in dB
f)
g) CMRR in dB
CONCLUSION:
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DATE:
1. OBJECTIVE:
To Design and Construct a Common Emitter Amplifier using Pspice simulation tool and to
determine its:
a. Gain of the amplifier
b. Bandwidth of the amplifier
c. Gain -Bandwidth Product
2. REQUIREMENTS:
S.no
Requirements
Quantity
PC
Pspice Software
THEORY:
A common emitter amplifer is type of BJT amplifier which increases the voltage level of the
applied input signal Vin at output of collector.
The CE amplifier typically has a relatively high input resistance (1 - 10 K) and a fairly high
output resistance. Therefore it is generally used to drive medium to high resistance loads. It is
typically used in applications where a small voltage signal needs to be amplified to a large
voltage signal like radio receivers.
The input signal Vin is applied to base emitter junction of the transistor and amplifier output
Vo is taken across collector terminal. Transistor is maintained at the active region by using the
resistors R1,R2 and Rc. A very small change in base current produces a much larger change in
collector current. The output Vo of the common emitter amplifier is 180 degrees out of phase
with the applied the input signal Vin.
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MODEL GRAPH:
4.RESULT:
INFERENCE:
The Common Emitter Amplifier was simulated and the following results were determined:
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
c) Gain-Bandwidth product :
CONCLUSION:
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DATE:
1. OBJECTIVE:
To Design and Construct a Common Emitter Amplifier using Pspice simulation tool and to
determine its:
a. Gain of the amplifier
b. Bandwidth of the amplifier
c. Gain -Bandwidth Product
2. REQUIREMENTS:
S.no
Requirements
Quantity
PC
Pspice Software
THEORY:
There are three basic types of FET amplifier or FET transistor namely common source
amplifier, common gate amplifier and source follower amplifier.
The common-source (CS) amplifier may be viewed as a transconductance amplifier or as a
voltage amplifier.
i) As a transconductance amplifier, the input voltage is seen as modulating the current going
to the load.
ii) As a voltage amplifier, input voltage modulates the amount of current flowing through the
FET, changing the voltage across the output resistance according to Ohm's law.
However, the FET device's output resistance typically is not high enough for a reasonable
transconductance amplifier (ideally infinite), nor low enough for a decent voltage amplifier (ideally
zero). Another major drawback is the amplifier's limited high-frequency response. Therefore, in
practice the output often is routed through either a voltage follower (common-drain or CD stage), or
a current follower (common-gate or CG stage), to obtain more favorable output and frequency
characteristics
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3. PROCEDURE:
1. Click on the start menu and select the pspice simulation software
2. Select the parts required for the circuit from the parts menu and place
them in the work space
3. Connect the parts using wires
4. Save the file and select the appropriate analysis
5. Simulate the circuit and observe the corresponding output waveforms
MODEL GRAPH:
4.RESULT:
INFERENCE:
The Common Emitter Amplifier was simulated and the following results were determined:
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
c) Gain-Bandwidth product :
CONCLUSION:
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DIGITAL EXPERIMENTS
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DATE:
1. OBJECTIVE:
To design and verify the truth table of the following code converters
a. Binary to Gray converter
b. Gray to Binary converter &
c. BCD to Excess3 &
d. Excess3 to BCD.
2. REQUIREMENTS:
S. No.
1.
2.
3.
3. THEORY:
Components / Equipments
Digital IC trainer
NOT, AND, OR, Ex-OR Gate
Connecting wires
Specifications
Quantity
---
IC7404,7408,7432,7486
---
1 in each
Sufficient
numbers
By representing the ten decimal digits with a four bit Gray code, we have another form
of BCD code. The Gray code however can be extended to any number of bits and conversion
between binary code and Gray code is sometimes useful. The following rules apply for conversion:
1. The MSB in the Gray code is the same as the corresponding bit in the binary number.
2. Going from left to right, add each adjacent pair of binary bits to get the next Gray code bit.
Disregard carries.
GRAY to Binary Converter:
To convert from Gray code to binary code, A similar method is used, at there are some
differences. The following rules apply:
1. The MSB in the binary code is the same as the corresponding digit in the Gray code
2. Add each binary digit generated to the gray digit in the next adjacent position Disregard
carries.
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Binary input
B3
B2
B1
B0
G3
G2
G1
G0
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G3 = B3
K-Map for G2:
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Gray Code
Binary Code
G3
G2
G1
G0
B3
B2
B1
B0
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B3 = G3
K-Map for B2:
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BCD input
Excess 3 output
B3
B2
B1
B0
G3
G2
G1
G0
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E3 = B3 + B2 (B0 + B1)
K-Map for E2:
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Excess 3 Input
BCD Output
B3
B2
B1
B0
G3
G2
G1
G0
K-Map for A:
A = X1 X2 + X3 X4 X1
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K-Map for C:
K-Map for D:
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4. PROCEDURE:
1. Connections are given as per the circuit diagram (Binary to GRAY).
2. Switch on the power supply.
3. Verify the truth table given for different inputs.
4. Repeat the above procedures for other converters.
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5. Results:
INFERENCE:
Thus the truth tables for Binary to Gray, Gray to Binary and BCD to Excess3 converters were
verified.
CONCLUSION:
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DATE:
1. OBJECTIVE:
To study the 4 bit binary adder/subtractor using IC7483.
2. REQUIREMENTS:
S.No.
Specifications
Quantity
OR gate
IC 7432
AND gate
IC 7408
IC 7483
Connecting wires
some
3. THEORY:
The full adder/sub tractors are capable of adding/subtracting only two single digit binary
numbers along with a carry input. But in practice we need to add/subtract binary numbers, which
are much longer than just one bit. To add/subtract two n-bit binary numbers we need to use the nbit parallel subtractor/adder.
Binary adder: IC type 7483 is a 4-bit binary parallel adder/subtractor .The two 4-bit input
binary numbers are A1 through A4 and B1 through B4. The sum is obtained from S1 through S4. C0 is
the input carry and C4 the output carry. Test the 4-bit binary adder 7483 by connecting the power
supply and ground terminals. Then connect the four A inputs to a fixed binary numbers such as 1001
and the B inputs and the input carry to five toggle switches. The five outputs are applied to indicator
lamps. Perform the addition of a few binary numbers and check that the output sum and output
carry give the proper values. Show that when the input carry is equal to 1, it adds 1 to the output
sum.
Binary subtractor :
The subtraction of two binary numbers can be done by taking the 2s
complement of the subtrahend and adding it to the minuend. The 2s complement can be obtained
by taking the 1s complement and adding. To perform A-B, we complement the four bits of B, add
them to the four bits of A, and add 1 through the input carry. The four XOR gates complement the
bits of B when the mode select M=1(because x 0 x ) and leave the bits of B unchanged when
M=0(because x 0 x ) .Thus , when the mode select M is equal to 1, the input carry C0 is equal 1
and the sum output is A plus the 2s complement of B. when M is equal to 0, the input carry is equal
to 0 and the sum generates A+B.
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Operand1
Operand2
B3 B2 B1 B0
A3 A2 A1 A0
C4
C0
4 bit IC 7483
O/P
Pin Diagram of IC7483:
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CARRY
S4
S3
S2
S1
K MAP
Y = S4 (S3 + S2)
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4. PROCEDURE:
1.
2.
3.
4.
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DATE:
1. OBJECTIVE:
To design and implement multiplexer and demultiplexer using logic gates
2. REQUIREMENTS :
S.No.
Specification
Quantity
OR gate
IC7432
AND gate
IC7411
NOT gate
IC7404
Connecting wires
3. THEORY:
Multiplexer:
It has a group of data inputs and a group of control inputs. The control inputs are
used to select one of the data inputs and connected to the output terminal. It selects one
information out of many information lines and directed to a single output line.
Demultiplexer:
Demultiplexers perform the opposite function of multiplexers. They transfer a small
number of information units (usually one unit) over a larger number of channels under the
control of selection signals. Fig shows a 1-line to 2-line Demultiplexer circuit. Construct this
circuit; connect an LED to each of the outputs D0 and D1. Set the select signal S to logic 1 or
logic 0, and toggle the input I between logic 1 and logic 0. Which output followed the input
when S = 1 and S = 0.
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4:1 MULTIPLEXER:
BLOCK DIAGRAM
Circuit Diagram:
Truth Table:
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S1
S0
I0
I1
I2
I3
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:
Circuit Diagram:
Truth Table:
Selection Lines
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S1
S0
D0=Di
D1= Di
D2= Di
D3= Di
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TRUTH TABLE:
8X1 Multiplexer
S0
S1
D0
D1
D2
D3
O/P
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TRUTH TABLE
1:8 DEMULTIPLEXER:
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5. RESULTS
INFERENCE :
Thus the truth table of multiplexer and demultiplexer was studied and verified using logic
gates.
CONCLUSION:
6. VIVA QUESTIONS:
1.
2.
3.
4.
5.
6.
What is a multiplexer?
What are the applications of multiplexer?
What is the difference between multiplexer & demultiplexer?
In 2n: 1 multiplexer how many selection lines are used?
Draw a 2 to 1 multiplexer circuit
Draw a 1 to 2 demultiplexer circuit.
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EXPERIMENT:12.a.
DATE:
1. OBJECTIVE:
To construct and verify the 8 X 3 Encoder using logic gates.
2. REQUIREMENTS:
S. No
Components / Equipments
Specification
Quantity
1.
2.
OR Gate
IC7432
3.
Connecting Wires
Sufficient Numbers
3. THEORY:
Digital Computers, Microprocessors and other digital systems are binary operated
whereas our language of communication is in decimal numbers and alphabetical characters
only. Therefore, the need arises for interfacing between digital system and human operators.
To accomplish this task, Encoder is used.
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Truth Table:
INPUT
OUTPUT
D0
D1
D2
D3
D4
D5
D6
D7
Outputs:
A = D4 + D5 + D6 + D7
B = D2 + D3 + D6 + D7
C = D1 + D3 + D5 + D7
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4. PROCEDURE:
1. Construct the circuit as per the diagram
2. Switch on the power supply.
3. Apply the necessary input and observe the outputs to verify the truth table.
5. RESULTS:
INFERENCE:
Thus an 8 x 3 encoder is constructed and verified.
CONCLUSION:
6. REVIEW QUESTIONS:
1. Draw the basic block diagram of a practical decoder.
2. What is the need for decoder?
3. Name the procedure involved in decoding.
4. Give some practical applications where decoding is necessary.
5. List the advantages of decoding.
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EXPERIMENT:12.b
DATE:
1. OBJECTIVE :
To construct and verify the decoder / driver along with seven segment LED display unit and
verify the results.
2. REQUIREMENTS :
S. No.
1.
2.
3.
4.
5.
Components / Equipments
Specification
Quantity
Decoder
IC 7447
Common Anode
Resistors
330
IC Trainer Kit
---
Connecting Wires
---
Required
numbers
3. THEORY:
The 7-segment LED display is the most popular display device used in digital systems.
To use this device the data that is in the BCD form has to be changed suitably. For this
purpose a BCD to 7-segment decoder is required. The IC7447 is a BCD to 7-segment pattern
converter. . The 7447 converts the four input bits (BCD) to their corresponding 7-segment
codes. The outputs of the 7447 are connected to the 7-segment display.
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4. PROCEDURE:
1.
2.
3.
5. RESULTS:
INFERENCE :
A decoder / driver unit along with 7 segment display unit is constructed and the
results were verified.
CONCLUSION:
6. REVIEW QUESTIONS:
1. Draw the basic block diagram of a practical decoder.
2. What is the need for decoder?
3. Name the procedure involved in decoding.
4. Give some practical applications where decoding is necessary.
5. List the advantages of decoding.
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EXPERIMENT: 13
DATE:
1 . OBJECTIVE:
To construct and verify the synchronous up/down counters.
2. REQUIREMENTS:
S. No.
Components / Equipments
Specification
Quantity
1.
----
2.
IC 7473,7408
2,1
3.
Connecting wires
----
Sufficient Nos
3. THEORY:
Synchronous Counter
Clock input is applied simultaneously to all flip-flops. The output of the first FLIP-FLOP is
connected to the input of second FLIP-FLOP and so on.
Design of synchronous counter
Step 1: Find the number of flip-flops required. For an n-bit counter, n- flip-flops is
required.
Step 2: Write the count sequence in tabular form.
Step 3: Determine the flip-flop inputs, which must be present for the desired next State
from the present state using excitation table of flip-flops.
Step 4: Prepare K-map for each flip-flop input in terms of flip-flop output as input
Variables. Simplify the K-map and obtain the minimized expressions.
Step 5: Connect the circuit using the flip-flops.
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Pin Diagram
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Clock
Q2
Q1
Q0
Clock
Q2
Q1
Q0
4. PROCEDURE:
1. The connections are made as per the circuit diagram.
2. Switch on the power supply.
3. The input is given at the appropriate terminal and corresponding output is observed
and truth table is verified.
5. RESULTS:
INFERENCE:
Thus the counters were constructed and their truth tables verified.
CONCLUSION:
6. REVIEW QUESTIONS
1.
2.
3.
4.
5.
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DATE:
1. OBJECTIVE:
To implement the 4 bit shift register using flip flops and to study the operations in the
following modes.
(i)
(ii)
(iii)
(iv)
2. REQUIREMENTS:
S.No.
D Flip Flop
Connecting wires
Range
Quantity
1
IC 7474
2
some
3. THEORY:
SHIFT REGISTER:
A register is a device capable of storing a bit. The data can be serial or parallel. The
register can convert a data from serial to parallel and vice versa shifting then digits to left and right is
the important aspect for arithmetic operations,
A register capable of shifting its binary information either to the right or to the left is
called a shift register. An N bit shift register consists of N flip-flops and the gates that control the
shift operation. A shift register can be used in four different configurations depending upon the way
in which the data are entered into and taken out of it. These four configurations are:
a.
b.
c.
d.
Serial-input, Serial-output
Parallel-input, Serial-output
Serial-input, parallel-output
Parallel-output, parallel-output
The serial input is a single line going to the input of the leftmost flip-flop of the register. The
serial output is a single line from the output of the rightmost flip-flop of the register, so that the
bits stored in the register can come out through this line one at a time.
The parallel output consists of N lines, one for each of the flip-flops in the register, so the
information stored in the register can be inspected through these lines all at once.
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PIN DIAGRAM:
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Q3
Q2
Q1
Q0
O/P
4. PROCEDURE:
1. The flip-flop is connected using connecting wires as shown in the circuit.
2. The flip flop are then reset to zero internally with the help of reset to set inputs.
3. The bits are shifted in by giving suitable clock input.
4. Thus the truth table is then verified.
5.
RESULTS:
INFERENCE:
Thus the operation of 4 bit shift register for SISO, SIPO, and PIPO was
studied and verified.
CONCLUSION:
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DATA SHEETS
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FEATURES
APPLICATIONS
amplification.
DESCRIPTION
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