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SERVICE MANUAL
MODEL NO. H-PDP4201
Hyundai
CONTENTS
Part:PP06 Chassis Features and Circuit
Part:Introduction on Circuit Functions of PT4206
Part:Analysis on Signal Process of PT4206
Part:Typical Defectives and Repair of PT4206
Annex:
8523(RGB)480
16,777,216
1.095mm(H)1.110mm(V)
High brightness
High contrast
20000 Hours
U/D160 / L/R160
933mmH533mm(V)
Remarks: Brightness and contrast may vary because of different panels being used.
PDP Panel Resolution
Colors
Dot Pitch
Brightness
Contrast
Lifespan of Panel
Viewing Angle
Response Time
640480/60Hz
800600/60Hz
Unsupportable
Input
Indication
Color Temp. Adjust.
Quick Plug-In & Use
Format
Yes
Yes
Yes
Yes
Compatible with
HD Signal
DVI
Compatible with
Video
Including
S-Video
Audio
Input Voltage
Rating
Consumption
Standby
Consumption
480P576P720P 1080i
480P576P720P
1080i and HDTV
PAL/NTSC/SECAM
D/K I B/G M
Yes
Yes
Picture System
Sound System
Digital Comb Filter
3D Comb Filter NTSC
Movement Compensation Function
Output Voltage
Audio Effect
NICAM/IGR
Video/YpbPr Audio Input
PC/DVI Audio Input
220V~, 50Hz
400W
Yes
2 5W
W OW
Yes
Audio L/R
Audio L/R
3W
1.2Main Features
1.2.1 Terminals
RF Input
1Rear
S Terminal Input
1Rear
A/V Input
RCA1Rear
YCbCr
RCA1Rear
DTV YPbPr
RCA1Rear
VGA/SVGA Input
Hi-Density D-SUB 15 pin connector1Rear
DVI Input
1 Rear
A/V Output
RCA Rear
Remarks: PT4206 is equipped with a service terminal, which service people can connect with
PC RS232 terminal to upgrade the software.
1.2.2 Working Condition Requirement:
Working Condition Requirement
Temperature
040
Humidity
2070
Altitude
02000m
1.2.3 Others
Tuning System
FS Tuning236 Programs
NICAM Demodulation
Audio Effect Process
Picture Freeze
On Screen Display
Blue Background without Signal
Power Saving
Yes
AV stereoSRS WOW5 Bands Equalizer
TV/AV/S-VIDEO/YcbCr Only
Chinese/English, Menu Location movable by user.
Yes
When TV is connected with PC input, while there is
no signal from PC, after 60 seconds, TV will be
automatically off and enter into Power Saving Mode.
Press any key on TV or R/C, or there is signal from
PC again, TV will be switched on automatically.
When this function is on, pictures will move on
regularly to protect the screen.
When this function is on, the screen will be
completely white to clear up slight shadowsplease
see the instruction manual for more details
Users can choose between 15 minutes auto-off without
signal or 3 hours auto-off without operationplease
see the instruction manual for more details
Pixel Movement
White Screen Display
1.3CBU Content
1.3.1 PDP Inside Drawing:
rial No.
Name
Front Cabinet
Filter Glass
Shelve Bar
Back Cabinet
Remarks: This drawing is for references only, please see the main assembly diagram
and wire-connecting diagram for details.
1.3.2 Circuit Content
The main content of PP06 circuit include: Power Regulating Circuit, RF Circuit, VGA,
Analog Video, Digital Video Signal Processing Circuit, System Control Circuit, Button Control
Circuit. Reference drawing as below:
NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
N901
N601
U705
U701
N902
U1
U6
U11
U16
U17
U22
U20
U7
U9/U13
U71
U8
U19
U4
U5
U3
Function
TYPE
Unify tuner
Sound disposal
sound amplifier
NTSC 3D comb filter
AV video switch
Digital video disposal
A/D converter
DVI signal disposal
Format transform and MCU
FLASH ROM
Difference transmit
RS-232 signal disposal
EPROMdisplay parameter information
Suffer amplifier
Sync. face lifting enlarge
EPROMDVI parameter information
EPROMuser control information
SDRAM
RGB/YpbPr switch
IP transform and picture improve
TDQ-6F7-FM2W
MSP3410G-C12-100
TA2024
uPD64083GF-3BA
TEA6425D
VPC3230D-QA-B3
MST9885
SiI161BCT100
PW113-20Q
AM29LV800BT-90
DS90C383AMTD
ST232CD
24LC21A/SN
SN74LVC126AD
74LV32D
24LC21A/SN
24LC32A/SN
IS42S16400(A)-7T
PI5V330(Q)
PW1235
name
RED0RED7
GREEN0GREEN7
BLUE0BLUE7
DATACK
HSOUT
SOGOUT
VSOUT
MIDSCV
REFBYP
VSYNC
HSYNC
BAIN
SOGIN
GAIN
RAIN
COAST
CLAMP
A0
SCL
SDA
FILT
AVDD
Function
Red output data
Green output data
Blue output data
Output data clock
HSYNC output
Sync-on- Green Slicer output
VSYNC output
Internal mid-scale voltage bypass
Internal reference bypass
Vertical SYNC input
Horizontal SYNC input
Blue analog input
Sync-on- Green analog input
Green analog input
Red analog input
Hold PLL frequency and do not track HSYNC
External clamp input(we connect it to ground
Serial interface address pin
I2C busclock
I2C busdata
PLL connect to external filter
Analog power
V33
PVDD
GND
PLL power
ground
2.2.2VPC3230 General
VPC3230 Pin Function Descriptions
Pin No.
13
46
76430
111225
356577
465168
80
8
9
102936
4552
596976
13
14
15
16
17
18
1923
24
27
28
3134
Pin Name
R1G1B1IN
R2G2B2IN
GND
Short Description
RGB Analog Component Input 1
RGB Analog Component Input 2
GND
NC
VSUPCAP
V33
NC
Supply Voltage, Digital Decoupling Circuitry
Supply Voltage, Digital Circuitry
AVCC
SCL
SDA
RESQ
TEST
VGAV
YCOEQ
FFIE
CLK20
LLC2
LLC1
Y0Y7
Analog Voltage
I2C Bus Clock
I2C Bus Data
Reset Input
Test Pin
VGAV Input
Y/C Output Enable Input
NC
Main Clock Output
Clock Output
NC
YUV signal output (Digital ITU-R656 format)
10
3740
4144
4750
53
54
55
56
57
58
60
61
62
63
66
67
70
71
72
73
74
78
79
C0C7
INTLC
AVO
FSY/HC
MSY/HS
VS
FPDAT
CLK5
NC
XTAL1
XTAL2
VRT
I2CSEL
VOUT
CIN
VIN1
VIN2
VIN3
VREF
FB1IN
11
2.2.3PW113 General
The PW113 integrates an industry-leading scaler, an advanced OSD engine, a flexible input
port system, system memory, and a powerful 80186-based horizontal and vertical image scaler
swith intelligent Auto Image Optimization circuitryThe Image Processor supports NTSC or PAL
video data with a 4:3 aspect ratio and 16:9 aspect ratio sources, such as DVD or HDTV. Video
Input formats can be in either YUV4:4:4 (24 bit) or YUV4:2:2 (16 bit) input modesThe PW113
uses an integrated PLL to synchronize the display interface timing to the input timingAn
integrated OSD controller supports sophisticated bit-mapped based OSDs The OSD controller
supports transparent, translucent, and fade-in/ fade-out functions.
name
Function
VPort Pixel Clock input
VPort Vertical Sync input
VPort Horizontal Sync input
VGPort Field Input
VPort Pixel Enable
VGPort ITUR656 Pixel Data.I/O port
We use 47 MUTE mute control 48 PW1230E
PW1235output enable49 VGASEL VGA/YpbPr select
50 S1 sound system control51 DVIPD DVI interface
standby54 STANDBY power standby control56 RST1
peripheral IC reset
GPort Pixel Clock input
GPort Vertical Sync input
GPort Horizontal Sync/GPort Sync- on-Green input
GPort Pixel Enable input
GPort PLL Feedback / Line Advance Input
GPort Red Pixel Data input
GPort Green Pixel Data input
GPort Blue Pixel Data input
111118
DGB0DGB7
Display Port Pin Descriptions
106
DCLK
108
DVS
109
DHS
110
DEN
96103
DR0DR7
8895
DR0DR7
7683
DB0DB7
13
PW113
Block Diagram
14
2.2.4PW1235 General
PW1235 supports standard digital video signal incorporates deinterlacing
scaling .the PW1235 is able to effectively deinterlace video input by creating motion vectors that
follow frame-to-frame movement, and provide clear, progressive output in both analog and digital
formats. The PW1235 integrates input interfaceMEMORY control circuitpicture improve
output interface circuitI2C bus interface and so onall the function are controlled by I2C bus
Pin Function Descriptions
Pin(s)
Name
Video Port Pin Descriptions
27
PVVS
28
PVHS
25
PVCLK
26
CREF
12
SVVS
11
SVHS
13
SVCLK
30333538 VR0VR7
15182023 VG0VG7
1469
VB0VB7
Digital/Graphics (DG) Port Pins
68
DGCLK
67
DGVS
Function
Primary Video (PV) Port vertical sync input.
Port horizontal sync input
Port pixel clock input
Video input clock reference
Port (ITU-R BT656 format) vertical sync input
Port (ITU-R BT656 format) horizontal sync input
Port (ITU-R BT656 format) pixel clock input
Video port red data input
Video port green data input
Video port blue data input
Digital/Graphics (DG) port pixel clock
141142
121 122 DG0DG7
124 125
127130
110 111 DB0DB7
113 114
116119
Memory Pin Descriptions
229
MCLK
223
MCLKFB
225
MRAS
226
MCAS
227
MWE
213210207204 MA0
203206209211 MA13
214217215220
221218
255252248245 MD0
MD15
242239236232
231234238241
244247250254
Host Interface Pin Descriptions
47
2WDAT
45
2WCLK
43
2WA1
44
2WA2
178179181186 MCUD0
MCUD7
168170172 PORTB1
174176177
190
MCUCS
191
MCUWR
192
MCUCMD
188
MCURDY
Miscellaneous Pin Descriptions
56
TEST
144
TESTCLK
55
RESETn
40
XTALI
41
XTALO
146
CGMS
201
MVE
62, 63, 194,195
NC
System Power Pin Descriptions
5, 34, 93, 123,140, VDD
175,205, 235
19, 49, 77, 112,
VSS
134, 187, 219, 251
SDRAM clock
SDRAM clock feedback
SDRAM row address strobe
SDRAM column address strobe
SDRAM write enable
SDRAM address bus
SDA
SCL
Programmable two-wire serial bus address bit 1
Programmable two-wire serial bus address bit 2
MCU data bus
MCU address bus
Chip select
MCUR/W signal
MCU command signal
MCU Ready signal
Test mode
Used for testing, can be used to supply display clock
Hardware asynchronous reset.
Crystal oscillator input
Crystal oscillator output
CGMS Enable
Macrovision write protected enable
16
PVDD
PVSS
Ground.
MPAVDD
MPAVSS
MPDVDD
MPDVSS
DPAVDD
DPAVSS
DPDVDD
DPDVSS
AVD33R
AVD33G
AVD33B
AVS33R
AVS33G
AVS33B
ADAVDD
ADAVSS
ADDVDD
ADDVSS
ADGVDD
ADGVSS
17
18
2.2.5TA2024 general:
19
The TA2024 is a 10W/ch continuous average two-channel Class-T Digital Audio Power
Amplifier IC using Tripaths proprietary Digital Power Processing technology. Class-T
amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D
amplifiers.
Pin Function Descriptions
Pin(s)
2, 3
4, 9
5, 8, 17
6
7
Name
DCAP2, DCAP1
V5D, V5A
AGND1, AGND2, AGND3
REF
OVERLOADB
1014
11, 15
12
16
18
19
OAOUT1, OAOUT2
INV1, INV2
MUTE
BIASCAP
SLEEP
FAULT
20, 35
22
24, 27; 31, 28
25, 26, 29, 30
13, 21, 23, 32, 34
33
36
1
PGND2, PGND1
DGND
OUTP2 & OUTM2; OUTP1
& OUTM1
VDD2, VDD2 VDD1,
VDD1
NC
VDDA
CPUMP
5VGEN
20
Function
Charge pump switching pins
Digital 5VDC, Analog 5VDC
Analog Ground
Internal reference voltage
A logic low output indicates the input signal
has overloaded the amplifier
Input stage output pins.
Single-ended inputs
Mute control
Input stage bias voltage
Sleep mode control
A logic high output indicates thermal
overload
Power Grounds (high current)
Digital Ground
Bridged outputs
Supply pins for high current H-bridges,
nominally 12VDC.
Not connected
Analog 12VDC
Charge pump output
Regulated 5VDC source used to supply
power to the input section (pins 4 and 9).
2.2.6DS90CF383A General
The DS90C383A/DS90CF383A transmitter converts 28 bits of CMOS/TTL data into four
LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is
transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit
clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65
MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME,
DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock,
the data throughput is 227 Mbytes/
sec. The DS90C383A transmitter can be programmed for Rising edge strobe or Falling edge
strobe through a dedicated pin. The DS90CF383A is fixed as a Falling edge strobe transmitter.
21
Name
Function
VCC
Power supply
GND
Ground
DRE0DRE7
DGE0DGE7
DBE0DBE7
HSYNC
VSYNC
DE
TXCLK IN
PWRDWN
TXOUT+
TXOUTTXCLKOUT+
TXCLKOUT-
22
23
General
The Sil161B receiver uses Panel Link Digital technology to support high-resolution
displays up to UXGA. The Sil161B receiver supports up to true color panels (24 bit/pixel,
16.7M colors) in 1 or 2 pixels/clock mode. In addition, the receiver data output is time
staggered to reduce ground bounce that affects EMI. All Panel Link products are
designed on a scaleable CMOS architecture. This ensures support for future
performance requirements while maintaining the same logical interface. With this
scalable architecture, system designers can be assured that the interface will be fixed
through a number of technology and performance generations.
Name
RX0+
RX0RX1+
RX1RX2+
RX2RXC+
RXC-
4956
QO0QO7
Function
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input clock pair.
TMDS Low Voltage Differential Signal input clock pair.
8bit odd-pixel Blue output
5966
QO8QO15
6975,77
QO16QO23
1017
QE0QE7
2027
QE8QE15
3037
99
100
QE16QE23
RESERVED
OCK_INV
HS_DJTR
PD
ST
PIXS
STAG_OUT
24
SCDT
PDO
44
ODCK
46
47
48
18,29,43,57,78
19,28,45,58,76
6,38,67
5,39,68
82,84,88,95
99,83,87,89,92
97
98
96
DE
VSYNC
HSYNC
OVCC
OGND
CVCC
GND
DAVCC
AGND
PVCC
PGND
EXT-RES
25
26
3.1.1 .2
SOUND Disposal
the 9 pin of N901 outputs the second sound IF signal, enlarged by the Q910,following to
Q602 and passing C611 to the 67 pin of MSP3410G to carry on SIF demodulation and the
NICAM identify the decodingThe sound of PC, DVI, AV, YCbCr, and YPbPr are transited to
MSP3440, and then input to the speakers after transits to TA2024 and to the speakers.
.
3.1.1.3
In response to input signal of PW113 ,it must convert the input analog video signal, VGA
analog signal and DVI signal into digital or video decode outputinclude three partsone, VGA or
27
YpbPr (analog signal)is converted the signal into A/D by MST9885it is 24bit digital tricolor
signalsecond various video signalsinclude TV signal are disposalled by VPC3230 then
output the signal format ITU-R656 YUV signalThe third part decode DVI1.0 standard digital
signal then output 24bitRGB signal
3.1.1 .4
R, G, B signal From the VGA 1, 2, 3 pin through the static electricity protection
circuit switches with video signal from YpbPr input port in PI5V330. After then RGB
signal(PC source) pass C81C82C84 to 544843 pin of MST9885 and A/D converter in it
Moreover , Vertical , Horizontal sync from the VGA 13,14 pin also send to the
synchronous pulse orthopedics circuit after static electricity protect processing.
Horizontal sync after face lifting in 74LCX32 sends to the PI5V330 to the switch , and
then feedback to the 30 pins of MST9885, By the effect of Horizontal sync ,
MST9885 creates PLL lock providing the MST9885 work clock. Vertical sync after
buffer and enlarge in U71 outputs from the 6 pin of U71, and choices in U9(74
LVC126s).In VGA mode ,the signal to the 31 pin of MST9885, provides a Vertical
sync to the MST9885.
The PDP display is the exterior equipments, and need an identify signal to
examined by host when host communication. The 24LC21s of U8( EEPROM) saves
the hardware concerning display parameter.( install etc. such as the factory, model
number, resolution)
MST9885 under the control of PW113 bus, converts the R,G,B input 8 bit digital R,G,B
signal. 67 pin outputs pixel clock signal DATACKThe above signal sends to the PW113
and PW1235s at the same time, disposals the format judged by PW113.
3.1.1.4
9 pin of N901 outputs video signal passes VN901 and goes to 1 pin of TEA6425Dat the
same time 1 channel AV video signal sends to the 8 pin of TEA6425Dand other channel S-video
signal (YC signal) sends to 65 pin of TEA6425D respectively. The three signals switches in
the TEA6425D. VIDEO or Y signal outputs toVPC3230D from 17pinC signal outputs from
18pinat the same time 19 pin video outputs from19 pinVPC3230 The signal from TEA6425
after switch and A/Dsend to chroma decode circuit ,which can identify PAL/NTSC/SECAM
signal automatically and to each decode after identify. Such as NTSC video after identify the
system switches the TEA6425D channel sends to NTSC 3D comb filter from 14 pin of
TEA6425D. After digital 3D comb filter in uPD64083 YC signal sends back to 7371pin of
VPC3230Dto AD convertor and saturation control etc. The output digital YUV signalswitches
with digital YUV signal after A/D which inputs from 456pinand outputs digital YUV
signal sends to video disposalinclude zoomcontrast panorama modebrightnessgain control
28
tc. After then the signal transforms to from 3140pin digital YUV signal4:2:2(ITU-R656
format )and sends to PW1235 to DEINTERLACE etc
the video format outputs the digital R,G,B signal which fits PDP
display driver
PW113 the input video signal after disposalled by PW113outputs 852480 resolution digital
R,G,B signal which fits PDP panel spec and relevant syncclock signal and transform them into
LVDS by DS90CF383send to PDP panel to control the panel display correctly
29
S0
S1
Tuner demodulation
RF
MSP3410G
FmorNICAM demodulation
SIF
67
SRS(WOW)
27
CVBS
sound disposal
28
1
TEA6425 video switch
NTSC video
16
TA2024 sound
amplifier
MUTE
17
When NTSC,
Change the video switch by bus
Sync
88
separate
74
83
VPC3230
Identify color system
84
Not NTSC
Y
73
VPC3230 decode
71
SO
S1
D/K
1 0
BG
I
1 1
0 1
0 0
PW1235 I channel
SDRAM
BUFF
ER
PW1235E
PW113
SCALER
D
LVDSON
DS90C383
LVDS output
30
5PW1235Econtrol
High enable
BUFFER and polarity
controlled by Q3
6LVDSON control
3.2.2 AV
L
53
cvbs
MSP3410G
Sound switch
27
28
8
TEA6425
NTSC
16
video switch
17
Sync separate
88
uPD64083
NTSC
switch by bus
74
VPC3230
Identify color system
comb filter
83
MUTE
84
Not NTSC
Y
73
VPC3230
decode
71
Digital video and clock
SV
PW1235
SDRAM
I channel
BUFF
ER
PW1235E
PW113
SCALER
D
LVDSON
DS90C383
LVDS output
31
3.2.3 S-VIDEO
TEA6425 video
53
54
switch
17
18
74
72
MSP3410G
Sound switch
SRS(WOW)
sound disposal
27
28
VPC3230 decode
MUTE
Digital video and clock
SV
PW1235 I
channel
SDRAM
PW1235E
BUFF
ER
PW113
SCALER
D
LVDSON
DS90C383
LVDS output
32
3.2.4 YcbCr
L
MSP3410G
53 Sound switch SRS(WOW) sound disposal
54
27
CVBS
28
8
NTSC video
TEA6425 video
16
MUTE
switch
17
Sync.
separate
88
uPD64083 comb
VPC3230
fliter
83
signal
74
84
Not NTSC
Y
73
VPC3230 decode
71
Digital video and clock
SV
DS90C383
LVDSON
PW1235
SDRAM
channel
LVDS output
BUFF
ER
PW1235E
PW113
SCALER
disposal
LVDSON
DS90C383
LVDS output
33
3.2.5 YpbPr
VGASEL
Pb Pr
11
47
48
MSP3410G
Sound switch
PI330 switch
4
54 48
43
27
AD9883
MUTE
BUFF
ER
PW1235E
G
PW113
Format identify
PW113 SCALER
LVDSON
DS90C383
LVDS output
34
28
3.2.6 VGA
HS R
13 3
6 10
L
50
51
MSP3410G
VGASEL
PI330 switch
Sound switch
SRS(WOW) sound disposal
12 4
HS R
27
28
30 54 48 43
TA2024 sound amplifier
VS
U9
31
G
PW1235 P
SDRAM
MST9885
MUTE
BUFF
ER
channel
PW1235E
4VGASEL control
640X480800X600@60Hz signal
High enable
5PW1235E control
High enable
BUFF
G PW113 SCALER
BUFFER and polarity are controlled by Q3
ER
G
D
6LVDSON control
PW1235E
LVDSON
DS90C383
LVDS output
35
3.2.7 DVI
50
51
MSP3410G
SiL161
Sound switch
SRS(WOW) sound disposal
27
28
G
BUFF
ER
PW1235 P channel
SDRAM
PW1235E
MUTE
Not standard mode
Switch the channel
PW113
Format identify
Signal after vertical sync change
vertical sync 60HZ signal
BUFF
ER
PW113 SCALER
D
PW1235E
LVDSON
DS90C383
LVDS output
36
TA2024
sound amplifier
37
N803
LM1117-3.3
VUU
U19
U17
XP801
2 pin
5V-ST
N804
LM1117-1.8
24LC32
8pin
29LV800B
37pin
U16
PW113
16376584137185pin
VLL
VPP
U16 PW113
165167pin
NK605
remote head
XP101
11 pin
K board
connect
XPK3
11pin
VDK1
LED
U20
MAX202E
38
U5
PI5V330 16 pin
XP801
11 pin
D6V
N802
TA4805F
U27
LM1117-3.3
VCC
U26
LM1117-3.3
U6 AD9883A
262739424546
51525962 pin
VFF
VEE
U6 AD9883A
3435 pin
U3 PW1235
53493123140
175205235 pin
U28
LM1086CSX-2.5
VXX
VYY
39
U3 PW1235
197199 pin
VZZ
U3 PW1235
5860 pin
2.5
U3 PW1235
149163166
pin
U11 SiL161B
618293843576778
8284889597pin
to reduce interference
U11 power is divided into
VDDVIIVJJ by LC
filter
97 pin is VII power82
848895 pin are VJJ
power
U4 IS42S16400(A)-7T
13914274349pin
U3 PW1235
1429425464698090101109120131143165
180200208216224230237243249256pin
U3 PW1235
515457pin
XP801
8
9pin
U22 DC90C383
1926pin
VDD
VNN
U22 DC90CF383
34pin
VOO
U22 DC90CF383
44pin
U6 AD9883
11222369
7879pin
U71
74LV32
14pin
U1 VPC3230
10293645
52pin
40
VNNVOO is in order to
reduce the interference
from VDD after LC filter
3.4.2.4A6Vpower branch
XP805
1pin
A6V
N806
TA4805F
N601 MSP3410G
6566pin
VCC
N601 MSP3410G
111213pin
N805
TA4805F
N901 TDQ-6F7
311pin
5VTUNER
TV videoSIF
follow amplifer
circuit
N650
TA4805F
N702
LM1117-2.5
5V2
A2.5V
U701 uPD64083
538192
93pin
D2.5V
N701 uPD64083
3132454664
100pin
N703
LM1117-3.3
D3.3V
N701
uPD64083
38pin
N701 small
signal filter
amplifer circuit
5V-3D
41
3.4.2.5A12Vpower branch
XP805
3pin
N651
TA78M08
+8V
PC/YPbPr sound
amplifer
N902
TEA6425D
20pin
N601
MSP3410G
39pin
AVOUT sound
amplifer
42
Check K board
iack XK01 11 pin
5V power
yes
no
Check
resistance RK2
LBD VDK1
Check circuit
connect
yes
43
no
twoThe red led lightsbut doesnt turn to yellow after power on and black display
power oncheck
XP801 4 pin standby
is low0.5Vvoltage
check N803N804
output voltage
No
1check PW113
power impedance
2checkN803
N804
Yes
yes
check X3 14.318M
crystal
1check
connector
2check PDP
power
no
checkXP801 D6VVDD
yes
abnormality
I2Cbus
check PW113
RESET pin
voltage
check AM29LV800BT to
PW113 addressdata
control
normal
1check VPC3230PW1235
power circuit
2check VPC3230PW1235
reset voltage
3check VPC3230PW1235
peripherally circuit
change Y2
crystal
No
check
resetcircuit
Yes
Yes
check bus
circuit and PCB
wire
No
change
AM29LV800BT or
PW113 and wire
between them
44
threeThe red led lightbut turn to other color after power on and black display
change switch
find if there is
icon on the
screen
Yes
follow no
picture to check
Yes
mend
No
check mainboard
J15check the
line
No
check LVDS
signal
No
1LVDS ON is
hign or not
2check PW113
syncpixel
clockRGB data
sinal
Yes
Yes
check PW113
syncpixel
clockRGB data
sinal
checkDS90c383
power supply
Yes
Yes
check crystal
frequentcheck
PW113change
No
check PW113
output port
change PW113
No
check power
supply
check DS90C383
change
45
fourno picture
check if there
is a icon to
display when
source switches
No
other part is
following
no picture only
DVI
no picture only
VGA
check AD9883A
3031 pin sync
Yes
No
output abnormality
all abnormality
input abnormality
part abnormality
checkSiI161B/169
control signal
abnormality
change AD9883A
46
if there is one
state to display
when switch the
source
TVAVS-VDEO
YCbCr all no
picture
check PW1235
power clock
check VPC3230
output
repair abnormality
Yes
only TVAV
S-VIDE Ono
picture
only TVAV is
NTSC no picture
check AV board
connector
check TEA6425D14
pin video outout
joint well
Yes
check TEA6425D
I/O
check uPD64083
I/O filter and
amplifer circuit
check TDQ-6F7
powerbus and
video followwing
outout circuit
check uPD64083
resetclock
power
changeuPD64083
No
check VPC3230
power clock
periphery
circuitchange
VPC3230
check TEA6425
powerbus
change TEA6425
47
only TV no
picture
No
checka
nd
change
TEA642
5D
Yes
check TEA6425D1
pin video signal
input
colour
dissimilation
check liner
voltage circuit
source switch if
one mode is well
or not
checkDS90C383A
(37)-(42)(45)-(4
8)
all colour
dissimilation
check AD9883A
and 74LV16244
RGB digital
signal
check Sil161B
and 74LV16244
RGB digital
signal
check mainboard
panel jack
normal
normal
change U8
24LC21A
check56
pin
changeu7
24LC21Acheck
56
mosaic phenomena
check PW113
power
No
change PW113
No
change memorizer
U19 24LC32A
check PW113 and
U19
normal
normal DS90C383A
normal
check PW113
output video
siganl
48
change
DS90C383A
repair output
connector
follow
next
picture
picture
dissimilation
lack colourno
Rno G,no B
plane crossband
interference
lack front
one analog
signal
VGA state
AV/TV state
check C81C82
C84
check PW1235
output data
checkPI5V330
check VPC3230
output
check L901
L902L905
R904R909R910
check VPC3230
input signal
change AD9883A
No
only VGADVI
not commendatory
state
VGA mode
commendatory
state
DVI mode
commendatory
state
change U8
check5(6)
pin
change U7
check5(6)
pin
checkAD9883A and
peripherally
device
check SiI161B
and peripherally
device
49
check XP302
XP303sound box
connector
check XP302
XP303
outputsignal
Yes
check TA2024
input signal
normal
check TA2024
powermute
check MSP3410G
output signal
Yes
check MSP3410G
input signal
TV
other source
check sound
input
Yes
normal
check 67 pin
SISF input
Yes
normal
check MSP3410G
powerclock
resetbus
no input
normal
check signal
sourcesound
jackinput
coupling circuit
50
Annex 1
51
Annex 2
52
53