Professional Documents
Culture Documents
Lecture Slides
2015t1 (Winter)
Instructor: Rodolfo Pellizzoni
Notes by: Mark Aagaard
University of Waterloo
Dept of Electrical and Computer Engineering
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CONTENTS
Contents
1 Fundamentals of VHDL
1.1 Introduction to VHDL . . . . . . . . . . . . . . . . . . . . . . . .
1.1.1 Levels of Abstraction . . . . . . . . . . . . . . . . . . . . .
1.1.2 VHDL Origins and History . . . . . . . . . . . . . . . . . .
1.1.3 Semantics . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.4 Synthesis of a Simulation-Based Language . . . . . . . .
1.1.5 Solution to Synthesis Sanity . . . . . . . . . . . . . . . .
1.1.6 Standard Logic 1164 . . . . . . . . . . . . . . . . . . . . .
1.2 Comparison of VHDL to Other Hardware Description Languages
1.3 Overview of Syntax . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1 Syntactic Categories . . . . . . . . . . . . . . . . . . . . .
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3 Overview of FPGAs
3.1 Generic FPGA Hardware . . . . . . . . . .
3.1.1 Generic FPGA Cell . . . . . . . . .
3.1.2 Lookup Table . . . . . . . . . . . . .
3.1.3 Interconnect for Generic FPGA . . .
3.1.4 Blocks of Cells for Generic FPGA .
3.1.5 Special Circuitry in FPGAs . . . . .
3.2 Area Estimation for FPGAs . . . . . . . . .
3.2.1 Area for Circuit with one Target . . .
3.2.2 Algorithm to Allocate Gates to Cells
3.2.3 Area for Arithmetic Circuits . . . . .
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4.2.12 Reset . . . . . . . . . . . . . . . . . . . . . .
4.3 Dataflow Diagrams . . . . . . . . . . . . . . . . . . . .
4.3.1 Dataflow Diagrams Overview . . . . . . . . . .
4.3.2 Dataflow Diagram Execution . . . . . . . . . .
4.3.3 Dataflow Diagrams, Hardware, and Behaviour
4.3.4 Performance Estimation . . . . . . . . . . . . .
4.3.5 Area Estimation . . . . . . . . . . . . . . . . .
4.3.6 Design Analysis . . . . . . . . . . . . . . . . .
4.3.7 Parcels . . . . . . . . . . . . . . . . . . . . . .
4.3.8 Bubbles and Throughput . . . . . . . . . . . .
4.4 Hnatyshyn with Registered Outputs . . . . . . . . . .
4.4.1 Leftovers . . . . . . . . . . . . . . . . . . . . .
4.4.2 Design Process . . . . . . . . . . . . . . . . .
4.4.3 Requirements . . . . . . . . . . . . . . . . . .
4.4.4 Data-Dependency Graph . . . . . . . . . . . .
4.4.5 Initial Dataflow Diagram . . . . . . . . . . . . .
4.4.6 Area Optimization . . . . . . . . . . . . . . . .
4.4.7 Assign Names to Registered Signals . . . . . .
4.4.8 VHDL #1: Big and Obviously Correct . . . . .
4.4.9 Allocation . . . . . . . . . . . . . . . . . . . . .
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4.7.8 Allocation . . . . . . . . . . . . . .
4.7.9 VHDL #2: Post-Allocation . . . . .
4.7.10 Separate Datapath and Control .
4.8 Design Example: Hnatyshyn with Bubbles
4.8.1 Control Table Standard Method
4.8.2 Control Table Valid Bit Shortcut
4.9 Example: LeBlanc . . . . . . . . . . . . .
4.9.1 System Description . . . . . . . .
4.9.2 Design for ASAP Parcels . . . . .
4.9.2.1 Implicit State Machine . .
4.9.2.2 Explicit State Machine . .
4.9.2.3 Datapath Control . . . .
4.9.2.4 Final Implementation . .
4.9.2.5 Buggy Implementation .
4.9.3 Design for Unpredictable Bubbles
4.9.3.1 Implicit State Machine . .
4.9.3.2 Explicit State Machine . .
4.9.3.3 Datapath Control . . . .
4.9.3.4 Final Implementation . .
4.9.3.5 Buggy Implementation .
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CONTENTS
CONTENTS
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493
494
495
500
502
503
507
515
516
521
521
521
522
523
523
524
526
527
528
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529
530
531
534
537
537
545
546
546
547
551
556
xvii
xviii
CONTENTS
CONTENTS
8 Timing Analysis
8.1 Delays and Definitions . . . . . . . . . . . . . . . . . . .
8.1.1 Background Definitions . . . . . . . . . . . . . .
8.1.2 Clock-Related Timing Definitions . . . . . . . . .
8.1.2.1 Clock Latency . . . . . . . . . . . . . .
8.1.2.2 Clock Skew . . . . . . . . . . . . . . . .
8.1.2.3 Clock Jitter . . . . . . . . . . . . . . . .
8.1.3 Storage-Related Timing Definitions . . . . . . .
8.1.3.1 Flops and Latches . . . . . . . . . . . .
8.1.4 Propagation Delays . . . . . . . . . . . . . . . .
8.1.5 Timing Constraints . . . . . . . . . . . . . . . . .
8.1.6 Review: Timing Parameters . . . . . . . . . . . .
8.2 Timing Analysis of Simple Latches . . . . . . . . . . . .
8.2.1 Structure and Behaviour of Multiplexer Latch . .
8.2.2 Strategy for Timing Analysis of Storage Devices
8.2.3 Clock-to-Q Time of a Latch . . . . . . . . . . . .
8.2.4 From Load Mode to Store Mode . . . . . . . . .
8.2.5 Setup Time Analysis . . . . . . . . . . . . . . . .
8.2.6 Hold Time of a Multiplexer Latch . . . . . . . . .
8.2.7 Example of a Bad Latch . . . . . . . . . . . . . .
8.2.8 Summary . . . . . . . . . . . . . . . . . . . . .
8.3 Advanced Timing Analysis of Storage Elements . . .
8.4 Critical Path . . . . . . . . . . . . . . . . . . . . . . . .
8.4.1 Introduction to Critical and False Paths . . . .
8.4.1.1 Example of Critical Path in Full Adder
8.4.1.2 Longest Path and Critical Path . . . .
8.4.1.3 Criteria for Critical Path Algorithms . .
8.4.2 Longest Path . . . . . . . . . . . . . . . . . . .
8.4.2.1 Algorithm to Find Longest Path . . . .
8.4.2.2 Longest Path Example . . . . . . . .
8.4.3 Monotone Speedup . . . . . . . . . . . . . . .
8.5 False Paths . . . . . . . . . . . . . . . . . . . . . . . .
8.6 Analog Timing Model . . . . . . . . . . . . . . . . . .
8.6.1 Defining Delay . . . . . . . . . . . . . . . . . .
8.6.2 Modeling Circuits for Timing . . . . . . . . . . .
8.6.3 Example: Two Buffers . . . . . . . . . . . . . .
8.6.4 Ex: Two Bufs with Both Caps . . . . . . . . . .
8.7 Elmore Delay Model . . . . . . . . . . . . . . . . . . .
8.7.1 Elmore Delay as an Approximation . . . . . . .
8.7.2 A More Complicated Example . . . . . . . . .
8.8 Practical Usage of Timing Analysis . . . . . . . . . . .
xix
CONTENTS
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563
564
564
565
565
567
569
571
571
574
575
577
578
578
581
582
583
584
590
593
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596
597
598
600
601
603
606
607
607
608
609
613
614
615
619
623
628
632
632
635
639
xx
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641
642
642
643
644
644
645
646
649
651
653
654
655
655
655
660
666
666
670
670
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671
673
680
681
682
683
684
688
690
690
692
694
696
702
703
703
704
CONTENTS
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xxi
xxii
CONTENTS
10 Review
10.1 Overview of the Term . . . . . . . . . . .
10.2 VHDL . . . . . . . . . . . . . . . . . . .
10.2.1 VHDL Topics . . . . . . . . . . .
10.2.2 VHDL Example Problems . . . .
10.3 RTL Design Techniques . . . . . . . . .
10.3.1 Design Topics . . . . . . . . . . .
10.3.2 Design Example Problems . . . .
10.4 Performance Analysis and Optimization
10.4.1 Performance Topics . . . . . . .
10.4.2 Performance Example Problems
10.5 Timing Analysis . . . . . . . . . . . . . .
10.5.1 Timing Topics . . . . . . . . . . .
10.5.2 Timing Example Problems . . . .
10.6 Power . . . . . . . . . . . . . . . . . . .
10.6.1 Power Topics . . . . . . . . . . .
10.6.2 Power Example Problems . . . .
10.7 Formulas to be Given on Final Exam . .
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705
706
707
707
708
709
709
710
711
711
712
713
713
714
715
715
716
717
1.1
1.1.1
24
Introduction to VHDL
Levels of Abstraction
Transistor Signal values and time are continous (analog). Each transistor is
modeled by a resistor-capacitor network.
Switch Time is continuous, but voltage may be either continuous or discrete.
Linear equations are used.
Gate Transistors are grouped together into gates. Voltages are discrete values
such as 0 and 1.
Register transfer level Hardware is modeled as assignments to registers and
combinational signals. Basic unit of time is one clock cycle.
Transaction level A transaction is an operation such as transfering data across
a bus. Building blocks are processors, controllers, etc. VHDL, SystemC, or
SystemVerilog.
Electronic-system level Looks at an entire electronic system, with both
hardware and software.
1.1.2
Chapter 1
Fundamentals of VHDL
1.1.2
25
26
1.1.3
1.1.4
Semantics
28
The original goal of VHDL was to simulate circuits. The semantics of the language
define circuit behaviour.
a
c <= a AND b;
simulation
b
c
But now, VHDL is used in simulation and synthesis. Synthesis is concerned with
the structure of the circuit.
Synthesis: converts one type of description (behavioural) into another, lower level,
description (usually a netlist).
a
synthesis
c <= a AND b;
c
b
Synthesis vs Simulation
1.1.5
The VHDL semantics define the behaviour of the hardware that is generated, not
the structure of the hardware.
ula
tio
sim
same
behaviour
synthesis
c
b
simulation
b
c
syn
the
sis
different
structure
a
c <= a AND b;
Be careful if you have to port VHDL code from one tool to another
same
behaviour
a
a
c
b
simulation
b
c
27
1.1.5
29
30
1.1.6
uninitialized
strong unknown
strong 0
strong 1
high impedance
weak unknown
weak 0
weak 1
dont care
1.3.3
1.3.3
32
entity
architecture
Entity
1.3
1.3.1
Overview of Syntax
Syntactic Categories
This section reserved for your reading pleasure
1.3.2
library ieee;
use ieee.std_logic_1164.all;
entity and_or is
port (
a, b, c : in std_logic ;
z
: out std_logic
);
end entity;
Example of an entity
Library Units
This section reserved for your reading pleasure
31
1.3.3
33
34
Architecture
architecture main of and_or is
signal x : std_logic;
begin
x <= a AND b;
z <= x OR (a AND c);
end architecture;
Example of architecture
1.3.4
Concurrent Statements
36
Concurrent Statements
architecture main of bowser is
begin
x1 <= a AND b;
x2 <= NOT x1;
z <= NOT x2;
end main;
x1
x2
1.3.4
Concurrent Statements
35
Concurrent Statements
37
38
1.3.6
Processes
39
1.3.6
Processes
40
1.3.6
Processes
41
42
Sensitivity List
1.3.8
44
The sensitivity list contains the signals that are read in the process.
1.3.7
Sequential Statements
loop
while loop
for loop
next
wait until . . . ;
. . . <= . . . ;
if . . . then . . . elsif . . . end if;
case . . . is
when . . . | . . . => . . . ;
when . . . => . . . ;
end case;
loop . . . end loop;
while . . . loop . . . end loop;
for . . . in . . . loop . . . end loop;
next . . . ;
1.4
All concurrent assignments can be translated into sequential statements. But, not
all sequential statements can be translated into concurrent statements.
1.4.1
43
1.4.1
45
46
1.4.4
1.4.4
Coding Style
48
Coding Style
Code thats easy to write with sequential statements, but difficult with concurrent:
The two code fragments below have identical behaviour:
Concurrent Statements
t <=
<val1> when <cond>
else <val2>;
Sequential Statements
if <cond> then
t <= <val1>;
else
t <= <val2>;
end if
47
Sequential Statements
case <expr> is
when <choices1> =>
t <= <val1>;
when <choices2> =>
t <= <val2>;
when <choices3> =>
t <= <val3>;
end case;
case <expr> is
when <choice1> =>
if <cond> then
o <= <expr1>;
else
o <= <expr2>;
end if;
when <choice2> =>
...
end case;
1.5
Overview of Processes
Processes are the most difficult VHDL construct to understand. This section gives
an overview of processes. section 1.6 gives the details of the semantics of
processes.
49
50
Process Semantics
Process Semantics
52
Process Semantics
execution sequence
execution sequence
architecture
procA: process
stmtA1;
stmtA2;
stmtA3;
A1
A1
A2
A3
Combinational process:
A1
A2
A2
A3
A3
end process;
procB: process
stmtB1;
stmtB2;
end process;
B1
B1
B2
single threaded:
procA before
procB
51
B1
B2
single threaded:
procB before
procA
multithreaded:
procA and procB
in parallel
1.5.1
53
54
Clocked process:
1.5.1
56
process
begin
wait until rising_edge(clk);
b <= a;
end process;
Note:
Clocked processes are sometimes called sequential
processes, but this can be easily confused with sequential
statements, so in E&CE 327 well refer to synthesizable
processes as either combinational or clocked.
55
1.5.1
57
58
1.5.2
1.5.2
Latch Inference
60
Latch Inference
process (clk)
begin
a <= clk;
end process;
process (a, b, c)
begin
if (a = 1) then
z1 <= b;
z2 <= b;
else
z1 <= c;
end if;
end process;
a
b
c
z1
z2
Latch Inference
When a signals value must be stored, VHDL infers a latch or a flip-flop in the
hardware to store the value.
If you want a latch or a flip-flop for the signal, then latch inference is good.
If you want combinational circuitry, then latch inference is bad.
59
1.5.2
Latch Inference
61
62
z
a
Combinational loop
Question:
EN
Latch
Flip-flop
Simple Simulation
d
e
c
d
e
10ns 12ns
15ns
64
1.6.2
process (a,b,c,d)
begin
c <= a and b;
d <= not c;
e <= b and d;
end process;
process (a,b)
begin
c <= a and b;
end process;
process (c)
begin
d <= not c;
end process;
process (b,d)
begin
e <= b and d;
end process;
1.6.3
1.6.3
Zero-Delay Simulation
66
Zero-Delay Simulation
register-transfer-level
67
68
1.6.4
1.6.4.4
70
1ns
1. Simulate a gate if any of its inputs changed. (If no input changed, then the
current value of the output is correct and the output can stay at the same value.)
3. When a gate is executed, the projected (i.e., new) value of the output remains
invisible until the beginning of the next delta cycle.
4. Increment time when there is no need for another delta cycle (no gate had an
input change value in the current delta cycle).
Delta-cycle simulation
with projected values
Simple
simulation
1ns
Delta-cycle simulation
1ns
2ns
-cycle
a
b
c
1.6.4.5
2ns
10ns
11ns
b
c
9ns
clk
Simple simulation
1ns
b
a
a
c
clk
69
1.6.4
71
1.6.4.6
1ns
-cycle
-cycle
Final value
a
b
73
1.6.4
75
a
b
1ns
-cycle
-cycle
The choice of in which order to simulate the gates must not affect the result.
a
1ns
-cycle
-cycle
a
1
b
0
c
0
d
0
Execution order: b, c, d
1.6.5
Execution order: b, d, c
a
b
Final value
Final value
-cycle
-cycle
1ns
-cycle
-cycle
a
1
b
0
c
1
d
1
Execution order: b, c, d
74
Final value
1ns
Final value
Execution order: b, d, c
1.6.5
76
77
1.6.5.2
Time
Sim rounds
Sim cycles
proc_a
proc_b
proc_c
a
0ns
a
values
old new
graphical
symbol
text
U 0
U U
0 1
79
1.6.5
( initialization )
set all signals to default value;
add to resume set all processes;
set time to 0 ns;
( simulation loop )
while time <
{
Definition simulation cycle: The operations that occur in one iteration of the
simulation algorithm.
Definition delta cycle: A simulation cycle that does not advance simulation
time.
Definition simulation round: A sequence of simulation cycles that all have the
same simulation time.
80
81
1.6.5.4
proc_a : process
begin
a <= 0;
wait for 9 ns;
a <= 1;
wait;
end process;
Time
Sim rounds
Sim cycles
proc_a
proc_clk
proc_flops
a
clk
0ns
proc_clk : process
begin
clk <= 0;
wait for 10 ns;
clk <= 1;
wait for 10 ns;
end process;
proc_flops : process
begin
wait until re(clk);
b <= a;
c <= b;
end process;
re=rising edge
Time
Sim rounds
Sim cycles
proc_a
proc_clk
proc_flops1
proc_flops2
10ns
R E
S
R E
clk
b1
U
U
c1
U
U
b2
U
U
c2
U
84
a
b
a
b
Time
Sim rounds
Sim cycles
proc_a
proc_b
proc_c
proc_d
a
0ns
86
1.6.6
1.6.6
The VHDL Language Reference Manual gives only a textual description of the
VHDL semantics. The conventions for drawing the waveforms are just our own.
old value
new value
U 0 1
88
1.7
Register-Transfer-Level Simulation
U
0
1
1.7.1
Overview
In the first simulation step of the first simulation cycle of a simulation round (i.e.,
the first simulation step of a simulation round), at least one process will resume.
This is contrast to the first simulation step of all other simulation cycle, where
current values of signals are updated with projected values.
87
89
90
process begin
a <= 0;
wait for 10 ns;
a <= 1;
...
end process;
1.7.3
1.7.3
92
1.7.3.1
We revisit an earlier example from delta-cycle simulation, but change the code
slightly and do register-transfer-level simulation.
process begin
b <= 0;
wait for 10 ns;
b <= a;
...
end process;
Decomposed
Sorted
(b) Run clocked processes in any order, reading new values of timed signals
and old values of registered signals.
(c) Run combinational processes in topological order, reading new values of
signals.
91
1.7.3
93
94
Waveforms
0ns
a
1ns
2ns
3ns
102ns
huey: process
begin
clk <= 0;
wait for 10 ns;
clk <= 1;
wait for 10 ns;
end process;
dewey: process
begin
a <= to_unsigned(0,4);
wait until re(clk);
while (a < 4) loop
a <= a + 1;
wait until re(clk);
end loop;
end process;
clk
a
d
louie: process
begin
d <= 1;
wait until re(clk);
if (a >= 2) then
d <= 0;
wait until re(clk);
end if;
end process;
96
1.8
1.10
1.9
Variables in VHDL
This is an advanced section.
It is not covered in the course
and will not be tested.
98
1.11
1.11.1
Conditional
Arithmetic
Storage
97
99
100
1.11.1
OR
gate
and gate
xor
exclusive-or gate
adder
subtracter
not inverter
nand NAND gate
nor
102
clocked process
CE
flip flop
S
WE
A
DO
DI
WE
A0
DO0
DI0
A1
101
DO1
1.11.1
103
104
1.11.2
Some of the common gates you have encountered in previous courses should be
avoided when synthesizing register-transfer-level hardware, particularly if FPGAs
are the implementation technology.
Latches : Use flops, not latches
T, JK, SR, etc flip-flops : Limit yourself to D-type flip-flops
Tri-State Buffers : Use multiplexers, not tri-state buffers
Note:
Unfortunately and surprisingly, PalmChip has been
awarded a US patent for using uni-directional busses (i.e.
multiplexers) for system-on-chip designs. The patent was filed in
2000, so all fourth-year design projects completed after that date
will need to pay royalties to PalmChip
What is This?
process (a)
begin
if rising_edge(a) then
c <= b;
end if;
end process;
105
1.11.3
1.11.3
1.11.3.1
106
process (clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end process;
1.11.3
107
108
1.11.3.2
1.11.3
110
process (clk)
begin
if rising_edge(clk) then
if (reset = 1) then
q <= 0;
else
q <= d;
end if;
end if;
end process;
Question:
What is this?
109
1.11.3
111
112
1.11.3
Behavioural Comparison
sel
d0
d0
D
114
q0
sel
sel
d0
d1
clk
d1
d1
clk
q1
clk
Question: For the two circuits above, does q have the same behaviour in
both circuits?
Mux on output
Mux on input
q0
clk
d1
sel
d0
d0
d1
d1
q1
clk
113
clk
sel
sel
q
D
clk
1.11.3
115
116
1.12.1
1.12.1
Initial Values
118
Initial Values
1.11.4
Reason: At powerup, the values on signals are random (except for some FPGAs).
1.12.2
Wait For
Reason: Delays through circuits are dependent upon both the circuit and its
operating environment, particularly supply voltage and temperature. For example,
imagine trying to build an AND gate that will have exactly a 2ns delay in all
environments.
1.12.2
Wait For
119
120
1.12.3
Variables
process
variable bad : std_logic;
begin
wait until rising_edge(clk);
bad := not a;
d <= bad and b;
e <= bad or c;
end process;
Use signals, do not use variables
reason The intention of the creators of VHDL was for signals to be wires and
variables to be just for simulation. Some synthesis tools allow some uses of
variables, but when using variables, it is easy to create a design that works in
simulation but not in real hardware.
1.12.4
1.12.5
1.12.5
122
If a synthesizable clocked process has a wait statement, then the process must
begin with a wait statement.
process
process
c <= a;
wait until rising edge(clk);
wait until rising edge(clk);
d <= b;
wait until rising edge(clk);
d <= b;
c <= a;
wait until rising edge(clk);
end process;
end process;
Unsynthesizable
Synthesizable
Reason: In simulation, any assignments before the first wait statement will be
executed in the first delta-cycle. In the synthesized circuit, the signals will be
outputs of flip-flops and will first be assigned values after the first rising-edge.
1.12.6
121
1.12.6
123
124
1.12.8
126
1.12.7
1.12.9
process (clk)
begin
if rising_edge(clk) then
q0 <= d0;
end if;
if rising_edge(clk) then
q1 <= d1;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
q0 <= d0;
else
q0 <= d1;
end if;
end process;
Reason: The idioms for synthesis tools generally expect just a single if
rising edge statement in each process.
Reason: The idioms for the synthesis tools expect a signal to be either registered
or combinational, not both.
The simpler the VHDL code is, the easier it is to synthesize hardware.
Programmers of synthesis tools make idiomatic (idiotic?) restrictions to make their
jobs simpler.
125
1.12.9
127
128
1.12.10
Paths
loops where some paths are clocked and some are not (UNSYNTHESIZABLE)
process begin
while c /= 1 loop
if b = 1 then
wait until rising_edge(clk);
e <= d;
else
e <= not d;
end if;
end loop;
e <= b;
end process;
Reason: if the loop condition is true and the if-then-else condition is false, then
the combinational path is taken and the process will get stuck in an infinite loop
going through the combinational path.
1.12.11
1.12.11
130
1.13
latches
process
begin
for i in 0 to 7 loop
wait until rising_edge(clk);
x <= to_unsigned(i,4);
end loop;
end process;
asynchronous resets
combinational loops
using a data signal as a clock
using a clock signal as data
tri-state buffers and signals
multiple drivers for a signal
Reason: Idiom of synthesis tools; while-loops with the same behaviour are
synthesizable.
129
131
132
1.13.1
The most important guideline is: know what you want the synthesis tool to build for
you.
1.13.2
Latches
134
1.13.2
Latches
133
1.13.3
Asynchronous Reset
In an asynchronous reset, the test for reset occurs outside of the test for the clock
edge.
process (reset, clk)
begin
if (reset = 1) then
q <= 0;
elsif rising_edge(clk) then
q <= d;
end if;
end process;
All reset signals should be synchronous.
reason If a reset occurs very close to a clock edge, some parts of the circuit
might be reset in one clock cycle and some in the subsequent clock cycle.
This can lead the circuit to be out of sync as it goes through the reset
sequence, potentially causing erroneous internal state and output values.
1.13.3
Asynchronous Reset
135
136
1.13.4
Combinational Loops
1.13.6
1.13.6
138
process begin
wait until rising_edge(clk);
count <= count + 1;
end process;
b <= a and clk;
Clock signals should be used only as clocks.
reason Clock signals have two defined values in a clock cycle and transition in
the middle of the clock cycle. At the register-transfer level, each signal has
exactly one value in a clock cycle and signals transition between values only
at the boundary between clock cycles.
1.13.5
process begin
wait until rising_edge(clk);
count <= count + 1;
end process;
process begin
waiting until rising_edge( count(5) );
b <= a;
end process;
Data signals should be used only as data.
reason All data assignments should be synchronized to a clock. This ensures
that the timing analysis tool can determine the maximum clock speed
accurately. Using a data signal as a clock clock signals can lead to
unpredictable delays between different assignments, which makes it
infeasible to do an accurate timing analysis.
137
1.13.7
139
140
1.13.8
Multiple Drivers
process begin
wait until rising edge(clk);
if reset = 1 then
y <= 0;
z <= 0;
end if;
end process;
process begin
wait until rising edge(clk);
if reset = 0 then
if a = 1 then
z <= b and c;
else
z <= d;
end if;
end if;
end process;
process begin
wait until rising edge(clk);
if reset = 0 then
if b = 1 then
y <= c;
end if;
end if;
end process;
Each signal should be assigned to in only one process. This is often called the
single assignment rule.
reason Multiple processes driving the same signal is the same as having
multiple gates driving the same wire. This can cause contention, tri-state
values, and other bad things.
141