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Digital systems are said to be constructed by using logic gates. These gates are the
AND, OR, NOT, NAND, NOR, EXOR and EXNOR gates. The basic operations are
described below with the aid of truth tables.
AND gate
The AND gate is an electronic circuit that gives a high output (1) only
if all its inputs are high. A dot (.) is used to show the AND operation i.e.
A.B. Bear in mind that this dot is sometimes omitted i.e. AB
OR gate
The OR gate is an electronic circuit that gives a high output (1) if one or
more of its inputs are high. A plus (+) is used to show the OR operation.
NOT gate
The NOT gate is an electronic circuit that produces an inverted version of the
input at its output. It is also known as an inverter. If the input variable is A,
the inverted output is known as NOT A. This is also shown as A', or A with a
bar over the top, as shown at the outputs. The diagrams below show two ways
that the NAND logic gate can be configured to produce a NOT gate. It can also
be done using NOR logic gates in the same way.
NAND gate
This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate.
The outputs of all NAND gates are high if any of the inputs are low. The symbol is an
AND gate with a small circle on the output. The small circle represents inversion.
NOR gate
This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The
outputs of all NOR gates are low if any of the inputs are high.
The symbol is an OR gate with a small circle on the output. The small circle
represents inversion.
EXOR gate
The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not
both, of its two inputs are high. An encircled plus sign ( ) is used to show the EOR
operation.
EXNOR gate
The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a
low output if either, but not both, of its two inputs are high. The symbol is an EXOR
gate with a small circle on the output. The small circle represents inversion.
The NAND and NOR gates are called universal functions since with either one the
AND and OR functions and NOT can be generated.
Table 1: Logic gate symbols
Table 2 is a summary truth table of the input/output combinations for the NOT gate
together with all possible input/output combinations for the other gate functions.
Table 2: Logic gates representation using the Truth table
The result is that combinational logic circuits have no feedback, and any changes to the signals being
applied to their inputs will immediately have an effect at the output. In other words, in a Combinational
Logic Circuit, the output is dependant at all times on the combination of its inputs. So if one of its inputs
condition changes state, from 0-1 or 1-0, so too will the resulting output as by default combinational logic
circuits have no memory, timing or feedback loops within their design.
Combinational Logic
Combinational Logic Circuits are made up from basic logic NAND, NOR or NOT gates that are
combined or connected together to produce more complicated switching circuits. These logic gates are
the building blocks of Combinational Logic Circuits. An example of a combinational circuit is a decoder,
which converts the binary code data present at its input into a number of different output lines, one at a
time producing an equivalent decimal code at its output.
Combinational logic circuits can be very simple or very complicated and any combinational circuit can be
implemented with only NAND and NOR gates as these are classed as universal gates.
The three main ways of specifying the function of a combinational logic circuit are:
1. Boolean Algebra This forms the algebraic expression showing the operation of the logic
circuit for each input variable either True or False that results in a logic 1 output.
2. Truth Table A truth table defines the function of a logic gate by providing a concise list
that shows all the output states in tabular form for each possible combination of input variable that
the gate could encounter.
3. Logic Diagram This is a graphical representation of a logic circuit that shows the wiring
and connections of each individual logic gate, represented by a specific graphical symbol, that
implements the logic circuit.
and all three of these logic circuit representations are shown below.
As combinational logic circuits are made up from individual logic gates only, they can also be considered
as decision making circuits and combinational logic is about combining logic gates together to process
two or more signals in order to produce at least one output signal according to the logical function of each
logic gate. Common combinational circuits made up from individual logic gates that carry out a desired
application include Multiplexers, De-multiplexers, Encoders,Decoders, Full and Half Adders etc.
One of the most common uses of combinational logic is in Multiplexer and De-multiplexer type circuits.
Here, multiple inputs or outputs are connected to a common signal line and logic gates are used to
decode an address to select a single data input or output switch.
A multiplexer consist of two separate components, a logic decoder and some solid state switches, but
before we can discuss multiplexers, decoders and de-multiplexers in more detail we first need to
understand how these devices use these solid state switches in their design.
Analogue Switches Used in Data Switching and Communications, Video and Audio Signal
Switching, Instrumentation and Process Control Circuits etc.
Digital Switches High Speed Data Transmission, Switching and Signal Routing, Ethernet,
LANs, USB and Serial Transmissions etc.
Power Switches Power Supplies and General Standby Power Switching Applications,
Switching of Larger Voltages and Currents etc.
By connecting an N-channel MOSFET in parallel with a P-channel MOSFET allows signals to pass in
either direction making it a Bi-directional switch and as to whether the N-channel or the P-channel
device carries more signal current will depend upon the ratio between the input to the output voltage. The
two MOSFETs are switched ON or OFF by two internal non-inverting and inverting amplifiers.
Contact Types
Just like mechanical switches, analogue switches come in a variety of forms or contact types, depending
on the number of poles and throws they offer. Thus, terms such as SPST (single-pole single throw)
and SPDT (single-pole double-throw) also apply to solid state analogue switches with make-beforebreak and break-before-make configurations available.
Individual analogue switches can be grouped together into standard IC packages to form devices with
multiple switching configurations of SPST (single-pole single-throw) and SPDT (single-pole double-throw)
as well as multi channel multiplexers. The most common and simplest analogue switch in a single IC
package is the 74HC4066 which has 4 independent bi-directional ON/OFF Switches within a single
package but the most widely used variants of the CMOS analogue switch are those described as Multiway Bilateral Switches otherwise known as the Multiplexer and De-multiplexer ICs and these are
discussed in the next tutorial.
The Multiplexer
The Multiplexer (MUX)
Multiplexing is the generic term used to describe the operation of sending one or more analogue or digital
signals over a common transmission line at different times or speeds and as such, the device we use to do just
that is called a Multiplexer.
The rotary switch, also called a wafer switch as each layer of the switch is known as a wafer, is a
mechanical device whose input is selected by rotating a shaft. In other words, the rotary switch is
a manual switch that you can use to select individual data or signal lines simply by turning its
inputs ON or OFF. So how can we select each data input automatically using a digital
device.
In digital electronics, multiplexers are also known as data selectors because they can select
each input line, are constructed from individual Analogue Switches encased in a single IC
package as opposed to the mechanical type selectors such as normal conventional switches and
relays.
They are used as one method of reducing the number of logic gates required in a circuit design or
when a single data line or data bus is required to carry two or more different digital signals. For
example, a single 8-channel multiplexer.
Generally, the selection of each input line in a multiplexer is controlled by an additional set of
inputs called control lines and according to the binary condition of these control inputs, either
HIGH or LOW the appropriate data input is connected directly to the output. Normally, a
multiplexer has an even number of 2 data input lines and a number of control inputs that
correspond with the number of data inputs.
N
The Demultiplexer
The Demultiplexer
The data distributor, known more commonly as a Demultiplexer or Demux for short, is the exact opposite
of the Multiplexer we saw in the previous tutorial. The demultiplexer takes one single input data line and then
switches it to any one of a number of individual output lines one at a time. The demultiplexer converts a serial
data signal at the input to a parallel data at its output lines as shown below.
Output Select
Data Output
Selected
The Boolean expression for this 1-to-4 Demultiplexer above with outputs A to D and data select
lines a, b is given as:
F = abA + abB + abC + abD
The function of the Demultiplexer is to switch one common data input line to any one of the 4
output data lines A to D in our example above. As with the multiplexer the individual solid state
switches are selected by the binary input address code on the output select pins a and b as
shown.
Combinational circuit is circuit in which we combine the different gates in the circuit for example encoder, decoder,
multiplexer and demultiplexer. Some of the characteristics of combinational circuits are following.
The output of combinational circuit at any instant of time, depends only on the levels present at input
terminals.
The combinational circuit do not use any memory. The previous state of input does not have any effect on
the present state of the circuit.
BLOCK DIAGRAM
Half Adder
Half adder is a combinational logic circuit with two input and two output. The half adder circuit is designed to add two
single bit binary number A and B. It is the basic building block for addition of twosingle bit numbers. This circuit has
two outputs carry and sum.
BLOCK DIAGRAM
TRUTH TABLE
CIRCUIT DIAGRAM
Full Adder
Full adder is developed to overcome the drawback of Half Adder circuit. It can add two one-bit numbers A and B, and
carry c. The full adder is a three input and two output combinational circuit.
BLOCK DIAGRAM
TRUTH TABLE
CIRCUIT DIAGRAM
In the block diagram, A0 and B0 represent the LSB of the four bit words A and B. Hence Full Adder-0 is the lowest
stage. Hence its Cin has been permanently made 0. The rest of the connections are exactly same as those of n-bit
parallel adder is shown in fig. The four bit parallel adder is a very common logic circuit.
BLOCK DIAGRAM
Half Subtractors
Half subtractor is a combination circuit with two inputs and two outputs (difference and borrow). It produces the
difference between the two binary bits at the input and also produces a output (Borrow) to indicate if a 1 has been
borrowed. In the subtraction (A-B), A is called as Minuend bit and B is called as Subtrahend bit.
TRUTH TABLE
CIRCUIT DIAGRAM
Full Subtractors
The disadvantage of a half subtractor is overcome by full subtractor. The full subtractor is a combinational circuit with
three inputs A,B,C and two output D and C'. A is the minuend, B is subtrahend, C is the borrow produced by the
previous stage, D is the difference output and C' is the borrow output.
TRUTH TABLE
CIRCUIT DIAGRAM
Multiplexers
Multiplexer is a special type of combinational circuit. There are n-data inputs, one output and m select inputs with 2m
= n. It is a digital circuit which selects one of the n data inputs and routes it to the output. The selection of one of the n
inputs is done by the selected inputs. Depending on the digital code applied at the selected inputs, one out of n data
sources is selected and transmitted to the single output Y. E is called the strobe or enable input which is useful for the
cascading. It is generally an active low terminal, that means it will perform the required operation when it is low.
BLOCK DIAGRAM
2 : 1 multiplexer
4 : 1 multiplexer
16 : 1 multiplexer
32 : 1 multiplexer
BLOCK DIAGRAM
TRUTH TABLE
Demultiplexers
A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input and distributes it over several
outputs. It has only one input, n outputs, m select input. At a time only one output line is selected by the select lines
and the input is transmitted to the selected output line. A de-multiplexer is equivalent to a single pole multiple way
switch as shown in fig.
Demultiplexers come in multiple variations
1 : 2 demultiplexer
1 : 4 demultiplexer
1 : 16 demultiplexer
1 : 32 demultiplexer
BLOCK DIAGRAM
TRUTH TABLE
Decoder
A decoder is a combinational circuit. It has n input and to a maximum m = 2n outputs. Decoder is identical to a
demultiplexer without any data input. It performs operations which are exactly opposite to those of an encoder.
BLOCK DIAGRAM
Code converters
Relay actuator
2 to 4 Line Decoder
The block diagram of 2 to 4 line decoder is shown in the fig. A and B are the two inputs where D through D are the
four outputs. Truth table explains the operations of a decoder. It shows that each output is 1 for only a specific
combination of inputs.
BLOCK DIAGRAM
TRUTH TABLE
LOGIC CIRCUIT
Encoder
Encoder is a combinational circuit which is designed to perform the inverse operation of the decoder. An encoder has
n number of input lines and m number of output lines. An encoder produces an m bit binary code corresponding to
the digital input number. The encoder accepts an n input digital word and converts it into an m bit another digital word.
BLOCK DIAGRAM
Priority encoders
Priority Encoder
This is a special type of encoder. Priority is given to the input lines. If two or more input line are 1 at the same time,
then the input line with highest priority will be considered. There are four input D0, D1, D2, D3 and two output Y0, Y1.
Out of the four input D3 has the highest priority and D0 has the lowest priority. That means if D 3 = 1 then Y1 Y1 = 11
irrespective of the other inputs. Similarly if D3 = 0 and D2= 1 then Y1 Y0 = 10 irrespective of the other inputs.
BLOCK DIAGRAM
TRUTH TABLE
LOGIC CIRCUIT
In the same way that gates are the building blocks of combinatorial
circuits, latches and flip-flops are the building blocks of sequential
circuits.
While gates had to be built directly from transistors, latches can be built from gates,
and flip-flops can be built from latches. This fact will make it somewhat easier to
understand latches and flip-flops.
Both latches and flip-flops are circuit elements whose output depends not only on the
current inputs, but also on previous inputs and outputs. The difference between a latch
and a flip-flop is that a latch does not have a clock signal, whereas a flip-flop always
does.
Latches
How can we make a circuit out of gates that is not combinatorial?
The answer is feed-back, which means that we create loops in the
circuit diagrams so that output values depend, indirectly, on
themselves. If such feed-back is positive then the circuit tends to
have stable states, and if it is negative the circuit will tend to
oscillate.
This latch is called SR-latch, which stands for set and reset.
It is not practical to use the methods that we have used to describe combinatorial
circuits to describe the behavior of the SR-latch. Later, we will show a method for
describing flip-flops and clocked sequential circuits. For now, we just rely on our
intuition to describe how latches work.
The SR-latch is meant to have at most one of its inputs equal to 1 at any time. When
both of its inputs are 0 it has two different stable states possible. Either x is 0, in
which case we have the following signal values:
The actual value depends on the history of input values as we will show next.
Now suppose that s is 1 (and therefore r is 0 since we allow at most one input to
be 1 at any time). We get the following signal values:
The 1 on the s input makes sure the output of the upper nor-gate is 0, and the two 0s
on the input of the lower nor-gate make sure the x output is 1.
Now suppose the s input goes from 1 to 0, while the r input remains at 0. The
second input of the upper nor-gate is 1, so the transition from 1 to 0 of the s input,
does not make any difference. The x output remains at 1. In this case, if
the s and r inputs are both 0, there is only one possible stable state, the one that
gives x the value 1.
Conversely, suppose that r is 1 (and therefore s is 0 since we allow at most one input
to be 1 at any time). We get the following signal values:
The 1 on the r input makes sure the x output is 0, and the two 0s on the input of the
upper nor-gate make sure the output of the upper nor-gate is 0.
Now suppose the r input goes from 1 to 0, while the s input remains at 0. The
second input of the lower nor-gate is 1, so the transition from 1 to 0 of the r input,
does not make any difference. The output of the upper nor-gate remains at 1. In this
case, if the s and r inputs are both 0, there is only one possible stable state, the one
that gives x the value 0.
From the discussion above, we conclude that the SR-latch is able to remember the last
state of the inputs, in the sense that it remembers which of the two inputs, s or r, last
had the value of 1.
When we need to draw an SR-latch, we use the following symbol:
Flip-flops
Latches are asynchronous, which means that the output changes
very soon after the input changes. Most computers today, on the
other hand, are synchronous, which means that the outputs of all
the sequential circuits change simultaneously to the rhythm of a
global clock signal.
The leftmost SR-latch is called the master and the rightmost is called the slave.
Let us first consider what happens when the clock signal is 1. In this case, the
two and-gates in front of the input of the master are open, i.e., they let the value of
the D-input through to the s input of the master, and the inverse of the D input to
the r input of the master. Thus, the value of the D input will go straight trough the
master to the x output of the master. But the two and-gates of the slave re closed, i.e.,
their outputs are always 0, so the slave keeps its old value.
When instead the clock signal is 0, the reverse is true, i.e., the and-gates at the input
of the master are closed, whereas the ones at the input of the slave are open. In this
case, the flip-flop is completely insensitive to changes in input.
Now, let us consider what happens when the clock goes from 1 to 0. For this to work,
we have to assume that the input remains the same during a brief period from right
before to right after the clock signal changes. The first thing that happens is that
the and-gates at the input of the master turn off, i.e., they become insensitive to further
changes in input. The value of the x output of the master is now the value of
the D input right before the clock started changing. A brief moment later, the clock
signal transition has traversed the inverter and reaches the and-gates of the slave.
These gates open, allowing the x output of the master to be propagated to the x value
of the slave. The x value of the slave, and therefore that of the entire flip-flop now
contains the value of the D input right before the clock started changing. We can say
that the clock transition copied the input to the output of the flip-flop. But at no point
in time is there a direct path from input to output. The output changes only as a result
of clock transitions from 1 to 0.
Finally, let us see what happens when the clock goes from 0 to 1. First, the and-gates
of the master open, letting the value of the D input into the master. By the time
the D value reaches the master, the clock signal transition reaches the and-gates of the
slave, and turns them off before the possibly modified output of the master reaches the
slave. Thus, the slave keeps its old value. From the outside, nothing seems to happen,
since the output does not change. From now on, however, the master is open to
changes in the input.
Here is the symbol we use for D-flip-flops:
The little triangle for the clock input indicates that this input is sensitive only
to transitions as opposed to levels as described in the previous paragraph. Sometimes
we do not draw the clock input at all when it is understood that it is there. Clock
signals are boring since they are all just connected to each other. There is therefore
little use to draw them all, and thereby clutter the diagram unnecessarily.