Week 8

OC-192 communications system block diagram
Laser
10 Gb/s
Mod
TIA + Preamp
10 Gb/s
Photo Diode
10 GHz
16
TX
Network
Processor 622Mb/s
16
RX
10 Gb/s
RX
16
622Mb/s
TX
Network
Processor
16
OC-192 (10 Gb/s) transceiver

0.18 m CMOS process
EECS 270C / Spring 2014
Prof. M. Green / U.C. Irvine
Transceiver block diagram:
10 GHz
10 Gb/s
Transmitter Block Diagram

FIFO
Control
CLK16IP
CLK16IN
DI15P
DI15N
16:1 MUX
LVDS
Parallel
Input Bus
Write
Pointer
INPUT REGISTER
DI0P
DI0N
OVF
16 X 10 FIFO
RESET
Output
Retime
Read
Pointer
SELFECB
TSCKP
TSCKN
CML
HighSpeed
Outputs
RB_LD
REF155EN
LVPECL REFCLKP
Ref.
Clock REFCLKN
TSDP
TSDN
DIVIDE-BY-16
10/10.7 GHz
CMU
LVDS
Output
Clock
CLK16OP
CLK16ON
LCKDET
IFSEL
VCP
VCN
Low-Frequency Input signals
Input clock
Input data aligned to input clock

(usually jittery)
Input data
T
Reference clock
Very low jitter (~10 ppm)

reference clock; used in CMU
to generate 10 GHz internal clock
tsh
Reference clock and input clock are not synchronized.

Maximum allowable variation between
Input clock & Reference clock is T tsh
Illustration of Input Timing Regimes

Reference clock
High-frequency clock
input clock
16
16
16:1 MUX
16
input data
Input clock
timing domain
Connection could
exhibit varying delay
Reference clock
timing domain
Variable phasing between

input & reference clock domains
can cause bit errors in MUX
First-In/First-Out (FIFO) Circuit (1)
16:1 MUX
We require an intermediate
block to resolve timing variations
between input & reference clock
First-In/First-Out Circuit (2)

Read clock based on input clock
Write clock based on reference clock
Read
clock
Write
clock
k
Din_0
Dout_0
Ref
clock
Synchronized
with input clock
Read
clock
Din_n
Write
clock
To serializer
(signals synchronized
with reference clock)
Dout_n
Ref
clock
Since these signals have period k times longer than the input period, the circuit can
tolerate k times larger variation between input & reference clocks.
FIFO approach:
Large amount of hardware (many latches)
Significant power dissipation unless static CMOS is used
Can handle arbitrarily large delay variations
Appropriate phase chosen
DLL approach:
Less hardware
Can handle modest delay variations
Better choice for BJT or GaAs processes
16:1 Multiplexer Tree Structure
5 Gb/s
10 Gb/s
2.5 Gb/s
1.25 Gb/s
1.25 GHz
2.5 GHz
static
CMOS
5 GHz
CML
2:1 MUX cell details
D flip-flop with extra latch
10
1
f
4
1
f
2
1
f
2
10ISS
2ISS
5ISS
ISS
Total current: 18ISS
Assume all blocks have:

Tail current ISS
Resistor R
Diff pair transistor sizes W/L
11
We can take advantage of gain/bandwidth tradeoff by appropriate scaling:
W
L
W
L
W
L
Design parameters:
ISS
R
W/L CL
W
L
1
f
2
Idea:
= RCg
= 2RCg
1
1
1
ISS ,2R, W, Cg
2
2
2
I ,R,W,C
ISS ,R,W,Cg
Lower bit rate allows lower power!
SS
12
1
f
4
1
f
2
MSCALE=1/8
10
ISS
8
MSCALE=1/2
1
1
ISS ,2R, W
2
2
1
1
ISS ,2R, W
2
2
= 2RCg
ISS
= 2RCg
5
ISS
2
MSCALE=1
ISS ,R,W
Cp 10 fF
GSCALE=3
ISS = 1.2 mA
= RCg
ISS
MSCALE=1/2
1
1
ISS ,8R, W
8
8
= 4RCg
1
f
2
Itotal = 5.75ISS
= 6.9 mA
13
Clock Dividers
The operation of real high-speed clock dividers is more complex

14
Clock divider based on CML D flip-flop:
&W #
$ !
% L "D
&W #
$ !
% L "D
&W #
$ !
% L "C
&W #
$ !
% L "L
&W #
$ !
% L "L
&W #
$ !
% L "D
&W #
$ !
% L "C
&W #
$ !
% L "D
&W #
$ !
% L "L
&W #
$ !
% L "C
&W #
$ !
% L "L
&W #
$ !
% L "C
Divider sensitivity curve:

Vmin = minimum input clock amplitude required for
correct operation.
fso = self-oscillation frequency
Vmax
Vmax = maximum dc differential voltage that can be

applied to the input clock for which the circuit
self-oscillates.
15
Sensitivity Curve Analysis
Region I: Desired frequency divider operation

Region II: Quasiperiodic operation
Region III: Slew-rate limited operation
16
Region II: Quasiperiodic behavior

self-oscillating
fin = 11GHz
locked
17
Region III: Slew-rate limited Behavior
Sine-wave input
Square-wave input
18
Effect of Transistor Sizes on Sensitivity Curve
Driver transistors
Latch transistors
Clock transistors
19
Alternatives to DFF-Based Clock Dividers
Latches present large capacitive load ! slow
20
At very high frequencies, latch transistors are

not necessary and only add capacitance to
the circuit:
21
Ring-Oscillator-Based Divider
Behaves like a 4-stage ring oscillator with injection of full-rate frequency.
22
Comparison of Sensitivity Curves
Conventional divider:
Dynamic divider:
Wider frequency range; lower self-oscillation frequency

Narrow frequency range; higher self-oscillation frequency
23
Effect of Non-Ideal Clock Signals

ISS
0
VDD
I1
I2(t)
I1(t)
Vout-(t)
I2
VDD ISSR
Vout+(t)
VDD ISS(R+R)
ISSR
0
ISS(R+R)
Vout+(t)
Vout-(t)
Offset resistance causes deviation from

50% duty cycle in clock signal.
24
Result of nonideal half-rate clock is Periodic Jitter.
with offset
Half-rate clock
ideal
MUX output
with offset
ideal
25
Retimer eliminates this problem:

10 Gb/s data
10 Gb/s retimed data
5 Gb/s
retimer
5 GHz
10 GHz clock
retimed output
Full-rate clock
(could be non-50% duty cycle)
26
Internal MUX Timing

5 Gb/s
10 Gb/s data output
tp2
2.5 Gb/s data input
2.5 MHz
5 GHz
10 GHz clock
tp1
tp1 & tp2 are clock-to-Q delays.
Because the clock & data flow in opposite directions,

alignment between 5 Gb/s data & 5 GHz clock
is determined by the sum: tp1 + tp2
(High sensitivity to processing / temp. corners)
27
Serial Output 50 Line Driver
50 back termination used to reduce reflections.

CML blocks scaled up so that last stage drives ac load of 25.
Shunt-peaking used in second stage.
28
Receiver Block Diagram

RB_LD
LOS
DETECT
LOSB
RXDOUT0P
RDINN
9.953/10.3125/10.664/
10.709Gbps CML
OUTPUT
REGISTERS
1:16 DEMUX
RDINP
RXDOUT0N
622.08/644.54/666.51/
669.31Mbps LVDS
RXDOUT15P
RXDOUT15N
RXREFCLKP
RXREFCLKN
RATESEL0/1
RESETB
VCP
VCN
LCKREFB
REF155ENB
RXMCLKENB
Divide-by-16
RXPOCLKP
RXPOCLKN
CDR
Divide-by-4
RXMCLKP
RXMCLKN
LCKDET
9.953/10.3125/10.664/
10.709G
Test Only
RSCLKP
RSCLKN
29
DMUX Architecture
1:2
2:4
4:8
A
B
D
1:2
A
B
D
1:2
8:16
A
B
D
1:2
10Gb/s Data
A
B
D
1:2
A
B
D
1:2
A
B
D
1:2
A
B
622Mb/s
1:2
10GHz CLK
/2
/2
/2
/2
/2
311MHz
622MHz
CML
Static CMOS
30
1:4 DMUX Tree Structure

5 Gb/s
10 Gb/s data input
2.5 Gb/s data outputs
10 GHz clock
5 GHz
2.5 GHz
31
1:2 DMUX cell details:
32
Internal DMUX Timing
5 Gb/s
10 Gb/s data input
2.5 Gb/s data output
tp2
10 GHz clock
5 GHz
2.5 GHz
tp1
tp1 & tp2 are clock-to-Q delays.
Because the clock & data flow in the same direction,
alignment between 5 Gb/s data & 2.5 GHz clock
is determined by the difference: tp1 tp2
(Low sensitivity to processing/temp. corners)
33
Crosstalk in Transceivers
f1
f2
Capacitive coupling between VCOs can cause frequency pulling

Momentary differences in frequencies between 2 VCOs can give rise
to additional jitter.
34
Crosstalk Measurement
CMU reference clock
fref
10 GHz
=
1+104
16
Serial input data

10 Gb/s
Low-frequency
inputs/outputs
Low-frequency
inputs/outputs
output clock
recovered clock
10 GHz + 100ppm
10 GHz
output data
10 Gb/s + 100ppm
Jitter is measured at TX output clock (or data) and RX recovered clock.

35
Techniques for Reducing Transceiver Crosstalk
Sufficient physical separation between VCOs

Separate supply connections to package for each block
(e.g., CMU, CDR, MUX, DMUX, FIFO, etc.)
Ample guard rings to minimize substrate coupling
Very difficult to simulate & predict!
36
SONET Jitter Specifications
1. Jitter Generation (transmitters)

2. Jitter Tolerance (receivers)
3. Jitter Transfer (repeaters)
37
Jitter Generation (1)
Wideband jitter (p-p or rms) can be measured

directly from serial output data signal
DJ always specified in peak-to-peak

RJ rms jitter well-characterized
RJ peak-to-peak jitter dependent on measurement time (increases
without bound)
SONET:
JPP usually measured over a specified frequency range.
Gigabit Ethernet & Fiber Channel:
Equivalent JPP determined by measured BER.
38

SONET jitter generation is specified within a certain jitter frequency range.
For OC-192: 50 kHz 80 MHz
To measure narrowband jitter generation, we can:

A.
Measure the recovered clock from a golden CDR:

Ref. clock
TX
CDR
output data
(low jitter generation)
recovered clock
Should have
jitter bandwidth > 80MHz
10 GHz
SONET OC-192
bandpass filter
to jitter analyzer
39

B.
Measure the TX output clock directly

(assuming its jitter is the same as the data):
Ref. clock
TX
output data
TX output clock
10 GHz
to jitter analyzer
Note: ISI is usually measured separately (peak-to-peak only).
40

Measured at output clock;
231-1 PRBS serial data applied to input
9.95328 GHz
10.6642 GHz
Phase noise:
-100 dBc/Hz @ 1MHz offset
Jitter generation (SONET filter):
5.6mUI rms / 60mUI p-p
Phase noise:
-100 dBc/Hz @ 1MHz offset
Jitter generation (SONET filter):
6.2mUI rms / 65mUI p-p
41

Jitter measurements from clock:
Jitter Generation (231-1 PRBS):

6.44 ps pp (wide band)
0.38ps rms (within SONET band)
Closed-loop VCO phase noise (231-1 PRBS):

107 dBc/Hz @ 1 MHz offset
42

231-1 PRBS input data applied:
10.6642GHz clock
Wideband jitter:
7.5ps p-p / 1.2ps rms
10.6642Gb/s data
Wideband jitter:
10.7ps p-p / 1.8ps rms
43
Jitter Tolerance (1)

Experiment: Apply serial data to CDR with jitter at a certain frequency.
Increase the jitter amplitude until a bit error occurs.
retimed data out

Serial data in
To DMUX
retimer
recovered clock
If data jitter & recovered clock jitter

could perfectly track, then retiming
would be error-free.
Recovered clock
tsh
Data in
44

Given CDR open-loop characteristic
( )
G j = K pd
K^vco
F j
j
( )
fdata
fclock
data clock
1
=
data
1+G
clock
G
=
data 1+G
data(max) ( ) = 1+G( j ) data clock
max
= 1+G( j ) 2
T tsh
T
% t (
JTOL( ) = 1+G( j ) '1 sh *
& T )
(expressed in UI)
45

10000
rate: 10.7Gb/s
Bit rate:Bit
10.7
Gb/s
Pattern: 231-1PRBS
31
Pattern:
BER
2 threshold:
-1PRBS
10-12
Data in: 50 mV pp
BER threshold: 10-12
Jitter Tolerance [UIpp]
1000
100
10
1
0.1
0.01
10
100
1K
10K
100K
1M
10M
100M
Jitter
Frequency (Hz)" [Hz]
Jitter
Frequency
Jitter Tolerance > 40 ps pp at high frequency

46
Jitter Transfer
repeater
OE
[ ( )
RX
TX
HRX ( j )
HTX ( j )
( )]
j HRX j
n repeaters: HRX
EO
Jitter peaking should be minimized.
Jitter Transfer Mask:
0.1dB
-20 dB/decade
f0
47
Electrical-to-Optical Interfaces (1)

Electrical to optical (TX):
IL
MUX
laser
driver
optical
output
power
laser diode or
Vertical Cavity Surface Emitting Laser
(VCSEL)
Ith ~ 10mA
IL
48

Electroabsorption modulator
Pout
Pin
Pin
VM
Pout
Vswing~ 3V
VM
Operates by making optical material

more or less absorptive.
49
49

Mach-Zender modulator:
Mach-Zender interferometer:
Pout
Pin
Invented in 1890s
Used to precisely measure optical
phase shift of materials.
By using constructive/destructive
interference, can be used as a laser
modulator.
Vswing ~ 6V
VM
50
50

Optical pulsewidth distortion commonly occurs due to:
Unequal turn-on/turn-off times of laser diode
Non-ideal bias voltage in modulators.
Electrical signal
(IL or VM)
Results in DCD
Optical output
Additional circuitry to correct pulsewidth is often added to system...
51
51

Optical output control circuit:
laser diode
VM
monitor diode
IB
Vref
Feedback sets IB =
Vref
R
52
52
Optical Receiver Block Diagram
OE
TIA
-18 dBm
10 A
LA
10 mV p-p
EQ
CDR
DMUX
400 mV p-p
53
53
Optical-to-Electrical Interfaces (1)

p-i-n photodetector structure:
resulting
electrical
current
circuit model:
+
n
+
i
VR~5V
_
CD
ID = Popt
p
applied
optical
signal
= 0.6 ~ 0.9 A W
CD ~ 400 fF
54
54
Optical-to-Electrical Interfaces (2)
DCD & ISI are evident.

Noise is higher at logic 1 than at logic 0.
2
Photodetector noise: i n = 4qPopt f
Eye diagram of PRBS resulting

from 96 km of single-mode fiber
and photodetector.
55
55
Transimpedance Amplifier (TIA)

Used to convert photodetector current into voltage.
R
A0
Iin
Vout
Cd
from photodetector
Vref
low-impedance node maintains

nearly constant detector voltage
good linearity.
56
56
Transimpedance Amplifier (2)

R
Transimpedance: ZT
Cg
Iin
photodetector
A0
Cd
Vout
Input impedance: Zin
Vout
1
= Rf
Iin
1+ 1
A0
V
Rf
=
Iin 1+ A0
Vref
Loop gain: A(s) f (s) =
A0
1
(1+ s p1) (1+ s p2 ) 1+ sRf (Cd + Cg )
additional pole limits

closed-loop BW
57
57

Noise analysis:
i nR
v out
Good sensitivity requires:

Large Rf
Tradeoff with BW
Large Cg
Large gm
v ni
2
out
2
ni
=v + i
2
nR
2
f
2
= i eq
Rf2
2
eq
v ni2
2
= 2 + i nR
Rf
v ni2 =
4kT
K f
f + f
gm
Cg f
2
i nR
=
4kT
f
Rf
2
eq
4kT %
Kf (
=
'1+
+
* f
Rf & gm Rf Cg Rf f )
58
58
Cd
Cd
LB
Cg
Cg
Cd decoupled from feedback network

Common-gate device increases noise
LB provides decoupling (series peaking);

could be realized by bondwire.
59
59
Limiting Amplifiers
Requirements:
Amplify input signal with variable amplitude (~10-30 mV) to a fixed-amplitude
(~450 mV) output.
Sufficiently high bandwidth
Sufficiently low noise
Low offset voltage
+
Vin
A(s)
A(s)
A(s)
Single stage:
n stages
n-stage amplifier:
" A %n
n
0
A (s) = $
'
# 1+ s p &
A0
A(s) =
1+ s p
+
Vout
n
Overall gain: A0
Overall bandwidth: p 21 n 1
60
60
7-Stage Limiting Amplifier Example (1)

Each stage uses shunt-peaked CML buffer with:
A0 = 5.5 dB
BW = 10 GHz
A j (dB)
( )
7th stage output
1st stage output
100 MHz
1 GHz
10 GHz
100 GHz
61
61
7th stage output
7th stage output
6th stage output
6th stage output
1st stage output
Input amplitude = 20 mV p-p
1st stage output
62
62
7th stage output

6th stage output
1st stage output
Input-referred offset of 5 mV applied
Vout A0n VOS

Offset-cancellation circuitry required!
63
63
Limiting Amplifier Offset Compensation

RL
n-stage
amplifier core
RL
+
V
1
+
V
out
VOS
M1
+
vin
M1
M1
M1
+
Vout
RF
RF
CF
offset compensation
CF
lowpass filter
H.-Y. Huang et al., A 10-Gb/s

inductorless CMOS limiting amplifier
with third-order interleaving active
feedback, JSSC, May 2007, pp.
1111-1120.
compensation circuit:
[(
V1 = gm1R vin + VOS Vout V1 = gm1R VOS Vout

amplifier circuit:
)
Vout
v1 = gm1R vin
vout = gm1RA0n vin
Vout = A0n V1 Vout = A0n V1
vout = A0n v1
gm1RA0n
=
VOS VOS
1+ gm1RA0n
64
64

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OC-192 communications system block diagram

OC-192 (10 Gb/s) transceiver

Prof. M. Green / U.C. Irvine

Transceiver block diagram:

EECS 270C / Spring 2014

Prof. M. Green / U.C. Irvine

Transmitter Block Diagram

Prof. M. Green / U.C. Irvine

Low-Frequency Input signals

Input data aligned to input clock

Very low jitter (~10 ppm)

Reference clock and input clock are not synchronized.

Prof. M. Green / U.C. Irvine

Illustration of Input Timing Regimes

EECS 270C / Spring 2014

Variable phasing between

Prof. M. Green / U.C. Irvine

First-In/First-Out (FIFO) Circuit (1)

EECS 270C / Spring 2014

Prof. M. Green / U.C. Irvine

First-In/First-Out Circuit (2)

Prof. M. Green / U.C. Irvine

Appropriate phase chosen

Prof. M. Green / U.C. Irvine

16:1 Multiplexer Tree Structure

2:1 MUX cell details

D flip-flop with extra latch

EECS 270C / Spring 2014

Prof. M. Green / U.C. Irvine

Total current: 18ISS

Assume all blocks have:

Prof. M. Green / U.C. Irvine

We can take advantage of gain/bandwidth tradeoff by appropriate scaling:

Lower bit rate allows lower power!

EECS 270C / Spring 2014

Prof. M. Green / U.C. Irvine

EECS 270C / Spring 2014

Prof. M. Green / U.C. Irvine

The operation of real high-speed clock dividers is more complex

Prof. M. Green / U.C. Irvine

Clock divider based on CML D flip-flop:

Divider sensitivity curve:

EECS 270C / Spring 2014

Vmax = maximum dc differential voltage that can be

Sensitivity Curve Analysis

Region I: Desired frequency divider operation

EECS 270C / Spring 2014

Prof. M. Green / U.C. Irvine

Region II: Quasiperiodic behavior

EECS 270C / Spring 2014

Prof. M. Green / U.C. Irvine

Region III: Slew-rate limited Behavior

EECS 270C / Spring 2014

Prof. M. Green / U.C. Irvine

Effect of Transistor Sizes on Sensitivity Curve

Prof. M. Green / U.C. Irvine

Alternatives to DFF-Based Clock Dividers

Latches present large capacitive load ! slow

EECS 270C / Spring 2014

Prof. M. Green / U.C. Irvine

At very high frequencies, latch transistors are

EECS 270C / Spring 2014

Prof. M. Green / U.C. Irvine