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ABSTRACT
In this paper a Pulse Triggered Flip-Flop based on
Split Output TSPC Latch suitable for low power
high performance application is proposed. The
Pulse Triggered Flip-Flop is constructed using a
split output TSPC latch with embedded logic.
Proposed flip-flop has the advantages of simple
structure, less number of transistors, low
dissipation power and lower transistor area.
Proposed circuit is simulated in cadence analog
design environment with 0.25m CMOS
technology. Simulation results show that by using
the proposed circuit, dissipation power can be
reduced by 40%, number of transistors by 40%,
current drawn by 48% and transistor area can be
reduced by 68%.
KEYWORDS:
1. INTRODUCTION
Most digital circuits today are constructed
using static CMOS logic and edge- triggered
flip-flops. Although such techniques have
been adequate in the past and will remain
adequate in the future for low performance
design, they will become inefficient for highperformance components as the number of
transistors are increasing resulting in increase
of area. Some conventional high performance
flip-flops like Hybrid Latch Flip-Flop (HDFF)
and Semi Dynamic Flip-Flop (SDFF) have
the disadvantage that they have large amount
of power dissipation due to redundant
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Proceedings of the Third International Conference on Digital Information Processing, E-Business and Cloud Computing, Reduit, Mauritius 2015
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Proceedings of the Third International Conference on Digital Information Processing, E-Business and Cloud Computing, Reduit, Mauritius 2015
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Proceedings of the Third International Conference on Digital Information Processing, E-Business and Cloud Computing, Reduit, Mauritius 2015
Conditions
Supply Voltage
Temperature
Rise time of
100ps
input signal
Fall time of
100ps
input signal
Clock frequency 100 MHz
Clock duty
50%
cycle
Delay
Between 50%
calculations
points
0.25um
TSMC deep
submicron
0.25um
Nominal
2V
25 degree C
Flip-Flop
Flip-Flop
with
embedded
logic
1-bit
registered
full adder
Benchmark
design (m2)
38.115
Proposed
design (m2)
23.607
53.615
35.480
250.901
172.203
100ps
100ps
100 MHz
50%
Circuit
Between 50%
points
Flip-Flop
Flip-Flop
with
embedded
logic
Benchmark
design (ps)
193
Proposed
design (ps)
180
205
180
Proposed
15
Circuit
27
227
19
90
Circuit
Flip-Flop
Flip-Flop
with
embedded
logic
1-bit
registered full
adder
25.695
Proposed
design
(m)
15.9
35.995
23.82
168.39
116.04
Benchmark
design (m)
Setup time
Flip-Flop
Flip-Flop
with
embedded
logic
Hold time
Flip-Flop
Flip-Flop
with
embedded
logic
Benchmark
design
Virtual Real
(ps)
(ps)
Proposed
design
Virtual Real
(ps)
(ps)
-55
237
-58.82
210.3
-30
263
-55.05
223.8
160.3
-133
179
-90
160
-133
126
-154
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Proceedings of the Third International Conference on Digital Information Processing, E-Business and Cloud Computing, Reduit, Mauritius 2015
Clk (ps)
(LH)
(HL)
190.2
305.1
190.1
330
231.5
283.1
280
272.7
(ps)
(LH)
(HL)
291.4
299.8
231.7
344.7
301.6
266.1
299.9
283.6
Circuit
Flip-Flop
Flip-Flop with
embedded
logic
1-bit registered
full adder
Benchmark
design (nW)
1.4
Proposed
design (nW)
0.445
1.4
0.456
11.7
4.63
CONCLUSION
A Design using Pulse triggered Flip-Flop
based on split output TSPC latch is proposed
and simulated in a 0.25m process. Our
simulation results justify our analysis that we
reduced power dissipation by 40%, transistor
area by 68%, transistor count by 40% and
current drawn by 48% without affecting the
high performance of the circuit.
ACKNOWLEDGEMENT
The authors thank Guru Nanak Dev
Engineering College, Gill Road, Ludhiana,
for technical support for implementation and
simulation.
REFERENCES
Circuit
Flip-Flop
Flip-Flop with
embedded
logic
1-bit registered
full adder
Benchmark
design (nA)
0.7
Proposed
design (nA)
0.23
0.7
0.23
6.1
2.1
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