You are on page 1of 3

Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop

Featuring Efficient Embedded Logic


AIM:
The main aim of the project is to design Low-Power Dual Dynamic Node
Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic.

(ABSTRACT)
A new dual dynamic node hybrid flip-flop (DDFF) and a novel embedded logic
module (DDFF-ELM) based on DDFF. The proposed designs eliminate the large
capacitance present in the precharge node of several state-of-the-art designs by
following a split dynamic node structure to separately drive the output pull-up and
pull down transistors. The aim of the DDFF-ELM is to reduce pipeline overhead. It
presents an area, power, and speed efficient method to incorporate complex logic
functions into the flip-flop. The leakage power and process-voltage-temperature
variations of various designs are studied in detail and are compared with the
proposed designs. Also, DDFF and DDFF-ELM are compared with other state-ofthe-art designs by implementing a 4-b synchronous counter and a 4-b Johnson updown counter. The performance improvements indicate that the proposed designs
are well suited for modern high-performance designs where power dissipation and
latching overhead are of major concern
Proposed Architecture:
We can Implement the low power techniques like sleepy stack, sleepy keeper
which will reduce dynamic power . To all the circuits in the paper.

Advantage:
An analysis of the overlap period required to select proper pulse width was
provided in order to make the design process simpler. The proposed DDFF
eliminates the redundant power dissipation present in the XCFF.
By eliminating the charge sharing, the revised structure of the proposed flipflop, DDFF-ELM, is capable of efficiently incorporating complex logic in to
the flip-flop. The presented ELM outperforms the SDFF in the CLK driving
power and in internal power dissipation.
BLOCK DIAGRAM:

TOOLS: hspice_vA-2008.03, t-spice

REFERENCE:
[1] H. Patrovi, R. Burd, U. Salim, F. Weber, L. Di Gregorio, and D. Draper, Flowthrough latch and edge-triggered flip-flop hybrid elements, in Proc. IEEE ISSCC
Dig. Tech. Papers, Feb. 1996, pp. 138139.
[2] F. Klass, Semi-dynamic and dynamic flip-flops with embedded logic, in
Proc. Symp. VLSI Circuits Dig. Tech. Papers, Honolulu, HI, Jun. 1998, pp. 108
109.
[3] J. Yuan and C. Svensson, New single-clock CMOS latches and flip flops with
improved speed and power savings, IEEE J. Solid-State Circuits, vol. 32, no. 1,
pp. 6269, Jan. 1997.
[4] A. Hirata, K. Nakanishi, M. Nozoe, and A. Miyoshi, The cross charge control
Flip-flop: A low-power and high-speed flip-flop suitable for mobile application
SoCs, in Proc. Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2005, pp. 306307.

You might also like