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VHDL Entry and Simulation Tutorial

Table Of Contents
VHDL Entry and Simulation Tutorial................................................................................................ 1
Introduction .................................................................................................................................. 1
Design Entry................................................................................................................................. 1
Simulation .................................................................................................................................. 29
Creating Testbenches................................................................................................................ 37
Debugging.................................................................................................................................. 41

VHDL Entry and Simulation Tutorial


Introduction
The focus of this tutorial is to familiarize you with the creation cycle of designs based on the
VHDL language. This tutorial is based on freq_meter design shipped with Active-HDL
environment. Though some of the files are initially created using State Machine and Block
Diagram Editors, the generated code describing design functionality is pure VHDL.
By accomplishing the following tutorial you will create a frequency meter comprised of the
following models:
BCD counter created from four decimal counters and AND gates:

cnt_bcd.bde:
cnt_4b.vhd
and2.vhd
the control state machine control.asf
the hexadecimal to LCD digital display decoder
the measuring unit built upon the above mentioned components

Design Entry
1. By starting the Active-HDL environment you will see the Getting Started window that either
lets you create a new workspace or open an existing one. Since you will create a new project
check the Create new workspace option and accept it by clicking the OK button.
2. The New Workspace wizard window will be invoked. Provide the name and location for the
workspace to which the new design will be attached. Click the OK button.

3. In the next step, you need to define how you would like to create the design resources. Check
the Create an empty design option and click the Next button.
4. In the next window you have to specify information about the configuration of the Block
Diagram and the default language - VHDL. Additionally, you can chose the synthesis and
implementation tools which can be used to synthesize and implement the current project and
specify the programmable device family to be used.
After specifying required options, click the Next button.
5. This will open the New Design Wizard window for creating the new design sources files. Now
you need to type the name of the design and set its location. In the Type the design name field,
type the tutorial_VHDL name and leave the default location of the design folder suggested by

VHDL Entry and Simulation Tutorial


Active-HDL. The Design Wizard will create a working library with the same name as the name of
the created design. This library will contain all models compiled during design creation.

After filling out the fields, advance to the next window by clicking Next.
6. In the last window of the New Design Wizard press the Finish button to accomplish the design
creation stage.
7. As you can see in the Design Browser window, a new empty design has been created along
with a working library named after the design: tutorial_VHDL.

4-bit Counter
8. Now we are ready to create project resources. Double-click the Add New File icon located in
the Design Browser window. In the Add New File window switch to Wizards tab and click on the
VHDL Source Code Wizard icon. Next, click the OK button.

VHDL Entry Tutorial


9. A Wizard is invoked to guide you through the creation process. Make sure that the Add the
generated file to the design box is checked.
Advance to the next window by clicking Next.
In the New Source File Wizard window you have to define the new created file name and
optionally an entity and architecture name.

Type cnt_4b in the first field and click Next button.


10. The counter has the following ports:

CLK - 1-bit input signal


ENABLE - 1-bit input signal
RESET - 1-bit input signal
FULL - 1-bit output signal
Q - 4-bit output signal

To add a new port to a unit click the New button and type its name in the Name field selecting the
direction in the Port direction box. For the multi-bit ports such as Q , specify the range by
clicking the index arrows in the Array Indexes field as shown in the figure.

11. After clicking the Finish button, the automatically generated resource file is opened in the HDL
Editor window.

VHDL Entry and Simulation Tutorial

As you can see in the figure above, the skeleton VHDL file contains port declarations and empty
architecture requiring your modification. Insert the cursor below the -- enter your statements here
-- line as shown in the figure.
12. The counter code is incomplete without the behavior description. To complete the
architecture, insert the following code:
process (CLK, RESET)
begin
if RESET = '1' then
Qint <= (others => '0');
elsif CLK='1' and CLK'event then
if ENABLE = '1' then
if Qint = 9 then
Qint <= (others => '0');
else
Qint <= Qint + 1;
end if;
end if;
end if;
end process;
Q <= Qint;
FULL <= '1' when (Qint = 9) else '0';
The below HDL Editor window displays the full counter contents.

VHDL Entry Tutorial

13. You need to declare the Qint signal in the declarative part of the architecture. Insert the
following line before the begin keyword:
signal Qint: STD_LOGIC_VECTOR(3 downto 0);
See the correct code in the figure.

14. Since the counter uses the vector type addition operator in its description you need to expand
the description with the std_logic_unsigned library declaration.
Place the following line below the std_logic library declaration in the upper part of the file:
use IEEE.std_logic_unsigned.all;

15. Such modified code is complete and ready for compilation. To compile the file, right-click its
name in the Design Browser window and choose the Compile option from the pop-up menu.

VHDL Entry and Simulation Tutorial

16. A successful compilation is checked by a green check mark next to file name and is
appropriately reported in the Console window. There is also a sign next to the compiled file,
allowing branch expanding of the entity-architecture pair. The Design Browser contents are
shown in the following figure.

Notice how the compiled model has been automatically attached to a working library.
BCD Counter
17. To create a BCD counter you need to connect four 4-bit counters and utilize an AND gate.
You will now create the VHDL description of an AND gate. To add a new file to the design,
double-click the Add New File icon in the Design Browser window.
18. This will open the Add New File window that lets you choose the creation method. Switch to
the Wizards tab and select the VHDL Source Code Wizard by clicking the OK button.
19. A Wizard is invoked to guide you through the creation process. Make sure that the Add the
generated file to the design box is checked.
Advance to the next window by clicking the Next button.
Here, you need to specify the name of the file and optionally the name of the model entityarchitecture pair. Type the and2 name in the first field as shown in the figure.

VHDL Entry Tutorial

Click the Next button to go further.


AND Gate
20. In this step you will declare the AND gate ports. After clicking the New button, type the port
name in the Name field and specify its direction in the Port direction box.
Enter the following ports using the above method:

a0 - input port
a1 - input port
y - output port

Upon entering the above listed ports, finish the port declaration part by clicking the Finish button.
21. The results are shown in the Design Browser window. There is a new and2.vhd file.

22. The newly created file is automatically opened in the HDL Editor window. Type the below
assignment after the -- enter your statements here -- line describing the AND gate behavior.
y <= a0 and a1;

VHDL Entry and Simulation Tutorial

23. Such a modified file needs to be compiled. You can compile files by clicking the
button. This will compile the file opened in the HDL Editor window.

toolbar

As a result, the Design Browser displays a plus sign next to the and2.vhd file. There is an and2
entity-architecture pair attached to the file branch and the appropriate model is automatically
attached to the working library as well.
24. Using the 4-bit counter and the AND gate descriptions you can now create a BCD counter
comprised of four 4-bit counters and one AND gate. Double click the Add New File option in the
Design Browser window and switch to the Wizards tab in the opened window.

Choose the Block Diagram Wizard and accept your choice with the OK button.
25. The New Source File Wizard window is invoked. Make sure that the Add the generated file
to the design box is checked. Advance to the next window by clicking the Next button.
26. The schematic you create can be converted to three different file formats: EDIF, VHDL and
Verilog. In your case select VHDL and click the Next button.

VHDL Entry Tutorial


27. Similarly to the AND gate description you need to enter the name of the file and optionally
entity-architecture pair. Type the cnt_bcd in the first field as seen in the figure.

Go to the next step by clicking the Next button.


28. At this point you need to specify the counters ports. After clicking the New button, type the
port name in the Name field and specify its direction in the Port direction box. For the multi-bit
outputs such as: bcd_a, bcd_b, bcd_c and bcd_d specify their range by clicking the index arrows
in the Array Indexes field as shown in the figure.
Enter the following ports using the described method above:

clk, reset, gate - input ports - single input port,


bcd_a, bcd_b, bcd_c, bcd_d - 4-bit output port

Finish the step by clicking the Finish button.


29. The Design Browser window now displays a new cnt_bcd.bde file.

30. The Block Diagram Editor window is automatically opened with the port pads specified by
the wizards.

VHDL Entry and Simulation Tutorial

The Block Diagram Editor toolbar contains the Symbol Toolbox


place previously generated symbols on the schematic.

button that allows you to

31. By clicking the Symbol Toolbox button you open the following window. Notice that there
already are two design symbols for the and2 and cnt_4b files.

32. Drag the and2 and cnt_4b symbols onto the schematic and drop them according to the figure.

You can close the System Toolbox window by clicking the toolbar button again.
33. The symbols placed on the schematic must be connected properly. To create a single wire
connection click the Wire

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button on the toolbar. This will switch the cursor to the drawing

VHDL Entry Tutorial

mode
. Now click somewhere on the schematic and drag the wire. Notice how the line follows
the cursor. To connect two symbol pins click the source pin once and drag the wire to the
destination pin. Click the pin once and the wire connection will be automatically created. Connect
the symbols as shown in the figure.
NOTE: To delete any wire segment, switch to the Select mode. Click the wire once and hit the
Delete keyboard key.

34. To connect the reset and clk signals, you will employ a named connection technique. It
utilizes the global signals that let you connect pins without actually drawing wires. The connection
is established by naming the global signal and connected pins. To create a global signal use the
button located in the Block Diagram toolbar. After clicking the button, place the
Global Wire
two global signals as shown in the figure.

35. Switch to the Select mode (click the arrow icon on the toolbar or press the Escape key) and
double-click the Global0 and Global1 signals to change their names to clk and reset them
respectively.

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VHDL Entry and Simulation Tutorial


36. There are output pins left unconnected. These are vectors and require bus connections. To
draw a bus use the Bus
change its shape to

button located on the toolbar. By clicking the button the cursor will

. Similarly to drawing the wire, create the following connections between:

The Q output of the first counter with the bcd_d(3:0) pin


The Q output of the second counter with bcd_c(3:0) pin
The Q output of the third counter with bcd_b(3:0) pin
The Q output of the fourth counter with bcd_a(3:0) pin

The complete schematic should look as follows:

37. The completed schematic can now be compiled. Right-click the cnt_bcd.bde schematic file in
the Design Browser window and choose the Compile option from the pop-up menu.

The file successfully compiled is marked in the Design Browser window by a green check mark
. During the compilation Active-HDL automatically generates a VHDL netlist for the schematic.

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VHDL Entry Tutorial

Hex to LED Decoder


38. The frequency meter contains a hexadecimal to LED display decoder. To create the decoder,
double-click the Add New File branch in the Design Browser window. Switch to the Wizards tab
in the opened window.
After selecting the VHDL Source Code Wizard option click the OK button.
39. Add the generated file to the design and click the Next button.
Advance to the next window by clicking the Next button.
40. As done before enter the name of the file and entity-architecture pair. Type the hex2led name
in the first field as shown in the figure.

41. Similarly to the previous cases, define the ports using the New button.

hex - 4-bit input port


led - 7-bit output port

Click the Finish button to end the declaration step.


42. The generated file is automatically attached to the Design Browser tree with the hex2led.vhd
name.

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VHDL Entry and Simulation Tutorial

43. The file is automatically opened in the HDL Editor window. Its contents require some
modifications. Place the cursor under the -- enter your statements here -- line.

44. Active-HDL comes with a Language Assistant that speeds up the creation process providing
you with ready to go examples of frequently used models and functions.
toolbar button. Navigate to the Synthesis
To launch the Language Assistant click the
templates branch and locate the HEX2LED Converter model. Right click its name and choose
the Use option from the pop-up menu.

45. After performing this action, the decoder description should be copied into a previously
selected place as shown in the figure.

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46. A compilation of the modified decoder file can be performed with the Compile
button
located in the Active-HDL toolbar. Successful compilation is reported in the Console window and
marked in the Design Browser.

Top-level schematic
47. A design binding the components you created earlier will be created in the Block Diagram
Editor. Double-click the Add New File branch in the Design Browser window. Choose the
Wizards tab in the opened window and select the Block Diagram Wizard icon. Click the OK
button.
48. In the New Source File Wizard window accept the default settings and advance to the next
window by clicking the Next button.
49. Choose VHDL as the resulting code language for the block diagram and click the Next
button.
50. At this point enter the entity and the file name for the created file. Type the freq_top in the first
field and click the Next button.

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VHDL Entry and Simulation Tutorial

Using the method described previously, click the New button and declare the following model
ports:
Inputs:

f_input - one bit input signal of STD_LOGIC type


f_pattern - one bit input signal of STD_LOGIC type
reset - one bit input signal of STD_LOGIC type
start - one bit input signal of STD_LOGIC type

Outputs:

led_d - 7-bit vector of STD_LOGIC type


led_c - 7-bit vector of STD_LOGIC type
led_b - 7-bit vector of STD_LOGIC type
led_a - 7-bit vector of STD_LOGIC type

After entering the ports, click the Finish button to end the creation process.
51. The Design Browser displays a new freq_top.bde block diagram file.

The freq_top.bde is automatically opened in the Block Diagram Editor window.

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VHDL Entry Tutorial


52. The Block Diagram Editor contains the model port pads declared in the wizard windows.
So far, you have described the behavior of the design by using the VHDL code to draw the
schematics based on the symbols created from the VHDL models. This method of developing
designs is called the bottom-up methodology.
An opposite top-down methodology also exists where empty symbols are drawn in the Block
Diagram Editor or State Machine Editor and their contents, in this example a VHDL source
code, are specified at the last stage of the development process. You will utilize this technique to
build a state machine.
To draw an empty symbol, called FUB in Active-HDL, click the Fub
button on the toolbar.
Now, draw a rectangle by clicking the left mouse button and drag it diagonally downwards
releasing the left mouse button as shown in the figure.

Switch to the Select mode (click the arrow icon on the toolbar or press the Escape key), rightclick the Fub and choose the Properties option from the pop-up menu.
In the Fub Properties window change fub name into control and accept changes with OK button.

53. Notice that the drawn symbol contains no pins. In the next few steps you will build the sources
for the symbol placed on the schematic. Right-click the symbol and choose the Push option from
the pop-up menu.

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VHDL Entry and Simulation Tutorial

Control State Machine


54. As a result the Create New Implementation window appears. Choose the State Diagram
icon and type the control name in the Name filed. Accept entries with the OK button.

55. This will attach a newly created control.asf file to the current design.

56. In the first step, create the state diagram ports. To place the terminals in the diagram click the
Input Port
button located in the main toolbar. Place three input terminals in the upper
declarative part of state diagram as shown in the figure.

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VHDL Entry Tutorial

57. Change the Port1, Port2, Port3 terminal names by double-clicking their labels (you have to
switch to the Select mode first) to start, reset, f_pattern respectively. Save the settings using the
Ctrl + S keyboard shortcut.

58. Similarly, to input ports define the output terminals. To do this, use the Output Port
button and place two output ports.

59. The names of the terminals should be changed. Switch to the Select mode, double click the
port1 and port2 labels and change them to end_reset and gate, respectively.

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VHDL Entry and Simulation Tutorial

60. The f_pattern input terminal serves as a clocking signal. To change the port mode to clock,
right-click its name and choose the Properties option from the pop-up menu.

61. In the Port Properties window, check the Clock box and accept changes with the OK button.

As a result, the f_pattern signal symbol contains a small waveform.

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VHDL Entry Tutorial


62. The automaton will be comprised of three states. To place the state on the diagram use the
State

button. Place the three states on the diagram.

63. To draw the transitions between states use the Transition


button. To draw a transition,
click within one state and drag the line dropping the transition within another state. Draw the
transitions as shown in the figure.
NOTE: To draw a transition from a state to itself, click the state once and then move slightly
within the state and click once again. This will create a smooth loop transition.

64. The drawn diagram requires a reset signal. This is accomplished with the Reset
button
located in the toolbar. Click this button and place the reset symbol next to the S1 state. Now
connect it with the state.

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VHDL Entry and Simulation Tutorial

65. At this point, change the names of the created states. Double-click the S1, S2 and S3 labels
and change them to idle, open_gate and end_cycle respectively as shown in the figure.

66. The only thing left is to define the conditions of the states transitions. To place the conditions
on the diagram, click the Condition
button. Now click the transition for which the condition
needs to be set. Type the condition in the box that appears on the transition. Particular transition
conditions should be set as shown in the figure.

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VHDL Entry Tutorial

67. The last step in drawing the state diagram is to set the output values in each state. This is
achieved with the State Action
button located in the toolbar. Click it once and drag the line
with a small circle at the end of the line dropping the small circle over the selected state. Now
type the assignments in the active box.

All output value assignments are shown in the following figure.

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VHDL Entry and Simulation Tutorial

68. This is the end of the drawing stage. Now you will set the reset signal settings. Right-click the
empty space in the diagram and choose the Properties option from the pop-up menu.

69. In the Machine Properties window, switch to the Reset tab and change the signal type from
Synchronous to Asynchronous in the Type field.

Accept the change with the OK button. Save the diagram by using the Ctrl+S keyboard shortcut.
A compilation of the file can be performed with the Compile
button located in the Active-HDL
toolbar. Successful compilation is reported in the Console window and marked in the Design
Browser.

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VHDL Entry Tutorial


70. Switch to the Block Diagram Editor window clicking the freq_top.bde tab. Since the symbol
contains no ports, you will need to compare it with its contents to apply latest changes. Right-click
the symbol and choose the Compare Symbol with Contents option from the pop-up menu. If
prompted, choose Yes and save the diagram.

71. Check the Update symbol radio button and close the Compare Interfaces window clicking
the OK button.

72. The symbol is automatically updated and terminals are created according to the state
machine ports declared for the automaton. Now, draw a new fub to the right of the existing
symbol.

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VHDL Entry and Simulation Tutorial

73. This time you will attach an existing file to the symbol. Switch to the Select mode, right-click
the fub and choose the Push option from the pop-up menu.

74. In the Create New Implementation window, select the Block Diagram icon and navigate to
the existing file using the Browse button. You do not need to provide a name for the fub, since it
will be automatically assigned during the push operation.

Click the OK button.

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VHDL Entry Tutorial


75. In the Open window, select the cnt_bcd.bde file and accept the choice with the Open button.
Next, choose OK.

Active-HDL will prompt you with a message confirming that such a file already exists and will ask
you whether to use the existing file or overwrite it. Choose the Use existing file option and click
the OK button.

This will automatically attach the cnt_bcd.bde file to the fub and appropriate pins will be created
according to the file contents.

76. Now place the LED display decoder symbols on the schematic. Click the Show Symbol
toolbox

button located in the toolbar.

77. Select the hex2led symbol and drag it onto the schematic. Repeat this operation four times
and arrange the symbols as shown in the figure.
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VHDL Entry and Simulation Tutorial

78. At this stage, draw the connections between the symbols and terminals. Start with drawing
buses connecting decoders with output terminals and the counter symbol. Click the Bus
button and draw the connection as in the figure.

79. The connection between the state machine and the counter is done by a wire. Click the Wire
button and drag the wire between the symbols.

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VHDL Entry Tutorial

80. The last step requires you to create the connections between the symbols and input
terminals. After selecting the
button, draw the lines between the terminals and the symbols
as shown in the figure. Save such created diagram using the Ctrl + S keyboard shortcut.

81. The prepared project is ready for compilation. Compile it using the Compile
or choose the
Compile option from the pop-up menu in the Design Browser window. As usual, a successful
compilation is marked by a green check mark.

Simulation
1. The frequency meter unit is comprised of several components implemented previously and
connected in the Block Diagram Editor as a freq_top.bde file. So far, the Design Browser
window should contain the following files.

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Compiling the design files


2. Before you start the simulation, make sure you have compiled all design sources. To do so,
select the freq_top.bde file in the Design Browser and right-click it choosing the Compile All in
Folder option from the pop-up menu.

Setting the Top-Level


3. The next most important thing is to specify the design's entity/architecture for the functional
simulation. This pair is called in Active-HDL Top-Level.

To set the architecture as Top-Level, click the sign next to the freq_top.bde file in the Design
Browser window to expand the contents. Select the freq_top(freq_top) branch and right-click it to

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VHDL Entry Tutorial


call the pop-up menu. Choose the Set as Top-Level option and notice how the branch is
displayed in bold.
Initializing the Simulation
4. In this step, you will initialize the simulation choosing the Initialize Simulation from the
Simulation menu. The simulation initialization is indicated by an automatic change in the Design
Browser where the Structure tab is brought up to front.
5. To open the Standard Waveform Editor window, click the New Waveform
button located
in the main Active-HDL toolbar. Selecting the freq_top (Structure tab) branch in the upper part
of the Design Browser window displays the signals visible for the selected unit in the lower part
of the window.

Some of the signals were created automatically to enable communication between the design
components and have the BUS and NET prefixes.
6. After clicking the New Waveform button, a new Waveform window appears.

Adding signals
7. Add the signals by selecting them in the Design Browser window with the freq_top branch
selected.
Holding the Shift key, click the F_INPUT signal first and then click the LED_D signal. As a result
all signals located between the selected ones are highlighted as shown in the figure.

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To place the selected signals in the Waveform Editor window, drag them holding the left mouse
button and drop over the empty editor space. You should see the following Waveform Editor
contents displayed.

8. Apart from displaying simulation results as waveforms, Active-HDL allows using a tabled text
format for the produced result. For this purpose, a List window has been developed. To call it,
click the New List

button located in the toolbar.

Similarly to adding signals to the Waveform Editor window, drag them to the List window and
observe the contents.

Applying stimulators
9. Go back to the Waveform Editor window by clicking the Waveform editor 1 tab shown in the
figure.

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VHDL Entry Tutorial

Select the F_INPUT signal and by right-clicking it, choose the Stimulators... option from the popup menu. This will open the Stimulators window where you can apply predefined test vectors to
signals.

10. In the Stimulators window, select the stimulator type for the signal choosing an appropriate
one from the Type: list.

Choose the Clock stimulator for the F_INPUT signal. Accept the choice and the default clock
settings by clicking the Apply button.

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11. To set the test vectors for the remaining signals, it does not require closing the Stimulators
window. Move the window aside to see the signals in the Waveform Editor window and click the
next signal name. Choose the F_PATTERN signal and notice how the name is automatically
added to the Signals list in the Stimulators window.

The F_PATTERN signal utilizes the same Clock stimulator type. This time change the default
settings from 100 ns to 10 000 ns. To do this click the editing field with the 100 ns value displayed
and type the new 10 000 value as shown in the figure.

Accept the changes with the Apply button. This is indicated in the Stimulators window by a bold
display of the signal name and a check mark next to it.
12. Similarly to the signals described before, select the Reset signal.

This time choose the Value stimulator. In the Force Value field choose '1' as the stimulator value.

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VHDL Entry Tutorial

Accept it with the Apply button.


13. The only input signal left is the Start signal. Add it to the Stimulators window.

Its value will be constant throughout the entire simulation run. As you may guess, choose the
Value as the stimulator type and select '1' as its value.

Accept settings with the Apply button. All stimulators have been applied; however leave the
Stimulators window opened.
Running simulation
14. There are five Run simulation buttons located in the main Active-HDL toolbar. Notice the time
scroll-box next to them used with the Run for
button. There is a 100 ns value set that should
be changed to 10 us. To do this click the scroll-box and edit the value. The result is shown in the
following picture.

15. After changing the default value, use the Run For
button to advance the simulation by 10
us. The results are automatically displayed in the Standard Waveform Editor window.

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16. After the first simulation step, you need to change the value of the Reset signal from '1' to '0'.
Click the Reset signal in the Stimulators window and choose a new '0' value from the drop-down
list as shown in the figure.

As usual, accept changes with the Apply button and click the Close button to exit from the
window.
17. Click the Run For
button several times until you see the 40, 79, 40, 40 hexadecimal
values on the led_a, led_b, led_c and led_d outputs respectively. The LCD displays would
indicate the following numbers: 0,1,0,0 meaning that the measured frequency is 100 times
greater than the referenced one.

After switching to the List window you can observe the simulation results in a tabled format. To
do this click the List tab and you should see similar results as shown in the figure.

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Saving simulation results


18. You can save the simulation results as a waveform in a native .awf format choosing the Save
option from the File menu. You can also export the results to a VHDL .vhs file, to enable later
automatic testbench generation. Switch back to the waveform window and choose the Export ->
Waveforms option from the File menu.
In the Save As window, type the vectors name and save the file by clicking the Save button.

19. Close the waveform window.

Creating Testbenches
1. The simulation results exported from the Waveform Editor will serve as test vectors for the
testbench automatically created by the wizard. Expand the freq_top.bde file branch to display the
freq_top(freq_top) entity/architecture pair and select it. Next, right-click it to display the pop-up
menu and choose the Generate Testbench option to start the Testbench wizard.

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2. This will call the Testbench Generation Wizard shown below.

The type of the generated testbench should be set as Single Process. Advance to the next
window by clicking the Next button.
3. In the next window, check the Test vectors from file check box and click the Browse button.

4. In the Files of type: field change the format to stimulus files (*.vhs) and select the exported
vectors.vhs file. After selecting the file click the Open button.

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5. Active-HDL will automatically search the file for signals and adds them to the Signals found in
file: window. Notice that these signals match the tested model signals. Otherwise an error
message is displayed.

Click the Next button.


6. The next wizard window displays the entity and architecture names for the generated
testbench files as well as the folder name containing these files.

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Accept the default settings and advance to the next window by clicking the Next button.
7. The next window lets you create a timing configuration file for timing simulation. Since you will
not use it, leave this check box unchecked.

Finish the testbench generation process by clicking the Finish button.


8. As you may notice, the Design Browser window displays a new TestBench folder with two files:

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freq_top_TB.vhd - the testbench file


freq_top_TB_runtest.do - macro command file for automatic testbench execution

VHDL Entry Tutorial

9. Select the freq_top_TB_runtest.do file and right-clicking it, choose the Execute option to start
the automatic compilation and simulation.

10. During the simulation a new Waveform Editor window is opened where the signals are
automatically attached and the results are updated accordingly.

Debugging

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Active-HDL offers several useful tools designed for efficient line-by-line code debugging and
simulation results tracing.

VHDL Code Debugging


1. Before starting the debugging session you need to restart the simulation using the Restart
Simulation option from the Simulation menu.
Active-HDL offers step-by-step code debugging of VHDL source code with signal and code
breakpoints enabled. You can advance the simulation until a breakpoint is encountered using the
Trace

buttons located in the main toolbar.

In this tutorial you will set a breakpoint inside the description of a BCD counter. Go to the
CNT_4B.VHD file by double-clicking the file name in the Design Browser window. If the file is
already opened you can click the corresponding tab in the HDL Editor. In the counter description,
find the following line responsible for enabling the counter:
if ENABLE = '1' then
Place the insertion point there by clicking with the mouse cursor. Right-click this line and choose
the Toggle Breakpoint option from the pop-up menu.

After setting the breakpoint in the selected line a


mark is placed on the left side. You can
toggle any breakpoint using the F9 keyboard key or by choosing the Disable Breakpoint option
from the pop-up menu. The HDL Editor with a breakpoint set is shown below.

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2. To observe the values of selected signals, use the Watch window. To open the Watch
window, click the View Watch Window
button located in the main toolbar. Clicking this button
opens an empty Watch window as shown in the figure.

3. In the next step you will add the Qint signal of all counters used in the CNT_BCD.VHD file. To
do this, expand the freq_top_tb branch in the Structure tab of Design Browser as shown in the
figure.

After selecting the U1: cnt_4b unit, the first BCD counter instantiation signals appear in the lower
part of the window. As you can see, there is a Qint signal displayed, which should be dragged to
the Watch window. You should add the Qint signal of the following instances U2: cnt_4b, U3:
cnt_4b i U4: cnt_4b dragging them from the Design Browser to the Watch window. This way all
Qint signals of the mod 10000 counter have been added to the Watch window. The results
should be as shown in the figure below.

Initially, all signals have the U value, however during the simulation they will be assigned new
values. To observe the state of executed processes, open the Processes window by choosing the
Processes option from the View menu. The following window appears.

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4. Start the simulation by clicking the Run For


button several times. Since the breakpoint has
been set in the counter's code, the simulation will be stopped upon reaching the selected line.
The line with the breakpoint is highlighted in yellow. To execute the code line-by-line, use the
button located in the HDL Editor toolbar. Each click on the Trace button executes
Trace into
a single code line. You can use the F7 keyboard key to achieve the same result.

5. Repetitive Run For


Watch window.

button uses are reflected by value changes of the Qint signals in the

As you may notice, apart from the current signal values, previous values and event times are
displayed as well. The Processes window reflects the changes in the behavior of the counter.
The processes displayed can have either Wait or Ready status.

6. To trace the signal changes you can use the Design Browser window. Switch to the Structure
tab and select the required design branch. For example to watch the HEX-to-LED display
decoder signals expand the freq_top_tb tree and select the U4: hex2led branch.

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The lower part of the window displays the decoder signals with their current values.
7. You can check the current value of the signal in the HDL Editor after resting the cursor on any
signal name appearing in the code. To check the Qint signal value, move the cursor over the Qint
signal name as shown in the figure.

Tracing Signal Changes in Block Diagram Editor


1. Apart from many editing features, the Block Diagram Editor interactively displays the current
values in the schematic. Before you take advantage of this convenient feature you need to
remove the breakpoint set in the counter's code.
To do so, go back to the cnt_4b.vhd file and locate the line with the breakpoint. This line as you
may remember, is indicated with a
mark. Place the cursor somewhere in the line and press
the F9 keyboard key. This will remove the breakpoint from the line.
2. To observe signal changes in Block Diagram Editor, switch to the freq_top.bd file. You can
achieve this by clicking the freq_top.bde file tab or by double-clicking the same file name in the
Design Browser window. Moreover, restart the simulation by choosing the Restart Simulation
option from the Simulation menu. The Block Diagram contents are shown in the figure.

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As you can see, all initial signal values are U.


3. Press the Run For
toolbar button twice and observe how the values of all counter
instances are interactively changed.
Exemplary contents of the Block Diagram Editor after repetitive Run For
shown in the figure below.

button uses are

As you can see, the values are updated immediately.


NOTE: To toggle the display of values in Block Diagram Editor, use the Probes/Probes Visible
option from the Diagram menu.
State Diagram Debugging
Active-HDL offers interactively animated state diagram debugging in the State Diagram Editor.
This is achieved by advancing the simulation until a state transition is encountered.
1. To trace the value changes in the subsequent states, switch to the previously described
control.asf diagram. There are two ways to open the control.asf file. Either click the corresponding
tab or double-click the file name in Design Browser. As usual restart the simulation using the
Restart Simulation command from the Simulation menu.
The state diagram contents after simulation restart are shown in the following picture.

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The state highlighted with a yellow background represents the state in which the state machine is
initiated.
2. Open the Watch window by clicking the View Watch Window
button located in the
toolbar. You may also choose the Watch option from the View menu.
With the Structure tab active in the Design Browser window, expand the freq_top_tb branch as
shown in the next figure.

Select the following Sreg0, gate and end_reset signals and drag them to the Watch window.
The Watch window should look as follows.

The initial values of the gate and end_reset signals are U, and the machine is initiated in the
end_cycle state.

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NOTE: The initial state set after the initialization of simulation can be specified by using the FSM |
View\Sort Objects option.
3. To initialize the simulation and reset the state diagram, click the Trace over Transition
button located in the State Diagram toolbar. This is indicated by a transition to the Idle state
highlighted with a yellow background and Sreg0 signal change in the Watch window.

Notice the Sreg0 signal change from end_cycle to idle in the Watch window. Changes on the
signals are marked by a red exclamation mark, which indicates that an event occurred on the
selected object.

The subsequent Trace over Transition


button advances the simulation till the next
transitions between the state diagram states occur. This is immediately reflected in the Watch
window by a corresponding signal update.
Control Flow in Data Flow window
The Data Flow window is a graphical tool representing the signal data path flowing through active
processes during the simulation run.
1. First, choose the Restart Simulation option from the Simulation menu. Next, to open the
Data Flow window, switch to the Structure tab of the Design Browser window, expand the UUT's
structure, select the Stimulus process and choose option View In Data Flow from the context
menu.. As a result the Data Flow window will be opened as it is shown in the figure.

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The Stimulus process displayed in the window represents the forcing signals found in the
Testbench file. Note that since testbench process does not have input signals no input pins are
displayed for the Stimulus process.
button located in the main Active-HDL toolbar and observe the signal
2. Click the Run For
changes in the Stimulus process forced by a testbench. The Data Flow window contents can look
as follows.

3. Click the reset signal. This will trace the signal path and display the following contents.

The Stimulus process reset signal is read by the state diagram machine responsible for the
behavior of the controller described in the control.asf file.
4. Select the UUT/U1/Sreg0_machine branch to follow the signal path.

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As it was mentioned before, the reset signal is attached to the reset input of the Control
(Sreg0_machine) state diagram. There are three outputs updated in the Control diagram. As it is
shown in the picture, you can observe the latest values.
5. Now, click the gate signal to see what processes depend on its values.

The picture displays two processes reading the gate value shown on the right side of the data
flow. Each branch displayed in the window is responsible for:

UUT/U2/U1/line__32 - assigning the gate value to the ENABLE port of the BCD counter.
UUT/U2/U5/line__26 - feeding one of the AND gate inputs.

Now, click the UUT/U2/U1/line__32 branch.

The process represented in the figure above pertains to the BCD counter with a single Qint
output. The gate signal from the previous picture is connected to the Enable input.
6. Click the UUT/U2/U1/Qint signal and follow the path change in the Data Flow window.

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7. Next, click the UUT/U2/U1/line__49 branch.

As you can see, the Qint signal feeds the FULL port in the Cnt_4b.vhd file describing a 4-bit
counter. To follow the data path further, repeat the steps 1 through 7 until you reach the stage
where no output signals or ports are present.
Thank You for using Active-HDL!

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