Georgia Institute of Technology

School of Electrical and Computer Engineering

Solutions Problem Set 3

ECE-4430

Fall 2011

VDD

1. For the voltage divider below (ignore channel length modulation):

(a) Calculate Vref.
Vref
(b) Calculate SV DD
.
(c) Calculate TC(Vref).

RD
Vref
R1

(a)
I = I D1 +

Vref
R1 + R2

, I D1

M1

1
W
2
= n C ox (VGS 1 VThN )
2
L 1

W
= 1

R1

VGS1 = VGS1 I D1 = 1
V ref = 1 +
2
R2

= 1+ 1

R2

R2

n C ox

VDD Vref

V Vref
I = DD
RD

RD

V ref

V
ThN

= 1 ref VThN
2
R1 + R2

Vref

(1)

By solving (1), Vref can be found with respect to other circuit parameters.
To simplify (1), if R1 + R2 is large, then
VDD Vref
RD
VDD Vref
RD

V
1 ref VThN
2

2
1 Vref
2

+
V

V
V
ThN
ref
ThN
2

2 2
2 2
2
VDD
V = Vref2 2VThNVref + 2VThN
1RD
1RD ref

2

Vref + 2 VThN
Vref2 2 VThN
VDD
1RD
1RD

2b

V ref = b b 2 c

ref
(b) S VDD
=

V DD V ref
V ref V DD

Vref Vref
c
=

VDD
c VDD

b is independent of VDD

c
2 2
=
VDD 1R

Vref
VDD 2 2
1
VDD 2
1
1
Vref
=
SVDD =

2
2
2
c
Vref 1R 2 b c
Vref 1R
2 b c
b c

(c)

R
1 V ref
Vref = 1 + 1 VGS 1 = VGS 1 TC F (V ref ) =
V ref T
R2

Vref
V
1
L VDD
= GS = VThN TCVThN
2 1
2 W1 RD nCox
T
T

Using equation (20.25) in Baker Page 440.

1 2VDD 1 RD

TC F (Vref ) =
VThN TCVThN

Vref
2 1RD RD T

1 RD 1.5

T
RD T

1 .5

2. In the following wide swing cascode current source:

(a) Find the size of M3, M4, and M5 for Iout = 10A.
(b) Simulate the circuit using AMI-0.5m parameters.
(c) Sweep Vout from VSS = -2.5V to VDD = 2.5V, and draw Iout vs. Vout curve.
(d) From simulated Iout vs. Vout curve, find Rout and Vout(min).
(a)

VGS 3 = VGS1

1
I
=
I
D 3 2 D1

6
W W 1
= =
L 3 L 1 2 2.4

6
W
W
= =
L 4 L 3 2 .4
VGS 5

VDD

5 A

5 A
I out

1 W
1 6
W
= 2V + VThN = =

L 5 4 L 3 4 2 .4

(W L) = 12 2.4

But Wmin = 3m So we need to increase L5

M4

M5

3
W
=
L 5 4 .8

M2

(W L) = 12 2.4

(b) Simulation:

M3
VSS

M1

(c) Simulation

It can be seen that the hand calculations in this case are about 47% off the target value! Why?
Do you remember what we said in class about the effect of lateral diffusion and oxide encroachment in currentscaling mirrors, which do not have the same W/L on both sides?
One way to get around this problem is to change (W/L)3 to compensate for these effects between M3 and M1:

(d) Original value I out = 14.64 A , Rout =

1
= 38M
26.32 10 9

6
7 .8
W
Change from
to
to get I out 10 A
2 .4 2 .4
L 3

I out 9.85A , R out =

7 .8
W
I out 9.85A
=
L 3 2 .4

1
= 167 M , Vout (min ) = 2.1V VSS + 2V
5.97 10 9

But a better way to scale M3 current by a factor of 2 is to replace M1 with two NMOS transistors in parallel,
with the same size as M3 in order to scale ID3 with by an exact factor of 2.

3. In the following current source (a different version of regulated cascode) calculate Rout and Vout(min) when:
A = Gain of the OpAmp
(a) M1 and M2 are in saturation.

Rout

(b) M1 is in triode and M2 is in saturation.

(a)

Vout

Bias 2

Small Signal Model

M2

Since Bias1 and Bias2 are DC voltages, both will be

grounded in the AC model.
Vgs 2 = AVd 1 Vd 1 = I out rds1 I out = g m 2Vgs 2 +

Vout Vd 1
(1)
rds 2

Bias1

M1

Vgs 2 = Ards I out

I out
Bias 2

AV d 1

V gs1

G1

g m 2V gs 2
rds 2

V d1

Bias1

I out

rds1

Substituting Vgs 2 and Vd 1 in (1)

I out = g m 2 Ards I out +

Vout I out rds1

rds 2

Vout
r
= I out 1 + g m 2 Ards1 + ds1 = I out (2 + g m 2 Ards1 )
rds 2
rds 2

ro = rds1 rds 2

rds1
1
rds 2

Rout Ag m 2 rds1rds 2 = Ag m 2ro2

The OpAmp will try to keep VD1 = VS 2 = VBias 2 due to its high gain ( A >>1) and negative feedback.
For M 1 to be in saturation, VD1 = VBias 2 > V 200mV
The OpAmp provides enough gate voltage VG 2 to keep M 2 in saturation, provided that VDS 2 > V
Therefore: Vout (min) = VBias 2 + V = 2V 400mV

(b) M 1 in triode It works as a variable resistor, which resistance is controlled by Bias1

I out

I out
+

AV d 1

g m 2V gs 2

V gs1

rds 2
V d1

M 1

I out
R1

Bias1

V
W
I D1 = n C ox V GS1 VThN DS1 V DS1
2
L 1

I D1
W
= nCox (VGS1 VThN VDS1 ) = 1 / R1
VDS1
L 1
VGS1 = VBias1

VDS1 = VBias 2 (Due to the OpAmp function)

W
R1 = nCox (VBias1 VBias 2 VThN )
L 1

Now the same calculations that we did for part (a) will result in:
Rout = rds 2 (2 + g m 2 AR1 ) Ag m 2 rds 2 R1

In this circuit I out =

VDS1 VBias 2
=
, and R1 is controlled by VBias1 and
R1
R1

W

L 1

Therefore, VBias 2 can be chosen very small, even close to 0V

Therefore the only transistor that has to stay in saturation is M 2 : VDS 2 > V , V DS1 > 0V
Vout (min) = 0 + V 200mV

4. (a) Design a regulated cascode current sink of 1A in AMI-0.5m process (use hand calculation and the
topology shown in Fig. Ex20.8 of Baker in page 454). VDD = 5V, VSS = 0
(b) Simulate the circuit and fine tune the resistor (R) to get Iout = 1A.
(c) Sweep Vout from 0 to 5V and draw Iout vs. Vout curve. Find Rout and Vout(min).
out
(d) For Vout = 2.5V, sweep VDD from 0 to 5V and draw Iout vs. VDD curve. Find SVI DD
.

(a)
Since this is a design problem we can start with any ratio transistor size and change it later if needed.
7

12
W
Assuming =
L 1 2.4
VGS 1 =

2 I D1
+ VThN
W
nCox
L 1

I D1 = 1A ,

R1 =

1
10 6
n C ox = 57.1 A 2 , VThN = 0.74V VGS1 =
V
2
57.110 6 12

+ 0.74 = 0.06 + 0.74 0.8V

2 .4

VDD VGS 1 5 0.8

=
= 4 .2 M
I D1
10 6

This resistor value is too large for an IC design, unless it is an N-well resistor or if you have access to highresistive poly.

W
W
= = 12 2.4
L 2 5 L 1
1
n C ox
57.1
2
=
= 3.12 3 choose PMOS transistors 3 times wider than NMOS to provide the same g m
1
18.3
p C ox
2
(this is not necessary, but it gives a rough size for PMOS transistors)

48
W W
= =
L 6 L 7 2 .4
If supply level is small, M 6 and M 7 should be as wide as possible to reduce VGS 6 & VGS 7
(b) Simulation: R = 4.2 M

(c) Vout (0V ~ 5V ) : Vout (min) 0.8V VTHn + V , Rout > 200G!

(d) Vout = 2.5V , VDD 0V ~ 5V

10

Since the original Iref is not generated by a self-bias, supply independent reference generator, Iout is very
out
sensitive to VDD variations and SVI DD
1.

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