Release 14.7 - xst P.

20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.15 secs
--> Parameter xsthdpdir set to xst

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.16 secs
--> Reading design: xy_routing_for_mesh_topology.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report

=========================================================================
*
Synthesis Options Summary
*
=========================================================================
---- Source Parameters
Input File Name
: "xy_routing_for_mesh_topology.prj"
Ignore Synthesis Constraint File
: NO
---- Target Parameters
Output File Name
Output Format
Target Device

: "xy_routing_for_mesh_topology"
: NGC
: xc7a100t-3-csg324

---- Source Options

Top Module Name
Automatic FSM Extraction
FSM Encoding Algorithm
Safe Implementation
FSM Style
RAM Extraction
RAM Style
ROM Extraction
Shift Register Extraction
ROM Style

:
:
:
:
:
:
:
:
:
:

xy_routing_for_mesh_topology
YES
Auto
No
LUT
Yes
Auto
Yes
YES
Auto

Resource Sharing
Asynchronous To Synchronous
Shift Register Minimum Size
Use DSP Block
Automatic Register Balancing

:
:
:
:
:

YES
NO
2
Auto
No

---- Target Options

LUT Combining
Reduce Control Sets
Add IO Buffers
Global Maximum Fanout
Add Generic Clock Buffer(BUFG)
Register Duplication
Optimize Instantiated Primitives
Use Clock Enable
Use Synchronous Set
Use Synchronous Reset
Pack IO Registers into IOBs
Equivalent register Removal

:
:
:
:
:
:
:
:
:
:
:
:

Auto
Auto
YES
100000
32
YES
NO
Auto
Auto
Auto
Auto
YES

---- General Options

Optimization Goal
Optimization Effort
Power Reduction
Keep Hierarchy
Netlist Hierarchy
RTL Output
Global Optimization
Read Cores
Write Timing Constraints
Cross Clock Analysis
Hierarchy Separator
Bus Delimiter
Case Specifier
Slice Utilization Ratio
BRAM Utilization Ratio
DSP48 Utilization Ratio
Auto BRAM Packing
Slice Utilization Ratio Delta

:
:
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:
:
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:

Speed
1
NO
No
As_Optimized
Yes
AllClockNets
YES
NO
NO
/
<>
Maintain
100
100
100
NO
5

=========================================================================

=========================================================================
*
HDL Parsing
*
=========================================================================
Analyzing Verilog file "D:\NoCrouting\xy_routing_for_mesh_topology.v" into library work
Parsing module <xy_routing_for_mesh_topology>.
=========================================================================
*
HDL Elaboration
*
=========================================================================
Elaborating module <xy_routing_for_mesh_topology>.
=========================================================================
*
HDL Synthesis
*
=========================================================================
Synthesizing Unit <xy_routing_for_mesh_topology>.
Related source file is "D:\NoCrouting\xy_routing_for_mesh_topology.v".

PORT_NUM = 5
X_NODE_NUM = 4
Y_NODE_NUM = 3
X_NODE_NUM_WIDTH = 2
Y_NODE_NUM_WIDTH = 2
PORT_NUM_BCD_WIDTH = 3
PORT_SEL_WIDTH = 4
Found 3-bit subtractor for signal <xdiff> created at line 45.
Found 3-bit subtractor for signal <ydiff> created at line 46.
Found 32-bit comparator greater for signal <xdiff[2]_GND_1_o_LessThan_8_o> created at
line 53
Found 32-bit comparator greater for signal <GND_1_o_xdiff[2]_LessThan_9_o> created at
line 54
Found 32-bit comparator greater for signal <ydiff[2]_GND_1_o_LessThan_10_o> created at
line 56
Found 32-bit comparator greater for signal <GND_1_o_ydiff[2]_LessThan_11_o> created at
line 57
Summary:
inferred
2 Adder/Subtractor(s).
inferred
4 Comparator(s).
inferred
3 Multiplexer(s).
Unit <xy_routing_for_mesh_topology> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors
3-bit subtractor
# Comparators
32-bit comparator greater
# Multiplexers
3-bit 2-to-1 multiplexer

:
:
:
:
:
:

2
2
4
4
3
3

=========================================================================
=========================================================================
*
Advanced HDL Synthesis
*
=========================================================================

=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors
3-bit subtractor
# Comparators
32-bit comparator greater
# Multiplexers
3-bit 2-to-1 multiplexer

:
:
:
:
:
:

2
2
4
4
3
3

=========================================================================
=========================================================================
*
Low Level Synthesis
*
=========================================================================
Optimizing unit <xy_routing_for_mesh_topology> ...
Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block xy_routing_for_mesh_topology, actual
ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
*
Partition Report
*
=========================================================================
Partition Implementation Status
------------------------------No Partitions were found in this design.
------------------------------=========================================================================
*
Design Summary
*
=========================================================================
Top Level Output File Name

: xy_routing_for_mesh_topology.ngc

Primitive and Black Box Usage:

-----------------------------# BELS
#
LUT2
#
LUT3
#
LUT4
#
LUT6
# IO Buffers
#
IBUF
#
OBUF

:
:
:
:
:
:
:
:

7
3
1
1
2
11
8
3

Device utilization summary:

--------------------------Selected Device : 7a100tcsg324-3

Slice Logic Utilization:

Number of Slice LUTs:
Number used as Logic:

7
7

out of
out of

63400
63400

0%
0%

Slice Logic Distribution:

Number of LUT Flip Flop pairs used:
Number with an unused Flip Flop:
Number with an unused LUT:
Number of fully used LUT-FF pairs:
Number of unique control sets:

7
7
0
0
0

out of
out of
out of

7
7
7

100%
0%
0%

out of

210

5%

IO Utilization:
Number of IOs:
Number of bonded IOBs:

11
11

Specific Feature Utilization:

--------------------------Partition Resource Summary:
--------------------------No Partitions were found in this design.
---------------------------

=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
-----------------No clock signals found in this design
Asynchronous Control Signals Information:
---------------------------------------No asynchronous control signals found in this design
Timing Summary:
--------------Speed Grade: -3
Minimum
Minimum
Maximum
Maximum

period: No path found

input arrival time before clock: No path found
output required time after clock: No path found
combinational path delay: 1.557ns

Timing Details:
--------------All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 21 / 3
------------------------------------------------------------------------Delay:
1.557ns (Levels of Logic = 4)
Source:
dest_x_node_in<0> (PAD)
Destination:
port_num_out<2> (PAD)
Data Path: dest_x_node_in<0> to port_num_out<2>
Gate
Net
Cell:in->out
fanout
Delay
Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
3
0.001
0.389 dest_x_node_in_0_IBUF (dest_x_node_in_0_IBUF)
LUT2:I0->O
1
0.097
0.693 Msub_xdiff_lut<0>1 (Msub_xdiff_lut<0>)
LUT6:I0->O
1
0.097
0.279 Mmux_port_num_out31 (port_num_out_2_OBUF)
OBUF:I->O
0.000
port_num_out_2_OBUF (port_num_out<2>)
---------------------------------------Total
1.557ns (0.195ns logic, 1.362ns route)
(12.5% logic, 87.5% route)
=========================================================================

Cross Clock Domains Report:

-------------------------=========================================================================

Total REAL time to Xst completion: 15.00 secs

Total CPU time to Xst completion: 15.43 secs
-->
Total memory usage is 415236 kilobytes
Number of errors
:
Number of warnings :
Number of infos
:

0 (
0 (
0 (

0 filtered)
0 filtered)
0 filtered)