CONTENT

1.0

INTERNAL VERIFICATION

-2-

1.1

Definition

-2-

1.2

Internal Verification policy

-2-

2.0

SENIOR MANAGEMENT

-3-

3.0

SENIOR INTERNAL VERIFIER

-3-

4.0

THE INTERNAL VERIFIER ROLE

-3-

5.0

ASSIGNMENT BRIEFS

-4-

5.1 Timing

-4-

5.2 Planning

-4-

5.3 IV Process: Assignment Briefs

-5-

5.4 Feedback to the writer

-6-

ASSESSMENT DECISIONS

-7-

6.1 Timing

-7-

6.2 Planning

-7-

6.3 IV Process: Assessment Decisions

-8-

6.4 Feedback to the Assessor

-9-

6.0

7.0

8.0

SAMPLING

- 10 -

7.1

Criteria

- 10 -

7.2

Storage

- 10 -

APPENDIX

- 11 -

Appendix 1 - Front Assessment Cover

Appendix 2 - Learning Outcome Criteria Matrix Jul-Dec 2015
Appendix 3 - Internal Verification Checklist
Appendix 5 - Assignment Brief Form
Appendix 6 - Assessment Decision Form

- 12 - 13 - 14 - 15 - 16 -

KOLEJ KEMAHIRAN TINGGI MARA PETALING JAYA

INTERNAL VERIFICATION

1.0 INTERNAL VERIFICATION

1.1

Definition:
A system of quality checks made by a group of Internal Verifier (IV) in this
centre to ensure that asiignments have been written correctly and the
assessment decisions are accurate.

It is a recorded discussion between two or more professionals to ensure

accuracy, fairness, consistency and quality of assessment. It does not
involve the learner.
1.2

Policy:

To ensure that the internal verification is valid, reliable and covers

all assessors and programme activity.

To ensure that the internal verification procedure is open, fair and

free from bias.

To ensure that there is accurate and detailed recording of internal

verification decisions.

In order to do this, the centre will;

Ensure that all assessment instruments are verified as fit for

purpose.

Verify an appropriate structured sample of Assessor work from the

programme to ensure centre programme conforms to MQA
standard and BTEC requirement.

Plan an annual internal verification schedule, linked to assignments

plans.

Define, maintain and support effective internal verification roles.

Ensure that examination unit officer will maintain secure records of

all internal verification procedures.

Promote internal verifications as a development process between

staff.
-2-

Provide standardized internal verification to enhance future

assessment practice.

Key Roles in IV Process:

SENIOR MANAGEMENT
SENIOR INTERNAL VERIFIER
INTERNAL VERIFIER
ASSESSOR

2.0

SENIOR MANAGEMENT

Senior management coordinates the internal verification process and it is

very important for the senior management to get involve in each and
every process.

3.0

4.0

SENIOR INTERNAL VERIFIER

Plans and coordinates assessment and IV for a programme.

Ensures assessors are briefed on IV process

Checks and monitors IV activity

Supports and develops Internal Verifiers

THE INTERNAL VERIFIER ROLE

4.1

The internal verifier in this centre must have:

Knowledge and understanding of the BTEC programme area or

sector.

Experience of BTEC assessment requirements.

Course specific knowledge

Appropriate knowledge about the course

-3-

4.2

The internal verifier is responsible to undertake verification of the

following during the main stages of BTEC delivery:

4.3

When assignments are written

When assignment decisions are made

The internal verifier cannot internally verify their assignments or their own
assessment decisions.

5.0

ASSIGNMENT BRIEFS
5.1 Timing:
5.1.1 Assignments should be internally verified before they are issued to
learners. If any remedial action is identified by the internal verifier,
this should be carried out by the Assessor prior to issue. This will
ensure the assignment is fit for purpose and that:

The tasks and evidence will allow the learner to address the
targeted criteria

It is written in a clear and accessible language

The learners role and tasks are vocationally relevant and

appropriate to the level of qualification

Equal opportunities are incorporated

5.2 Planning:
5.2.1 Assignment briefs are often written during the planning and
preparation stage of a programme. Time should be allowed for
internal verification to take place before the assignments are given
to learners. Resources needed to carry out internal verification
include:

The unit specification outlining the unit content and grading

criteria.

The assignment

The internal verification form for assignment (A template is

available on the Edexcel website, although use of this is not
mandatory).
-4-

5.3 IV Process: Assignment Briefs

Start

Assessor prepares the question

and answer scheme

Submit to SIV

IV give
pointers on
what can
be done to
improve
the
assignment

IV Team verification

YES

The form must be

signed and dated
by the assessor
and IV for record.

Remedial action

NO
Verification by SIV and approved
by SM

Exam unit

Distribution

END

Figure 1: Assignment Briefs Flowchart

-5-

Assessment/assignment
ready a week before
distribution

5.4 Feedback to the Writer:

5.4.1 The writer of the assignment is often the Assessor. The outcome of
internal verification should be recorded on the form. The form is
part of the audit trail leading to certification. The form must be
signed and dated by the Assessor and the Internal Verifier.
5.4.2 Rather than just ticking the boxes, the feedback section on the
form should be used. A rigorous Internal Verifier will give pointers
on what can be done to improve the assessment process.
5.4.3 if action is identified by the Internal Verifier, the Assessor should
complete this and return it to the Internal Verifier for final sign off.
Once the assignment is verified as fit for purpose, it may be issued
to the learners.

-6-

6.0

ASSESSMENT DECISIONS
6.1 Timing:
6.1.1 For internal verification of assessment decisions to take place,
some assessment of learners work should have occurred.
6.1.2 Assessment decisions should be internally verified as soon as
possible after assessment and before any of the work is returned
to the learners. This will improve the quality of assessment. If any
remedial action is identified by the Internal Verifier, this should be
carried out by the Assessor, action taken agreed with the internal
verifier and then the work can be handed back to the learners.

6.2 Planning:
6.2.1 Internal verification of assessment decisions is an integral part of
programme planning. An internal verification schedule should be
drawn up, covering every unit, every assignment and every
Assessor, with proposed dates.
6.2.1 Internal verification should be carried out throughout the year. It
should not be saved until the end of year.
6.2.3 Effective internal verification will guide and support Assessor and
feedback from the Internal Verifier will aid their skills development.

-7-

6.3 IV Process: Assessment Decisions

Start

Assessor submits assessed

learners work to IV

Quantity is
determined
based on
sampling
table
sampling

IV samples learners work

IV checks using the IV

assessment decision form

YES

Remedial action

NO
Return to assessor

Consult with learner regarding

their achievement and collect the
assessment

Consult with learner regarding

their achievement and collect the
assessment

Assessor returns the earlier

sampled learners work to IV

IV attaches the filled assessment

decision form to the learners work
and send to IV room for storage

END
Figure 2: Assessment Decisions Flowchart

-8-

6.4 Feedback to Assessor:

6.4.1 The outcome of internal verification should be recorded on the
form. The form is part of the audit trail leading to certification. The
form must be signed and dated by the Assessor and the Internal
Verifier.
6.4.2 Rather than just ticking boxes, the feedback section on the form
should be used. A rigorous Internal Verifier will give pointers on
what can be done to improve the assessment process.
6.4.3 If action is identified by the Internal Verifier, the Assessor should
complete this and return it to the Internal Verifier for final sign off.
When the Internal Verifier is satisfied that work has been assessed
accurately, the work can be handed back to the learners.

-9-

7.0 SAMPLING
7.1 Criteria:
7.1.1 During the course of the programme, every Assessor, every unit
and work from every assignment should be sampled. The sample
should be constructed in a way that rigorously assures the entire
assessment process. There is no algebraic formula to determine
sample size but a well constructed sample should consider;
The full range of assessment decisions made: work meeting
distinction criteria, merit criteria, pass criteria and no criteria
yet, should all be included in the sample if possible.
The experience of the Assessor: new inexperienced
Assessor should have more work internally verified than an
experienced Assessor.
New BTEC programmes: when a unit or programme is first
introduced, the sample should be increased.
The size of the group of learners: there is a difference to
sampling a group of 6 learners to sampling a group of 160
learners.
Issues with internal verification identified at previous
external verification visit.
7.1.2 Please remember that all assignment briefs should be internally
verified before being distributed to learners and a sample of
assessment decisions made by each Assessor needs to be
internally verified.
7.2 Storage:
7.2.1 Internal verification documents should be stored for 3 years after
certification.

- 10 -

8.0 APPENDIX
Appendix 1

KOLEJ KEMAHIRAN TINGGI MARA

PETALING JAYA
SELANGOR
Student No : EEE .

Class : .

ASSESSMENT SPECIFICATION
Programme

PEARSON BTEC LEVEL 5 HND DIPLOMA IN ELECTRONICS ENGINEERING

(QCF)

Code/Level

EEE 6134 / LEVEL 5

Unit/Course

UNIT 68 / APPLICATION OF POWER ELECTRONICS

Assessor

ANWAR BIN MOHD ABD MAHI

Assessment Type:

QUIZ / TEST / ASSIGNMENT / LAB ASSIGN / PRAC TEST/

PRESENTATION
/ LISTENING / ORAL/ RETAKE/ RESUBMISSION
Assessment No. :

1/2/3

Issued date

16 / 03 / 2015

Duration

: 3 WEEKS

Completion date :

03 / 04 / 3025

Received date

__________________
Section of unit (module objective) being assessed:
MO 2
MO 3
MO 4

: UNDERSTAND THE METHODS USED FOR AC MOTOR CONTROL

: UNDERSTAND THE METHODS USED FOR DC MOTOR CONTROL
: UNDERSTAND OTHER APPLICATIONS OF POWER ELECTRONICS

Assessment Criteria
TASK 1

2.3 Investigate an industrial AC motor controller.

TASK 2

3.3 Examine an industrial DC motor controller.

TASK 3

4.1 Compare the principles of three other applications of power

electronics
4.2 Investigate an area of application for each of the three applications.

TASK 4

A pass is achieved by meeting all the above assessment criteria

- 11 -

Appendix 2
Learning Outcome Criteria Matrix Jul-Dec 2015
1

UNIT

UNIT

INTERNAL

LEVEL

Issue

Submission

ASSESSORS

SEMESTER

CODE

UNIT 2
(EES 1514)

TITLE

ENGINEERING
SCIENCE

VERIFIER

(QCF)

Abdul Mutalib

Date

NO.OF
.ASSESSMENT

Date

HEALTH,SAFETY AND
RISK ASSESSMENT IN
ENGINEERING

Mohd Hafif

ANALOGUE AND
DIGITAL ELECTRONICS

Hasrulnizam

EMT 1013

UNIT 64
(EEE 3154)

UNIT 39
(EEE 2224)

Norhayati/
Norma

A1

AT

A2

AL

A3

AT

1.1

1.2

A1

AS

A2

AS

A3

AT

A1

AT + QZ

A2

AS +PT

A3

AT

Mohd Fauzi

ELECTRICAL AND
ELECTRONIC
MEASUREMENT AND
TESTING

ELECTRONIC
PRINCIPLES

Mohd Zaini

Ali Nordin
Nur Akmal/
Halimahton/
Suhaimi

A1

AT

A2

AT

A3

AT

A1

PT

A2

AL

A3

AT

Siti Norazizah

UNIT 57
(EEM 4754)

UNIT 58
(EED 3414)

TECHNICAL
MATHEMATICS

MECHATRONIC
SYSTEMS

MICROPROCESSORS
SYSTEMS

Siti Fatimah

A1

AL + AS

A2

AL

A3

AT

Noran Zahrine

A1

AT + QZ

A2

AS

A3

AT

A1

AT

A2

AT

A3

AT

Mohd Fauzi

Suhaimi

Hasrulnizam
Mohd Hafif

Norhayati/
Norma

MANAGEMENT OF
PROJECTS

Norhisyam

A1

AS + PR

A2

AS + AL

A3

AT

A1

AS + PR

A2

AL + PRO

A3

AT

A1

AS

A2

AS

A3

AT

Norma
Zuraidah

Mohd Esta
Husna

A1

AS

A2

AL

A3

AT

A1

AT + QZ

ANALOGUE AND
DIGITAL ELECTRONICS

Mohd Esta
Husna

A2

AS

A3

AT

Mohd Fauzi

EMT 1013

UNIT 22
(EEM 4744)

UNIT 8
(EEP 4614)

UNIT 55
(EEM 5734)

PROGRAMMABLE
LOGIC CONTROLLERS

ENGINEERING DESIGN

INSTRUMENTATION
AND CONTROL
PRINCIPLES

Norma
/Norhayati

Nor Kamal

Norazuin

Noran Zahrine
Mohd Fauzi

Norhayati /
Norma

Anwar

A1

AT

A2

AT

A3

AT

A1

AT

A2

AL

A3

AT

A1

AS

Abdul Mutalib

Mohd Esta
Husna

A2

AL

A3

AS, PR

A1

AS

A2

AS

A3

AT

EEE 1013

ANALOGUE AND
DIGITAL ELECTRONICS

Khairul Fadzli

EMT 1013

UNIT 22
(EEM 6744)

PROGRAMMABLE
LOGIC CONTROLLERS

Siti Adila

Hablillah

UNIT 3
(EEP 6635)

UNIT 38
(EBM 6033)

UNIT 26
(MPU 6223)

APPLICATION OF
POWER ELECTRONICS

PROJECT DESIGN,
IMPLEMENTATION AND
EVALUATION

MANAGING PEOPLE IN
ENGINEERING

EMPLOYABILITY
SKILLS

Anwar
Nur Ana

Noran Zahrine
All technical
lecturers

Mazura
Mohd Haniez

Zuliana
Norhisyam

/
1.3

AT + QZ

A2

AS

A3

AT

Mohd Fauzi

Norhayati/
Norma

Anwar

A1

AT

A2

AT

A3

AT

A1

AT

A2

AL

A3

AT

A1

AL

A2

AS

A3

AT

AS

A2

AL,PRO, PR

A3

AL,PRO, PR

Abdul Mutalib

A1

AT

A2

AS

A3

AT

A1

AS

A2

AS

A3

AT

Zuliana

Mohd Haniez

/
2.3

2.2

3.2

3.1

3.2

10

3.3

11

12

13

14

15

16

17

3.2

18

Distinction Grade

3.3

4.1

4.2

4.3

4.4

5.1

2.3

3.1

3.3

4.1

4.2

2.1

2.2

2.3

2.1

2.2

2.3

3.2

1.2

2.1

1.2

1.3

2.2

3.1

3.2

2.3

3.1

/
1.2

1.1

1.2

2.1

3.1

3.2

/
4.2

4.3

4.4

4.1

4.2

4.3

4.1

4.4

2.3

3.1

5.1

2.3

3.1

3.2

/
4.1

2.3

3.1

1.3

1.4

2.1

1.2

1.3

2.1

2.3

2.2

2.3

3.1

1.2

2.1

2.2

3.1

3.2

2.3

2.4

/
1.3

1.1

1.2

3.2

3.3

4.1

4.2

2.3

1.4

2.1

1.4

2.1

1.1

1.2

1.3

1.1

1.2

1.3

1.4

3.1

2.3

2.2

2.3

3.2

2.1

2.2

/
1.3

2.2

2.3

3.1

3.2

/
/

1.1

1.2

4.1

4.2

1.3

2.3

1.4

2.1

1.4

2.1

3.1

2.3

3.2

3.3

3.4

/
2.2

2.4

2.5

2.3

2.4

4.1

3.2

3.1

3.2

2.5

2.6

4.2

4.3

4.4

5.1

3.3

4.1

4.2

3.2

3.3

3.4

/
/

/
/

/
/

/
/

2.3

3.1

3.2

4.1

4.2

2.3

2.4

2.5

/
/

3.1

2.3

3.1

4.1

4.2

3.2

3.3

3.4

4.1

4.2

4.3

4.4

/
/

4.2

4.3

/
/

/
/

/
/

/
/
/

/
/
/

/
/

/
/
/

/
/
/

/
/

/
/

/
/

/
/
/

/
/

/
/

/
/

/
/

/
/

/
/

/
/
/

/
/

/
/

/
/

/
/

/
/

/
/

4.1

4.2

3.3

3.3

3.1

3.2

/
/

/
3.2

5.2

/
2.3

4.1

/
/
/

/
/

/
3.3

3.5

2.2

- 12 -

3.4

2.1

/
/

3.3

1.3

/
3.1

3.2

1.2

2.2

3.1

1.1

2.1

/
/
/

/
/

2.4

1.4

/
2.7

3.3

1.3

4.2

1.4

1.2

4.1

1.3

/
/

1.2

1.1

3.1

1.1

2.1

5.2

2.4

/
/

/
/

2.2

2.2

/
/

/
/

1.2

5.1

/
1.3

4.4

2.2

/
/

/
/

2.1

4.3

/
/

1.2

3.3

/
/
/

/
/

1.5

3.5

2.2

/
/

2.1

3.4

1.2

3.3

/
1.3

3.2

2.2

/
/

3.1

/
/

2.1

/
/

2.5

/
/
1.2

/
/

/
/

/
/

/
/

/
/

/
/

3.2

2.2

/
/

1.2

/
/

4.2

/
/

4.2

/
/

/
/

/
/

/
/

3.3

2.2

4.1

5.2

/
3.3

3.2

/
/

4.3

/
/

4.2

D3

D2

5.2

4.1

2.2

2.2

2.1

/
1.3

3.3

D1

4.5

3.2

4.4

/
2.1

4.3

2.4

/
4.2

/
1.3

2.2

M3

/
3.4

M2

4.3

/
4.1

/
2.1

1.2

1.1

4.2

/
/

4.1

/
3.1

1.1

Mohd Fauzi

A1

3.1

1.1
UNIT 68
(EEE 6134)

1.2

1.1
TECHNICAL
MATHEMATICS

2.1

1.2

1.1
A1

/
2.2

1.1

1.1
TECHNICAL
MATHEMATICS

2.1

1.1
EEE 1013

2.3

1.1
QUALITY ASSURANCE
AND MANAGEMENT

1.3

Anwar

Mohd Esta
Husna

2.2

/
1.2

Anwar

3
UNIT 30
(EBM 4003)

1.2

1.1
UNIT 37
(EBM 4013)

1.1
EMT 1013

1.1
ANALOGUE AND
DIGITAL ELECTRONICS

2.1

Noran Zahrine

2
EEE 1013

1.3

Mohd Fauzi

Norhayati/
Norma

Merit Grade

1.1
TECHNICAL
MATHEMATICS

M1

1.1
EEE 1013

assessment

Noran Zahrine

Learning Outcome(LO)& Assessment Criteria

1.1
UNIT 6
(EES 1524)

Method of

/
/

Appendix 3
INTERNAL VERIFICATION CHECKLIST FOR PROGRAMME PEARSON BTEC LEVEL 5
HND DIPLOMA IN ELECTRONIC ENGINEERING
UNIT
SEMESTER

LEVEL
UNITS TITLE/COURSES

CODE

ASSIGNMENT
BRIEF

A2
ASSESSMENT
DECISIONS

ASSIGNMENT
BRIEF

A3
ASSESSMENT
DECISIONS

ASSIGNMENT
BRIEFS

UNIT 6
(EES 1524)

Mohd Hafif

Mohd Fauzi

30/1
30/1

23/3
24/3

UNIT 2
(EES 1514)

ENGINEERING SCIENCE

Abdul Mutalib
Mohd Fauzi

Noran
Zahrine

29/1
30/1

16/3
25/3

EEE 1031

ANALOGUE AND DIGITAL

ELECTRONICS

Hasrulnizam
Nur Akmal /
Halimahton

Mohd Fauzi

28/1
28/1

18/3
18/3

6/3
18/3

EMT 1013

TECHNICAL
MATHEMATICS

Norhayati

Norhayati

28/1
29/1

9/3
10/3

1/3
6/3

UNIT 64
(EEE 3154)

ELECTRICAL AND
ELECTRONIC
MEASUREMENT AND
TESTING

Mohd Zaini

Noran
Zahrine

27/1
30/1

16/3
17/3

UNIT 39
(EEE 2224)

ELECTRONIC PRINCIPLES

Ali Nordin

Noran
Zahrine

26/1
27/1

16/3
17/3

2
EEE 1031

ANALOGUE AND DIGITAL

ELECTRONICS

Siti Norazizah

Mohd Fauzi

28/1
28/1

18/3
18/3

6/3
18/3

EMT 1013

TECHNICAL
MATHEMATICS

Siti Fatimah

Norhayati

28/1
29/1

9/3
10/3

1/3
6/3

UNIT 57
(EEM 4754)

MECHATRONIC SYSTEMS

Suhaimi

Anwar

28/1
30/1

16/3
18/3

2/3
18/3

UNIT 58
(EED 3414)

MICROPROCESSORS
SYSTEM

Hasrulnizam

Anwar

28/1
30/1

16/3
18/3

2/3
17/3

UNIT 57
(EBM 3013)

MANAGEMENT OF
PROJECTS

Norhisyam

Mohd Esta
Husna

28/1
29/1

18/3
18/3

4/3
5/3

UNIT 30
(EBM 4003)

QUALITY ASSURANCE
AND MANAGEMENT

Norma
Zuraidah

Azlin

27/1
28/1

10/3
10/3

23/2
9/3

A1

VERIFIER

HEALTH, SAFETY AND

RISK ASSESSMENT IN
ENGINEERING

INTERNAL
ASSESSORS

(QCF)

EEE 1031

ANALOGUE AND DIGITAL

ELECTRONICS

Mohd Esta Husna

Mohd Fauzi

28/1
28/1

18/3
18/3

6/3
18/3

EMT 1013

TECHNICAL
MATHEMATICS

Norma

Norhayati

28/1
29/1

9/3
10/3

1/3
6/3

UNIT 22
(EEM 4744)

PROGRAMMABLE LOGIC
CONTROLLERS

Nor Kamal

Anwar

27/1
30/1

31/3
31/3

23/2
16/3

UNIT 8
(EEP 4614)

ENGINEERING DESIGN

Norazuin

Abdul
Mutalib

30/1
30/1

16/3
23/3

17/2
22/2

UNIT 55
(EEM 5734)

INSTRUMENTATION AND
CONTROL PRINCIPLES

Mohd Fauzi
Noran Zahrine

Mohd Esta
Husna

27/1
28/1

18/3
17/3

23/2
16/3

EEE 1031

ANALOGUE AND DIGITAL

ELECTRONICS

Mohd Khairul

Mohd Fauzi

28/1
28/1

18/3
18/3

6/3
18/3

EMT 1013

TECHNICAL
MATHEMATICS

Siti Adila

Norhayati

28/1
29/1

9/3
10/3

1/3
6/3

UNIT 22
(EEM 6744)

PROGRAMMABLE LOGIC
CONTROLLERS

Nor Kamal

Anwar

22/1
30/1

12/3
16/3

25/2
18/3

UNIT 68
(EEE 6134)

APPLICATIONS OF POWER
ELECTRONICS

Anwar
Nur Ana

Mohd Fauzi

26/1
29/1

6/3
9/3

25/2
16/3

UNIT 3
(EEP 6635)

PROJECT DESIGN,
IMPLEMENTATION AND
EVALUATION

Noran Zahrine
All technical
lecturers

Abdul Mutalib

26/1
26/1

2/3
3/3

16/2
24/2

UNIT 26
(MPU 6223)

EMPLOYABILITY SKILLS

Zuliana
Norhisyam

Mohd Haniez

30/1
30/1

23/3
17/3

6/3
23/3

UNIT 38
(EBM 6033)

MANAGING PEOPLE IN
ENGINEERING

Mohd Haniez
Mazura

Zuliana

29/1
30/1

16/3
16/3

5/3
16/3

- 13 -

ASSESSMENT
DECISIONS

Appendix 4

MASTER ASSESSMENT DECISIONS SAMPLING MATRIX (JAN - JUN 2015)

[ To be completed every semester by Lead Internal Verifier/Internal Verifiers ]

COURSE : Pearson BTEC Level 5 HND In Electronic Engineering

SEMESTER : 6A

UNIT CODE

UNIT 22
(EEM 6744)

UNIT TITLE

PROGRAMMABLE
LOGIC
CONTROLLER

ASSESSOR

Hablillah

Anwar

Anwar

Mohd Fauzi

INTERNAL VERIFIER
ASSESSMENT

A1

NO

STUDENT'S ID

EEE21202

ABDUL KARIM HAKIMI BIN NAZLIN

EEE21231

AHMAD BAHRIN BIN AHMAD BUSHRA

EEE21246

AHMAD BAIHAQI BIN MOHAMED

EEE21230

AHMAD HAFIZI BIN MOHAMED @ AZIZ

EEE21224

AHMAD NABIL FIKRI B. PAIMAN

EEE21205

MOHAMAD AMIRUL AEZRIQ BIN JOHARI

EEE21227

MOHAMAD FAEZ SOLIHIN BIN ABD HALIM

EEE21217

MUHAMAD NURRIDZUAN BIN MOHAMAD NOH

EEE21221

MUHAMMAD ADAM BIN ABDUL MALIK

10

EEE21225

MUHAMMAD SYAKIR BIN TAJUDIN

11

EEE21229

NUR DIANAH BINTI ABD. AZIZ

12

EEE21234

NUR MUHAMMAD HAKIM BIN JOHARI

13

EEE21223

NUR SYAZA SYAFIQAH BINTI ZULHAMRI

14

EEE21236

NURASHIKIN BINTI HARUN

15

EEE21213

SHAMIRRUL BIN KUSHAIRI

16

EEE11204

ZUHAIRI BIN MUHAMMAD**

17

EEE 11205

SYAHRIL BIN ADAM**

A2

UNIT 68
(EEM 5734)

A3

UNIT 38
(EBM 6033)

UNIT 3
(EEP 6635)

UNIT 26
(MPU 6223)

APPLICATION OF PROJECT DESIGN,

MANAGING PEOPLE EMPLOYABILITY
POWER
IMPLEMENTATION
IN ENGINEERING
SKILLS
ELECTRONICS AND EVALUATION

A1

A2

STUDENT'S NAME

18

- 14 -

Noran Zahrine & All

Technical lecturers
Abdul Mutalib
A3

A1

A2

A3

A1

Mohd Haniez

Norhisyam

Zuliana

Mohd Haniez

A2

A3

A1

A2

A3

Appendix 5

- 15 -

Appendix 6

- 16 -