302

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 14, NO. 4, NOVEMBER 2001

Characterization of Systematic MOSFET Current

Factor Mismatch Caused by Metal CMP Dummy
Structures
Hans P. Tuinhout and Maarten Vertregt, Member, IEEE

AbstractThis paper presents a study on techniques for characterization of metaloxidesemiconductor field-effect transistor
(MOSFET) transconductance mismatch, using matched pairs with
intentional 1% dimensional offsets. The relevance of this kind of
work is demonstrated by the introduction of a new mismatch phenomenon that can be attributed to mechanical strain, associated
with metal dummy structures that are required for backend chemical mechanical polishing (CMP) processing steps.
Index TermsMicroelectronic test structure, MOSFET measurement method, systematic parametric mismatch.

I. INTRODUCTION

RANSISTOR size reduction and the continuing evolution toward mixed signal system-on-a-chip solutions
that require integrated high-precision analog small-signal
processing, have considerably intensified the attention for
metaloxidesemiconductor field-effect transistor (MOSFET)
matching in modern complimentary metaloxidesemiconductor (CMOS) technologies [1][7]. Matching, short for
statistical device behavior differences between supposedly
identical components, is usually attributed to random variations
of microscopic physical quantities, like edge roughness, fluctuation of the number of dopant atoms or interface states, etc.
[3], [4]. Usually these stochastic variations are characterized
through the standard deviations of mismatch distributions of
and
the main MOSFET compact model parameters (
). Besides these random fluctuations, several physical
effects are causing so-called systematic mismatch, meaning that
the median (or the average) of the mismatch distribution deviates significantly from zero. Causes for systematic mismatch
observations are for example: photomask offsets, topography
related offsets [5] and local mechanical stress asymmetries [6],
[7]. Although systematic mismatch effects are often relatively
small (from a few percent down to a fraction of a percent),
their impact on the performance of high precision analog
electronic circuits can be quite significant. Applications like
high-resolution A/D and D/A converters (10 bits and higher)
suffer (yield loss) from levels of component inequality down to
as low as the 0.01% range. Apart from the efforts that need to
go into the fabrication of devices with these low mismatches,

Manuscript received November 14, 2000.

The authors are with Philips Research The Netherlands, 5656 AA
Eindhoven,
The
Netherlands
(e-mail:
hans.tuinhout@philips.com;
maarten.vertregt@philips.com).
Publisher Item Identifier S 0894-6507(01)09764-0.

Fig. 1. Example of a measured distribution of the relative current factor

mismatch = for a population of 90 W=L
= m N-channel
transistors. Statistical estimators: Median
0.15%, Standard deviation
0.18%.

=0

= 10 10

this poses stringent demands on measurement techniques for

characterization of these mismatch effects.
Fig. 1 presents a typical example of a measured histogram
for a population
of the relative current factor mismatch
m N-channel transistors. The MOSFET
of
,
current factor is defined in the usual manner as
the gate-oxide capaciin which represents the mobility,
and the (effective) transistor width and length
tance and
respectively. Even an inexperienced statistical eye will have
no difficulty to identify a systematic mismatch in this distribution, which is confirmed by the calculated statistical estimators
(for this example yielding a median value of 0.15%). However, the inevitable dilemma that one is faced with at this point
is the question whether this perceived systematic mismatch is
due to the fabrication process, or perhaps caused by the measurement. Note that a 0.15% mismatch on a 10 m large device
can be explained by as little as 15 nm dimensional offset on silicon. On the other hand, this systematic mismatch could have
also been caused by a 0.15% offset in one of the current meters
or, alternatively, a 150- V voltage offset in one of the 100-mV
drain voltage sources that are used for the linear region parameter extraction algorithm. These are numbers that generally fall
well within the overall specifications of the technology under
investigation as well as of the used measurement equipment.
Whereas most of the matching literature focuses on techniques for characterization of the random component of

08946507/01$10.00 2001 IEEE

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TUINHOUT AND VERTREGT: CHARACTERIZATION OF SYSTEMATIC MOSFET CURRENT FACTOR MISMATCH

303

Fig. 2. Schematic drawing of CS/CG matched pair test structure layout. The
two drains of each pair are padded out separately.

mismatch distributions, this paper (along with [5] and [7])

presents a study on the limits of systematic mismatch characterization of, in this case, the MOSFET transconductance (or
rather current factor ). A very useful tool for this study proved
a set of MOSFET matched pair test structures in which two
of the pairs were designed with intentional 1% dimensional
offsets. Techniques for calibrating measurements systems and
algorithms using known deviations around a target value are
quite common in the world of advanced metrology. Obviously
the approach as used in this paper does not provide an official
absolute measurement accuracy as the test structures are not
calibrated using traceable standards from a certified institute.
Nevertheless, offset test structures as the ones proposed in this
paper prove very useful for assessing whether the observed
small systematic mismatches could be due to measurement
system limitations, or that they can indeed be attributed to
physical phenomena.
In the following sections, our test structures are described,
a measurement method explained, some results discussed and
several measurement method improvements suggested. The relevance of this type of work is demonstrated through the introduction of a new systematic mismatch phenomenon. We show
that metal dummy patterns as used for backend chemical mechanical polishing (CMP) can have significant detrimental impact on matching of MOSFETs.

Fig. 3. Composite photograph of full suite of matched pair test structures. The
set of 45 matched pairs is placed twice on a multiproject chip. (The rest of the
test chip is not shown.)

II. TEST STRUCTURE

Fig. 2 presents a schematic drawing of the used MOSFET
matched pair test structure layout. The pairs are of a CommonSource/Common-Gate (CS/CG) layout configuration. The two
drains of each pair are padded out separately. This layout approach was applied for a full suite of transistor geometries in
a 0.18- m CMOS technology. The complete set of test structures consists of 45 different matched pairs (Fig. 3), ranging
from standard n- and p-channel pairs with varying geometries to
specials like the intentional offset pairs discussed in this paper.
Fig. 4 shows a photomicrograph of the heart of a
matched pair transistor test structure (after processing up to the
second metal level). The most striking (confusing) features of
modern CMOS test structures are the so-called CMP dummy
structures (tiles). In Fig. 4 they are visible for the mask layers
active and poly (small stacked squares) as well as for tungsten
metal-1 (large dark-grey squares) and aluminum metal-2 (large
light-grey squares). CMP dummy structures are automatically
generated and placed during the mask post-processing in order
to create sufficient layer coverage to assure homogeneous CMP
pad pressure over the entire (test) chip area. However, to prevent possible matching degradation associated with incomplete

Fig. 4. Photomicrograph of NC 10/10 MOSFET matched pair. Circles

indicate the positions of the two transistors T (left) and T (right). CMP
dummy structures (tiles) are visible for the mask layers active and poly (small
stacked squares, Metal-1 (Tungsten; large dark-grey squares) and Metal-2
(Aluminum; large light-grey squares).

H passivation [6], some of the metal dummies were removed

in the test structure areas where they coincided with a transistor
gate.
The MOSFET mismatch-measurement-algorithm verification study reported in this paper was carried out using three
pair. In two of
versions of a standard n-channel
the three pairs, a 0.1 m dimensional offset was deliberately
introduced in one of the transistors of the pair. This should
result in either a 1% or a 1% systematic offset of the
current factor mismatch distribution. Table I lists the design
dimensions of the three pairs as well as their names by which
they are identified in this paper.
To reduce the statistical uncertainty for calculation of the statistical estimators and for populations derived from a single

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304

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 14, NO. 4, NOVEMBER 2001

TABLE I
OFFSET PAIRS: LAYOUT DIMENSIONS

wafer, the entire set of transistor matching test structures was

placed twice on each reticle. In this paper these two positions
are denoted as the #1 and #2 positions respectively (see Fig. 3).
In total, all populations for the experiments discussed in this
paper hence consisted of 2 45 ( 90) pairs, coming from the
45 reticle placements that were spread out evenly over the entire
200-mm wafer.
III. MEASUREMENT ALGORITHM
The MOSFET mismatch measurements are performed using
a dedicated dc matching characterization station, based on an
HP4156A high-precision semiconductor parameter analyzer
and a low-noise Cascade-Microtech semi-automatic wafer
prober. Both transistors of each pair are probed simultaneously but are measured time-sequentially using a three-point
linear-region direct-extraction technique [8], [9]. This algorithm yields three parameters for each transistor of the pair: a
, a current factor and a mobility reducthreshold voltage
tion factor (Fig. 5). The parameter absorbs the source/drain
resistances as well as needle/probe/cable series resistances.
The current factor mismatch (equal to the transconductance
mismatch), is defined as:

To reduce measurement system induced uncertainties and

noise as much as possible, no switching matrix is used in
this mismatch characterization system. This avoids additional
switch relay resistances fluctuations and offsets due to thermal
voltage differences. Moreover, as this measurement station is
also used for matching characterization of high-performance
poly-emitter BJTs, it was decided to define test structures and
measurement methods in such a way that no switching matrix
would be required for the matching characterization studies
(switching matrices tend to make BJT measurements more
prone to device oscillations).
Fig. 6 gives the measurement circuit that we used. As a result
of relying on a measurement setup without switching matrix, the
drains of the two MOSFETs must be connected to two separate
(but fixed) SMUs (and needles, manipulators, cables, etc.).
The CS/CG matched pair test structure configuration and associated measurement circuit is usually chosen for its optimum
measurement system performance with respect to characterization of threshold voltage mismatch. The CS/CG layout assures that the main (sweeping) voltage variable for the threshold
is identical for both transistors of
voltage measurement

Fig. 5. Example of linear region MOSFET measurements (V

= 0:1 V,
V
=
0 V). Circles: Drain current. Triangles: Transconductance
(dI =dV
). Encircled (three) drain currents are used for parameter
extraction. Interpretation of resulting parameters V ,  and  are indicated in
the graph.

Fig. 6. Used measurement circuit for CS/CG MOSFET matched pair

mismatch characterization. Note: substrate (chuck or well) is connected to
SMU5.

the pair. By measuring the main transistor currents

and
in the (common) source connection (SMU2) rather than
using the two drain SMUs, systematic mismatch observations
due to offset, gain differences or ranging artifacts between the
current meters in SMU3 and SMU4 are avoided.
Time-sequentiality of the measurements of the two transistors
that are probed simultaneously is realized through alternating
is measured,
is set
the drain biases. When transistor
is equal to zero. When
is measured,
to 0.1 V while
is at 0.1 V while virtually switching off by setting
to zero. In reality setting
to zero is not a very effective
technique for switching off an MOS transistor. The transistor
that is supposed to be switched off is obviously biased with the

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TUINHOUT AND VERTREGT: CHARACTERIZATION OF SYSTEMATIC MOSFET CURRENT FACTOR MISMATCH

same gate voltage as its twin in the CS/CG pair. Hence, due to
the voltage offset of the zero volts SMU, a substantial current
(order of pico-Amps or even nano-Amps) will flow through this
transistor, which will add to the main transistor current in the
(common) source connection. This is a fundamental limitation
of this approach. The choice between measuring the two drain
currents (simultaneously) in separate SMUs or measuring them
(sequentially) in the common source SMU depends on the hardware specifications and the calibration accuracy of the available measurement system. In practice we have seen no evidence
of possible systematic mismatch contributions of the described
time-sequential measurement technique. Nevertheless, some alternative techniques are discussed in the discussion section of
this paper.
All transistors of a particular population are measured using
(e.g.,
V,
the same three fixed gate voltages
V and
V, see Fig. 5). This means that
may vary slightly due
the gate overdrive voltages
to the threshold voltage spread across the wafer. In the reported
experiment, the effect of this variation is negligible, as the stanvariation across the wafer was found to
dard deviation of the
devices. The most
be less than 1 mV for these
important criterion for the selection of the three gate voltages
is that the lowest point should at least be located at (or slightly
above) the peak-transconductance point (Fig. 5). This assures
that the transistor operates in the (linear) modeling regime that
is used for the parameter calculations. This is quite similar to
what was suggested by Hamer in [8].
For most studies on MOSFET matching, the system and
method described above proves to be more than adequate.
The short-term repeatability performance for determination of
and current factor mismatch standard deviations (
and
) are typically better than 50 V and 0.02%,
respectively. This is for instance visualized in Fig. 7, which
displays results of measuring the mismatch distribution for
a particular population of (standard) 10/10 pairs two times.
Along the horizontal axes, the individual mismatch observations are depicted as determined initially, whereas the vertical
axes corresponds to the results for exactly the same population
measured approximately one hour later. The correlation speaks
for itself while the scatter gives an impression of the normal
short-term repeatability levels as mentioned above.
IV. RESULTS AND DISCUSSION
The main purpose of the study as reported in this work was
to identify how useful the standard algorithm as discussed in
the previous section is for identification of systematic transconductance mismatch occurrences. As will become clear during
the remainder of this paper, the example of Fig. 1 is in fact
a classical example of a double distribution coming from two
slightly different populations, each with their own systematic
mismatch component. The questions that we were faced with
were: how real are these systematic mismatch observations and
what causes them?
During this study, we came to the conclusion that the main
weakness of the no-switching-matrix measurement approach
described in the previous section lies in the fact that the two

305

Fig. 7. Scatter plots of two measurement sequences (approximately one hour

apart) of the same population of standard 10/10 matched pairs. Deviation from
the perfect 1 : 1 correlation gives indication for the short-term repeatability of
the chosen characterization approach.

transistors of the pair are not biased with exactly identical drain
SMUs. Voltage forcing differences of up to 200 V are not uncommon according to the specifications of the used parameter
analyzer system. When studying subtle systematic mismatch effects, differences of this magnitude can be quite significant, as
the voltage forcing offset propagates linearly into the observed
current factor mismatch. Note that an offset of 200 V on an
intended 100 mV bias would correspond to a 0.2% systematic
current factor mismatch!
For very detailed mismatch studies like the one presented in
this paper, the effects of this systematic SMU voltage difference can be suppressed by measuring the mismatch distributions twice: initially as depicted in Fig. 6, and then the entire
mismatch distribution is remeasured after interchanging the two
drain probe positions, or alternatively by swapping the cables to
SMU3 and SMU4 (the manual cable chaser switch matrix).
consists of
Let us assume that an observed mismatch
associated with the actual
two independent components: a
due to the
mismatch between the devices of the pair and a
measurement system (for instance caused by the voltage source
offset difference suggested above). During the initial measurements of the population of pairs this results into mismatch obserfor each pair:
.
vations
When we interchange the physical connections to the pair we
.
get a second set of observations
As we can safely assume that the devices (and hence their mismatch) have not changed, the observed mismatch of the device (as seen by the measurement system) should reverse sign
, whereas the contribution of the system
itself will remain unchanged (if the voltage offset between the
two SMUs has not changed during the entire double measure. Now it follows that
ment procedure):

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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 14, NO. 4, NOVEMBER 2001

1 (solid triangles;
= 00:093% and  =

Fig. 8. Normal Scaled cumulative probability plot of


: % and 
: %) and
(xs; 
: %).

= 0 015
0 01

= 0 17

similar slopes (standard deviations). This is as expected as the

effective device areas are almost identical. The vertical axis
intercepts of the three distributions indeed yield the designed
1% 0% and 1% systematic mismatches quite accurately.
The statistical estimators resulting from these (twice measured)
transconductance mismatch distributions are summarized in
Table II. Values between brackets represent estimates for the
statistical uncertainties as determined using bootstrap analysis
[10]. Apart from the good agreement between the designed
and measured medians of the matching distributions, we see
that the median of measurement systems offset ranges from
0.093% to 0.101%. This contribution can be attributed to a
offset voltage difference between SMU3 and SMU4 of the
order of 100 V. Again it will be obvious that this offset would
have severely distorted any conclusion about the systematic
mismatch of the pairs if not compensated for.

V. ALGORITHM IMPROVEMENTS

Fig. 9. Cumulative probability plots for current factor mismatch for the three
offset matched pair test structures (#1 reticle position). Estimators: see Table II.

subtracting the individual mismatch observations removes the

SMU3/4 systematic offset contribution from the transistor mis. Adding
match observation:
the two observations and dividing by , yields the actual mea.
surement systems offset, as
An example of results obtained using this measurement compensation approach is shown in Fig. 8, where cumulative probability plots are given of the resulting device mismatches
for the standard 10/10 pairs at the #1 reticle positions, as well
. The horias the calculated measurement system offset
zontal axis in this figure represents the cumulative probability
expressed in terms of sigmas. The used (NORMSINV) scaling
transforms the (sorted) mismatch observations to a straight line
when the distribution is normal. Standard statistical estimator
% and
calculations yield
% for the transistor mismatch distribution and
% and
% for the measurement systems
offset distribution.
From this example, we can conclude that the noise contribuof the measurement system is very small comtion
pared to the transistor current factor mismatch fluctuations. The
, on the other hand
measurement system induced offset
(about 0.1%), can definitely not be neglected for this example.
Fig. 9 depicts the current factor mismatch results for the
three offset test structures when the double (cable swapping)
measurement technique as described above is used. The
cumulative distributions for the three populations display

It will be evident that once the main limitations of the original method are pinpointed, several alternative measurement
methods spring to mind. After all, measuring every distribution
twice may be acceptable for an exploratory study, but is not
very practical when many devices are to be characterized.
An example of an alternative method is based on a voltage
transformation scheme combined with SMU ground voltage
offset compensation. This approach is comparable to the one
used for accurate measurements of bipolar junction transistors
as described in [11]. For MOSFETs, this means that instead of
measuring the transistors with the drain at 0.1 V, we ground the
drain for the transistor under test and apply a negative source
voltage. Obviously one has to adapt all other biases for this
approach: i.e., the substrate at 0.1 V while subtracting 0.1 V
from all intended gate biases. Setting its drain bias also to
0.1 can deactivate the transistor of the pair that is supposed
to be inactive. The main advantage of this approach is that
is now also identical for
the secondary driving voltage
both transistors of the pair since it is determined by the forcing
voltage source of SMU2. Likewise to what was reported in
[11], the voltage source inequality problem is now shifted to
the inequality of the zero value (COMMON) of the two drain
SMUs. By placing extra needles on the two drain contact pads
and connecting these with the internal differential voltmeter of
the parameter analyzer (VMU1 and 2), we can monitor (and
compensate for) this offset voltage.
Fig. 10 shows a measured example of the voltage difference
between SMU3 and SMU4 when they are both at COMMON
(both transistors active!). This graph is compiled from offset observations during the mismatch measurements of some 500 pairs
while testing the voltage transformation scheme as sketched
above. As it took several hours to collect these measurements
(this includes the mismatch measurements, aligning the wafer,
adjusting probes etc.) the following conclusions can be drawn
from this figure:
offset voltages of the
1) It is indeed not unlikely that
order of 100 V are the major cause for the systematic
offset that was identified in the previous Section II.

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TUINHOUT AND VERTREGT: CHARACTERIZATION OF SYSTEMATIC MOSFET CURRENT FACTOR MISMATCH

307

TABLE II
MATCHING AND SYSTEM OFFSET RESULTS FOR OFFSET PAIRS AT #1 POSITION

Fig. 10. Voltage offset between SMU3 and SMU4 during verification of
voltage transformation measurement algorithm (both SMUs grounded).

2) Apart from some outliers that are probably due to EMC

disturbances (power-line disturbances?), the noise as observed around the typical offset voltage is of the order of
about 10 V.
3) A slow drift is observed of the order of 1020 V, possibly related to a small temperature increase in the measurement laboratory that was observed during this test.
4) Both the drift and the noise are small enough to justify
that the (accurate, lengthy, long integration) voltage offset
measurements do not have to be repeated for each pair as
was done for Fig. 10: Once for each distribution of 4050
pairs seems sufficient.
5) As the transconductance of a MOSFET is linearly pro, the value that is obtained from the
portional to its
offset voltage measurement can simply be used to correct
the mismatch observation. This brings the uncertainty due
to the measurement system down by at least an order of
magnitude: From 100 to 200 V to a level of 10 to 20 V.
This would correspond to a transconductance mismatch
level of the order of 0.01% to 0.02%, which is the same
order as the systems noise (Figs. 6 and 7).
In conclusion, we can say that the voltage transformation
scheme combined with occasional monitoring the common
offset drift of SMU3 and SMU4 proves a viable solution for
characterising systematic mismatches down to a level of as low
as 0.1%.
An alternative approach to reduce the impact of some of the
limitations sketched above would be to start from an entirely
different matched pair test structure design. If we would use a
common source and common drain (CS/CD) test structure (with

separate Gate pads for each transistor of the pair), we would

not have to worry about the offsets of the Drain connection, but
obviously this is now replaced by an uncertainty due to Gate
voltage differences. The advantages of this alternative type of
matched pair test structure are:
1) The observed mismatch will be independent of the
Drain and Source voltages and the main (Drain) currents
areby definitionmeasured with the same current
meter.
2) As both the Source as well as the Drain pad are common,
probe needle-to-pad resistance differences will not
influence the mismatch observation. This is particularly
important for higher current mismatch measurements
( 100 A). As the Gate current is (many) orders of
magnitude lower than the Drain and Source currents,
voltage drops in the Gate-pad-to-probe needle will be
negligible.
3) It is much easier to switch off one of the transistors while
the other one is measured, as the gate of the inactive transistor can be biased well into the subthreshold regime
of the transistor. This is much better controlled than the
rather unpredictable Drain off-current that can flow in the
CS/CG structure.
Whereas the CS/CG matched pair test structure approach
allows the choice between a time-sequential measurement
(using the current meter in the common Source connection)
and a simultaneous measurement (using the two current meters
of the two Drain SMUs), this freedom obviously does not exist
for CS/CD matched pair test structures. CS/CG pairs must be
measured time-sequential. The major concern of a time-sequential type of measurement is associated with temperature
drift between the measurements of the two devices. It should
be noted that for extremely sensitive mismatch measurements
( 100 ppm), a temperature drift of the order of 0.01 C
between measurements of two devices may become noticeable.
Obviously, for applications where systematic threshold
voltage mismatch measurements of the order of 100 V are
deemed critical, a voltage transformation scheme as sketched
above, combined with monitoring the (common) voltage offsets
of the Gate SMUs can be used.
Finally, a word of caution about an alternative for the earlier mentioned fundamental limitation of our original CS/CG
measurement algorithm. As discussed before, realizing time-sequentiality of the current measurements by switching off one of
is not very effective. In printhe transistors through a 0 V
ciple it is possible to assure that the current through the inactive

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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 14, NO. 4, NOVEMBER 2001

TABLE III
MATCHING AND SYSTEM OFFSET RESULTS FOR OFFSET PAIRS AT #2 POSITION

transistor is negligible by programming its SMU as a zero (or

very low) current source. This assures that the currents through
the inactive transistor are many orders of magnitude lower than
the currents in the active transistor. We tested this approach but
had to abandon it as we found that this method resulted in an
unacceptable number of destructed pairs. We did not investigate this in depth, but apparently the sequence of switching
on and off the various voltage and current sources in this approach resulted in substantial spikes on the gates, which sufficed
to blow-up the gate oxide of a significant number of pairs. In
practice this meant that re-measuring a distribution became virtually impossible, and the quite attractive repeatability results
as shown in Fig. 7 could not be reached with this alternative
approach.
VI. A NEW MISMATCH PHENOMENON
One of the reasons for conducting this extensive study toward
the limitations of the existing MOSFET mismatch characterization algorithm was the observation of a more or less unexpected
systematic mismatch phenomenon. Table III forms an introduction to this effect. This table summarizes the statistical estimators for the set of dimensional offset transistor pairs, be it that
they are taken from the #2 reticle positions, as opposed to the
data from Table II that were obtained from the #1 reticle positions. These #1 and #2 reticle positions (see Fig. 3) were supposed to be identical. They were placed on the reticle to reduce
statistical uncertainty and with an idea at the back of minds of
possibly searching for evidence of systematic differences due to
e-beam reticle writing artifacts.
Clearly, Table III reveals the same trends with respect to the
statistical estimators as Table II. The standard deviations are
very much comparable, while the system noise and offset are
virtually identical. Nevertheless, the data suggest that the median values of the matching differ statistically significant from
the data summarized in Table II. Since these results were collected from a different population (the other reticle position), the
initial explanation for this discrepancy was sought in a possible
offset caused by mask dimension differences on the reticle. The
e-beam writing of the reticle is not necessarily identical as the
patterns related to both reticle positions are relatively far apart
(a few mm). Moreover, the differences that are needed to explain the observations (0.1% for 10/10 transistors) correspond
to an offset on silicon of approximately 10 nm (or 40 nm on
the (4X) reticle). This is within the CD specifications of the reticles as used for this experiment. Nevertheless, this explanation
had to be abandoned as more transistor pairs from the same test

Fig. 11. Cumulative probability plots for current factor mismatch for
N-channel (W=L = 2=1) transistors. Estimators: see Table IV.
TABLE IV
MATCHING RESULTS FOR N-CHANNEL W=L = 2=1 PAIRS

chip were investigated. Surprisingly it was found that these systematic differences between the #1 and #2 reticle positions occurred for many pairs. Moreover, some pairs gave significantly
larger differences than others, seemingly without any consistency with respect to their dimensions and respective reticle
positions. A rather spectacular example of the systematic mismatch difference between the two reticle positions for n-channel
[ m/ m] pairs is shown in Fig. 11.
The statistical estimators for the two current factor mismatch
distributions from Fig. 11 are summarized in Table IV. The
values between brackets again represent the statistical uncertainties due to the fairly limited sample size and were again
estimated using the bootstrap technique.
These data were obtained using the original matching characterization algorithm without second measurement and interchanging SMU3 and SMU4. As pointed out before, a systematic mismatch of about 0.1% can be attributed to the offset of

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TUINHOUT AND VERTREGT: CHARACTERIZATION OF SYSTEMATIC MOSFET CURRENT FACTOR MISMATCH

Fig. 12. Photomicrograph of NC2/1 MOSFET matched pair (#1 reticle

position).

Fig. 13. Photomicrograph of NC2/1 MOSFET matched pair (#2 reticle

position).

the measurement system. However, in this case the two reticle

positions were measured alternating during one characterization
run. This means that the systematic mismatch due to the system
cannot explain the difference between the systematic current
factor mismatches of the two reticle positions. It will be evident
from Fig. 11 and Table IV that there is something quite peculiar with the matching of these devices. A closer look at the test
structures however, reveals an unexpected difference between
the two reticle positions (Figs. 12 and 13).
The two test structure realizations at the two reticle positions are covered by different Metal-2 CMP dummy patterns.
In essence the CMP dummy-filling algorithm of the chip-finishing program causes this. This program starts by placing its
first square at a certain pattern (origin) point of the mask layer.
Subsequently the program drops the dummy tiles at those points
where the filling of the particular mask layer is below a certain density at a fixed grid. Obviously, the tiles are not allowed
to interfere with the patterns already defined in the same layer.

309

Note for instance the (dark grey) Metal-1 dummy placement difference between the transistors when comparing Fig. 4 (10/10
transistors) and Fig. 12 (2/1 transistors). However, apparently
the origin point is not the same for each mask layer and dummy
pattern, for the used dummy placement algorithm, which in this
case results in slightly different Metal-2 dummy patterns for the
two reticle positions.
As mentioned before, the process family that was used to fabricate these devices has in the past given matching problems due
to incomplete H passivation as well as mechanical stress offsets
when transistors are covered with metal plates [6]. To avoid possible problems, dummy tiles were removed (manually) where
they coincided with a transistor. These seemingly arbitrary removals were intended to at least open-up paths for hydrogen to
diffuse toward the transistors. Unfortunately (or perhaps fortunately!), this last-minute manual removal action resulted in a
significant environmental asymmetry between the two transistors of the pairs. The asymmetries, resulting from these last
minute CMP dummy removals were recognized as they were
created, be it that the extend of their impact came as an interesting surprise .
We demonstrated before in [6] that metal coverage can result in significant matched pair asymmetries due to asymmetry
of the (local) mechanical strain that can be caused by strained
(ILD dielectric or Tungsten first metal) layers from the back-end
process. Strain differences translate into mobility differences
(and hence transconductance differences) through the piezo-resistance effect in silicon [6], [12]. That the systematic current
factor mismatch difference between the #1 and #2 reticle positions is due to mechanical strain was verified by checking the
distributions of the threshold voltage mismatch of these two
populations. As no significant difference could be distinguished
between the threshold voltage distributions, we felt quite safe to
conclude that we were indeed looking at a mobility related mismatch effect, although strictly speaking we realize that a complete proof of this conclusion is not given here. Further tests
involving extensive back-end experiments and device (or substrate) orientation variations would be required to prove this.
Now let us go back to the much smaller, but nevertheless statistically significant, median differences between Tables II and
III. Careful scrutiny of the 10/10 offset pair test structures indeed reveals similar CMP dummy coverage asymmetries, be it
less blatant than in the example of Figs. 11 and 12.
The careful reader of this paper will now understand the path
that this investigation followed. It was the initial histogram of
Fig. 1, composed of the combined populations of the #1 and #2
reticle positions, that initiated this work. The question whether
the observed systematic mismatch component that was observed
in Fig. 1 was due to the measurement algorithm or caused by
the process should be answered by: Both: We had to refine the
measurement method to get rid of measurement system induced
systematic mismatches of the order of a few tenths of a percent,
but after this we had to conclude that an unexpected mechanical strain related effect caused the major part of the observed
systematic mismatches. This work demonstrates that it is worthwhile to improve mismatch measurement algorithms to an accuracy level well below 0.1%. New mismatch effects are encountered at these levels, which may originally seem small, but can

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310

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 14, NO. 4, NOVEMBER 2001

prove to be serious matching hazards in modern mixed-signal

CMOS applications.
VII. CONCLUSION
This study exemplifies the relevance of careful systematic
transconductance mismatch characterization. It demonstrates
that one cannot be careful enough in assuring identicality of
the test structures (environment) as well as the characterization
hardware and measurement algorithms.
The paper discusses limits of MOSFET mismatch characterization. The commonly used CG/CS matched pair test
structure layout is discussed, together with the limitations of a
(no switching matrix) parameter analyzer based measurement
approach.
By analyzing transistor pairs with intentional 1% and 1%
dimensional offsets, limitations of the original measurement algorithm are established. Measurement algorithm improvements
are suggested and tested. These can bring the measurement
system induced systematic transconductance mismatch contribution down to a level of the order of 0.01%, which opens
up the possibility to study subtle sub 1% systematic mismatch
effects. As a demonstration of this improved characterization technique, a new systematic mismatch phenomenon is
revealed. It is shown that careless placement of the so-called
CMP dummy tiles can have significant detrimental effects on
matching of MOSFET transconductance.

[6] H. P. Tuinhout and M. Vertregt, Test structures for investigation of metal

coverage effects on MOSFET matching, in Proc. IEEE Int. Conf. Microelectronic Test Structures, vol. 10, 1997, pp. 179183.
[7] J. Bastos, Characterization of MOS transistor mismatch for analog design, Ph.D. dissertation, Katholieke Universiteit Leuven, 1998.
[8] M. F. Hamer, First-order parameter extraction on enhancement silicon
MOS transistors, Proc. Inst. Elect. Eng., pt. 1, vol. 133, no. 2, pp. 4954,
1986.
[9] H. P. Tuinhout, S. Swaving, and J. J. M. Joosten, A fully analytical
mosfet model parameter extraction approach, in Proc. IEEE Int. Conf.
Microelectronic Test Structures, vol. 1, 1988, pp. 7984.
[10] P. Diaconis and B. Efron, Computer-intensive methods in statistics,
Scientific Amer., pp. 96108, 1983.
[11] H. P. Tuinhout and W. C. M. Peters, Measurement of lithographical
proximity effects on matching of bipolar transistors, in Proc. IEEE Int.
Conf. Microelectronic Test Structures, vol. 11, 1998, pp. 712.
[12] A. Steegen, M. Stucchi, A. Lauwers, and K. Maex, Silicide induced pattern density and orientation dependent transconductance in MOS transistors, in IEDM Tech. Dig., 1999, pp. 497500.

Hans P. Tuinhout received the M.Sc. degree in electrical engineering from the Delft University of Technology, Delft, The Netherlands, in 1980.
Since then, he worked for the Philips Research
Laboratories, Eindhoven, The Netherlands, on
CMOS and BiCMOS process and device characterization. His current research activities in the device
modeling group at Philips Research are focused on
accurate dc parametric measurements, in particular
for characterizing statistical differences between
supposedly identical (matched) IC components and
looking for techniques to interpret stochastic mismatch effects to improve performance and yield of digital and mixed signal integrated circuit technologies.

REFERENCES
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analog low power design: The problem of low voltage and mismatch,
in Proc. CICC 97, 1997, pp. 285292.
[2] M. J. J. Pelgrom, H. P. Tuinhout, and M. Vertregt, Transistor matching
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[3] K. R. Laksmikumar, R. A. Hadaway, and M. A. Copeland, Characterization and modeling of mismatch in MOS transistors for precision
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Maarten Vertregt (M89) received the M.Sc. degree

in electrical engineering from the University of
Twente (UT), Enschede,The Netherlands, in 1985.
He started with Philips Research Laboratories,
Eindhoven, The Netherlands, on the design of 1- and
4-Mb SRAM memories. Subsequently, he worked on
A/D conversion with embedded signal processing.
Since 1996, he coordinates the design activities
for high-speed A/D conversion functions within
the Mixed-Signal Circuits and Systems Group of
Philips Research. His research interests are with the
migration of signal processing from the analog domain to the digital domain in
relation to both process technology scaling and new system demands.

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