PRR - Vxworks

A step by step guide to implement of 3 Partial Reconfiguration Regions through ICAP
with VxWorks
A
Technical Report
Submitted By
Vaibhawa Mishra
This flow will cover all specific changes which must occur in all tool flows in order to
integrate the PowerPC wrappers with any custom partial or static VHDL modules.
Following these steps it should be possible to create the entire design. This experimental
system is for ML410 board for other boards the same step can be followed. When
configuration is needed from the FLASH, use TestApp_Peripheral form flash.c file in the
resource folder.
Tools required
1. ISE design suit 9.1 service pack 2
2. EDK 9.1 service pack 2
3. PlanAhead 10.1
Platform Used
Windows XP Professional
Installation of tools
1. Install ISE and EDK 9.1[ SetUp files available in ISE folder]
2. Enter the Registration ID, which is available in ISE folder as License.txt
3. Update ISE and EDK with patches ISE sp2 and EDK sp2 by double click on
these update patches[available in ISE folder]
4. Install PlanAhead 10.1 tool[ Move to Xilinx10i_completeSuite folder and Run
setup.exe, Choose ONLY PlanAhead 10.1 and Uncheck rest of the options and
continue installation]
5. Install PR9.1 tools
a. Unzip PartialFlow_91i_PR10_nt.zip into a temporary directory.[folder
already unzipped]
b. Ready to install partial reconfiguration implementation tools by
executing from a command prompt in the temporary directory:
xilperl PRinstall.pl PRfiles_nt.txt
Installation can be verified by looking at the PR_assemble.pl

document and verifying that the files were copied to the
XILINX\bin\nt directory
Create Processor System

Step 1
Open XPS by selecting Start Programs Xilinx Platform Studio 9.1 Xilinx
Platform Studio. Refer to figure 1.
Figure 1-opening XPS from program menu
Use default setting of Base System Builder wizard and click OK as in figure 2
Figure 2- selecting option to create project
Browse to drive:/vab_test_doc/ edk_system directory and click Save as in figure 3
Figure 3- giving project path to EDK tools
Click OK
Base system Builder welcome will appear as in figure 4
Figure 4- BSB Wizard
Check the option I would like to create a new design. Click Next. As in figure 5
Figure 5- BSB Wizard Select Board Option
Xilinx in Board vendor, ML410 Evaluation Platform in Board name, and C in Board
revision fields, and then click Next as in shown 5
Figure 6-BSB Wizard- Select Processor
Select PowerPC and Click Next in the figure 6
Figure 7- BSB Wizard - Configure PowerPC option
Select
o
o
o
o
Processor CLK Frequency 100 MHz(defaultValue) and

Bus Clk Frequency 100 MHz(defaultValue)
select FPGA JTAG(defaultValue) enables
Deselect (uncheck) USE BRAM(defaultValue) option for data and
Instruction both
o deselect (uncheck) cash enable Click shown in figure 7.
Next you see Configure IO Interface form
Figure 8- BSB wizard Configure IO Interface

Select following
RS232_Uart_1 with 9600 baud rate,

use interrupt (TickIn CheckBox) and
DDR_SDRAM_32Mx_s64 as the peripheral from this dialog box and
use interrupt (TickIn CheckBox) for DDR section appeared in figure 8.
Click Next
Figure 9- BSB Wizard- Configure IO Interface option
Select SPI_EEPROM with include receive and transmit FIFO and

use interrupt from this dialog box,
deselect rest of the option, as shown in figure 9.
Click Next
Figure 10- BSB Wizard- Configure IO option
Select SysAce_CompactFlash with use interrupt from this dialog box;

deselect rest of the option as in the figure 10.
Click Next
deselect all of the option as in figure 11 Click Next
Deselect MGT_wraper.
Click Next.
Select DDR2_SDRAM_32Mx_64 with use interrupt as the peripheral from this dialog
box. Both are shown in figure 12.
Figure 13- BSB Wizard-Add Internal Peripheral option
Select plb_bram_if_cntlr with 128 kb memory size as shown in the figure 13.
Click Next software Setup window will appear.
Figure 14- BSB Wizard- software setup option
As in figure 14, deselect Memory test and select Peripheral Self-test options, and then
click next.
Note : Take care STDIN is selected with RS232_UART_1 from dropdown box
Next window leave as it is, and then click next twice and then generate option.
Figure 15- BSB Wizard- Summary
Click FINISH to end Base System Builder Wizard as in figure 15.

Using Windows Explorer, copy opb_dcr_socket folder from the project resource folder
(Task1 Major Folder) in pcores of working directory folder in edk_system folder.
Figure 16- setting for user repository
After copying of folder is done. Select Project Rescan User Repositories, in XPS, to
make the opb_dcr_socket visible in IP Catalog tab as in figure 16.
Figure 17- Adding IPs to system
In IP Catalog tab as in figure 17, expand Project Local pcores and

double-click on opb_dcr_socket three times to add an instance of it.
Similarly, add instance of
opb_hwicap (v1.00.b), from FPGA Reconfiguration
dcr_v29 (v1.00.a), from Bus
opb to dcr bridge (v1.00.b) from Bridges folders respectively.
Figure 18- selecting bus selection
Expand opb_dcr_socket_0, opb_dcr_socket_1, opb_dcr_socket_2 opb_hwicap_0, and

opb2dcr_bridge_0 instances in System Assembly View window and connect various
busses as shown in the diagram below (you can connect two peripherals on a bus by
clicking an unfilled circle or square. As shown in the figure 18)
Figure 19- Address Space
Select Addresses filter as in figure 19 and set 4KB, 64KB, 64KB, and 16 bytes for
opb2dcr_bridge_0, opb_hwicap_0, and opb_dcr_socket_0, opb_dcr_socket_1,
opb2dcr_bridge_0
opb_hwicap_0
opb_dcr_socket_0 --- SOPB
opb_dcr_socket_0 --- SDCR
SPI_EEPROM
4KB
64KB
64KB
64KB
64KB
16 bytes
16 bytes
16 bytes
64K
opb_dcr_socket_2 instances, and then
Note: You need to differentiate bytes & Kbytes from the dropdown. SDCR 16 bytes &
SOPB 64K
click Generate
Addresses.
Open Port_intro.rtf file located in resources folder and copy and paste the contents as
instructed in Port_intro.rtf in system.mhs file to add and bring out the ports at the toplevel.
Note : File Open system.mhs (@edksys folder)
Figure 20- Generate netlist
After all desired hardware modifications, click on Generate Bit stream button, in
Hardware tab to synthesize the system as shown in the figure 20.
Figure 21- Software platform setting
Select Software Software Platform Settings, and click on xilfats and xilmfs check
box to select the fatfs file system ddr file system support as in figure 21.
Figure 22- Software Platform setting
In drivers panel, make sure that opb_hwicap is set to use driver version 1.00.c as in
figure 22 (00. file is available in hwicap_v1_00_c folder @Resource.
Create a NEW folder named Drivers and copy the folder as it is & In EDK
ReScan)
Click OK to accept the settings and close the form.
Figure 23- Generate Libs and BSPs wizard
Select Software Generate Libraries and BSPs to generate library files as in the file
23.
Open TestApp_Peripheral.c from the project resource folder and copy to
TestApp_Peripheral.c in application tab. ( All you need to do is, Replace the contents (i.e.
code) provided in Resource Folder)
Figure 24- Build All User Application
Select Software Build All Users Applications to run LibGen to generate library files
and compiler to compile the application as in the figure 24.
Upto these steps, the system has been synthesized and application is ready.
Now, the following steps will show the designing of PRRs (Partial Reconfigurable
Region).
Create Peripheral IPs for integer modules
Step 2
In this step, the PRRs are designed separately in EDK and synthesized in ISE with
some precautions. Synthesizing of PRRs has different steps unlike the normal synthesis flow.
In this context, the steps for designing a PPR have been taken for only one module, rest of the
modules also have the same steps.
Figure 25-Start to create or Import Peripheral Wizard
In XPS select Hardware Create/Import Peripheral Wizard as in figure 25.
Figure 26-Create or Import Peripheral Wizard-welcome wizard
Click Next twice, as in figure 26
Figure 27- Create or Import Peripheral Wizard-Peripheral Flow
Select Create template for a new Peripherals click next as in figure 27.
Figure 28- Create or Import Peripheral Wizard-Repository or Project
Select To an XPS project option, click Browse button, browse to

E:\vab_test_doc\edk_system\pcores (it depends on your project location), and click
OK as in figure 28.
Click Next.
Figure 29-Create or Import Peripheral Wizard-Create Peripheral- Name and Version
Name it as math with version 1.00.a and click Next.
Figure 30- Create or Import Peripheral Wizard Bus Interface
Select OPB bus for this peripheral as in figure 30 and click Next.
Figure 31- Create Peripheral IPIF Interface
Select User logic S/W register support as the only support in IPIF Service form and
click Next. Shown in the figure 31
Figure 32- Create Peripheral User S/W Register
Using drop-down button, select 2 in number of software accessible registers (as we will
be sending two operands to this IP), leave the Enable Posted Write Behavior selected as
shown in the 32 and click Next.
Figure 33-Create Peripheral IP Interconnect (IPIC)
Click Next.
Figure 34- Create Peripheral Peripheral Simulation Support
Click Next.
Figure 35-Create Peripheral Peripheral Implementation Support
Click Next.
Figure 36-Create Peripheral Finish Wizard
Click Finish to complete the IP creation as in figure 36.

Make sure opb_dcr_socket folder is copied/ made available in pcores folder #Resource
Folder.
Open user_logic.vhd file from

E:\vab_edk_test\edk_sys\pcores\pcores\math_v1_00_a\hdl\vhdl directory and edit it
to perform 32-bit addition of slv_reg0 and slv_reg1 output. Clock the output and send
the result back via slv_rge0/slv_reg1 read (see the next diagram). Save the editing and
close the file as shown below
Above steps are only PRM 1 (adder of integer type ) for Reconfigurable Region 1. The
coming steps for PRM 2 (multiplier of integer type ) for Reconfigurable Region 1.

OK as in figure 40.
Click Next.
Name it as math with version 1.00.b and click Next.
shown in the 42 and click Next.
Click Next.
Click Next.
Click Next.

Open user_logic.vhd file from
E:\vab_edk_test\edk_sys\pcores\pcores\math_v1_00_b\hdl\vhdl directory and edit it to
perform 16-bit multiplication of slv_reg0 and slv_reg1 output. Clock the output and send
Above steps are only PRM 2 (multiplication of integer type) for Reconfigurable Region 1.
The coming steps for PRM 3 (division of integer type ) for Reconfigurable Region 1.
Select To anXPS
project option, click Browse button, browse to
OK as in figure 50.
Click Next.
Name it as math with version 1.00.c and click Next.
shown in the figure 54 and click Next.
Click Next.
Click Next.
Click Next.

Openuser_logic.vhdfilefromE:\vab_edk_test\edk_sys\pcores\pcores\math_v1_00_c\hdl\v
hdl directory and edit it to perform 32-bit division of slv_reg0 and slv_reg1 output. Clock
the output and send the result back via slv_rge0/slv_reg1 read (see the next diagram).
Save the editing and close the user_logic.vhd file as shown below
Copy div_int.vhd given in integer/div folder of resource folder to

E:\vab_test_doc\edk_sys\pcores\math_v1_00_c\hdl\vhdl folder
Above steps are only PRM 3 (division of integer type) for Reconfigurable Region 1. The
coming steps for PRM 4 (subtraction of integer type) for Reconfigurable Region 1.

OK as in figure 61.
Click Next.
Name it as math with version 1.00.d and click Next.
Click Next.
Click Next.
Click Next.

Openuser_logic.vhdfilefromE:\vab_edk_test\edk_sys\pcores\pcores\math_v1_00_d\hdl\v
hdl directory and edit it to perform 32-bit subtraction of slv_reg0 and slv_reg1 output.
Clock the output and send the result back via slv_rge0/slv_reg1 read (see the next
diagram). Save the editing and close the user_logic.vhd file as shown below
Create Peripheral IPs for floating type modules
Step 3
In this step, the PRMs (floating type arithmetic) are designed for PRR2 separately in
EDK and synthesized in ISE with some precautions. Synthesizing of PRRs has different steps
unlike the normal synthesis flow.
Figure 71 -Create or Import Peripheral Wizard-welcome wizard

OK as in figure 73.
Click Next.
Name it as prr with version 1.00.a and click Next.
Click Next.
Figure 78 - Create Peripheral Peripheral Simulation Support
Click Next.
Click Next.

Openuser_logic.vhdfilefromE:\vab_edk_test\edk_sys\pcores\pcores\prr_v1_00_a\hdl\vhd
l directory and edit it to perform 32-bit 754 addition of slv_reg0 and slv_reg1 output.
diagram). Save the editing and close the file as shown below
Copy all the VHDL files given in the folder resource\float\adder

E:\vab_test_doc\edk_sys\pcores\prr_v1_00_a\hdl\vhdl .
to
Above steps are only PRM 1 (adder of floating point unit) for Reconfigurable Region 2. The
coming steps for PRM 2 (subtraction of integer type) for Reconfigurable Region 2.

OK as in figure 84.
Click Next.
Name it as prr with version 1.00.b and click Next.
click next. Shown in the figure 87
Figure 89 -Create Peripheral IP Interconnect (IPIC)
Click Next.
Click Next.
Click Next.

Openuser_logic.vhdfilefromE:\vab_edk_test\edk_sys\pcores\pcores\prr_v1_00_b\hdl\vh
dl directory and edit it to perform 32-bit 754 subtraction of slv_reg0 and slv_reg1 output.
diagram). Save the editing and close the file as shown below
Copy all the VHDL files given in the folder resource\float\sub

E:\vab_test_doc\edk_sys\pcores\prr_v1_00_b\hdl\vhdl .
to
Above steps are only PRM 2 (subtraction of floating type) for Reconfigurable Region 2. The
coming steps for PRM 3 (division of float type) for Reconfigurable Region 2.
Select To an XPS
OK as in figure 95.
Click Next.
Name it as prr with version 1.00.c and click Next.
Click Next.
Click Next.
Click Next.

Openuser_logic.vhdfilefrom
E:\vab_edk_test\edk_sys\pcores\pcores\prr_v1_00_c\hdl\vhdl directory and edit it to
perform 32-bit 754division of slv_reg0 and slv_reg1 output. Clock the output and send
close the user_logic.vhd file as shown below
Copy div_flpt.vhd files given in the folder

E:\vab_test_doc\edk_sys\pcores\prr_v1_00_c\hdl\vhdl .
resource\float\div
to
Above steps are only PRM 3 (division of floating type) for Reconfigurable Region 2. The
coming steps for PRM 4 (multiplication of float type) for Reconfigurable Region 2.
Select To anXPS
OK as in figure 108.
Click Next.
Name it as prr with version 1.00.d and click Next.
Click Next.
Click Next.
Click Next.

Openuser_logic.vhdfilefrom
E:\vab_edk_test\edk_sys\pcores\pcores\prr_v1_00_d\hdl\vhdl directory and edit it to
perform 32-bit 754multiplication of slv_reg0 and slv_reg1 output. Clock the output and
send the result back via slv_rge0/slv_reg1 read (see the next diagram). Save the editing
and close the user_logic.vhd file as shown below
Copy mult_flpt.vhd files given in the folder resource\float\mul

E:\vab_test_doc\edk_sys\pcores\prr_v1_00_d\hdl\vhdl .
Create Peripheral IPs for FFT
to
Step 4
In this step, the PRMs (FFT calculation) are designed for PRR3 separately in EDK
and synthesized in ISE with some precautions. Synthesizing of PRRs has different steps
unlike the normal synthesis flow.
Figure 117 -Create or Import Peripheral Wizard-welcome wizard

Click Next.
Name it as fft with version 1.00.a and click Next.
Click Next.
Figure 118 - Create Peripheral Peripheral Simulation Support
Click Next.
Click Next.

Openuser_logic.vhdfilefromE:\vab_edk_test\edk_sys\pcores\pcores\fft_v1_00_a\hdl\vhd
l directory and edit it to perform 4 point integer type of fft calculation. Clock the output
and send the result back via slave registers (see the next diagram). Save the editing and
Copy all the VHDL files given in the folder

E:\vab_test_doc\edk_sys\pcores\fft_v1_00_a\hdl\vhdl .
resource\fft\fft4
to
Above steps are only PRM 1 (4 point fft calculation) for Reconfigurable Region 3. The
coming steps for PRM 2 (8 point fft calculation) for Reconfigurable Region 3.

Click Next.
Name it as fft with version 1.00.b and click Next.
click next. Shown in the figure 127
Figure 129 -Create Peripheral IP Interconnect (IPIC)
Click Next.
Click Next.
Click Next.

Openuser_logic.vhdfilefromE:\vab_edk_test\edk_sys\pcores\pcores\fft_v1_00_b\hdl\vhd
l directory and edit it to perform 8 point fft calculation. Clock the output and send the
result back via slave registers read (see the next diagram). Save the editing and close the
file as shown below
Copy all the VHDL files given in the folder

E:\vab_test_doc\edk_sys\pcores\fft_v1_00_b\hdl\vhdl .
resource\fft\fft8
to
Synthesize Peripherals
Step 4
In this section, we describes how IP peripherals will be synthesized to work as partial

reconfiguration module
Start ISE by selecting Start Programs Xilinx ISE 9.1i Project Navigatoras
shown in figure 133
Figure 133- Start ISE project
Figure 134-ISE project view
Open math [adder] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\math_v1_00_a\devl\projnav and selecting math.ise
Figure 135- ISE Design Flow Project Properties
Change device to xcv4fx60-ff1152-11 by double-clicking on xc2vp7-6fg456 (in sources

window) and selecting the desired device as in figure 135. (Family Virtex4) Check for
dotted box in Orange color in Fig 135
Select math module in Sources window, right-click on Synthesis in Processes window,

and change Synthesis property to disable I/O buffer insertion as this is a lower-level
module
Click OK to accept the settings.
Figure 136- Running synthesis option
Figure 137- Synthesis Output Report
Synthesize the design by double-clicking on Synthesis as in 136 and 137 in Processes

window and note down the resources used.
Using Windows Explorer, copy math.ngc from E:\vab_test_doc\edk_sys\pcores

\math_v1_00_a\devl\projnav to E:\vab_test_doc\PRRint\adder folder.
Open math [multiplier] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\math_v1_00_b\devl\projnav and selecting math.ise

window) and selecting the desired device as in done in math [adder].

module

Synthesize the design by double-clicking on Synthesis in Processes window and note
down the resources used.

\math_v1_00_b\devl\projnav to E:\vab_test_doc\PRRint\mult folder.
Open math [div] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\math_v1_00_c\devl\projnav and selecting math.ise

Select math module in Sources window, right-click on it , and go to Add Source
option. Browse to E:\vab_test_doc\edk_sys\pcores\math_v1_00_c\hdl\vhdl then select
div_int.vhd file. This file will be added to the project.
disable I/O buffer
and change Synthesis property to

insertion as
this is a lower-level module [RightClick Synthesize -> Choose Properties ->Tab Xilinx
Specific Options -> UnCheck Add I/O Buffers]


\math_v1_00_c\devl\projnav to E:\vab_test_doc\PRRint\div folder.
Open math [sub] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\math_v1_00_d\devl\projnav and selecting math.ise


module


\math_v1_00_d\devl\projnav to E:\vab_test_doc\PRRint\sub folder.
Open prr [add] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\prr_v1_00_a\devl\projnav and selecting prr.ise

Select prr module in Sources window, right-click on it, and go to Add Source option.
Browse to E:\vab_test_doc\edk_sys\pcores\prr_v1_00_a\hdl\vhdl then select all VHDL
file except user_logic.vhd and prr.vhd . These file will be added to the project.
Select prr module in Sources window, right-click on Synthesis in Processes window,

module

Using Windows Explorer, copy prr.ngc from E:\vab_test_doc\edk_sys\pcores

\prr_v1_00_a\devl\projnav to E:\vab_test_doc\PRRfloat\add folder.
Open prr [sub] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\prr_v1_00_b\devl\projnav and selecting prr.ise

Browse to E:\vab_test_doc\edk_sys\pcores\prr_v1_00_b\hdl\vhdl then select all VHDL
file except user_logic.vhd and prr.vhd . These file will be added to the project.

module


\prr_v1_00_b\devl\projnav to E:\vab_test_doc\PRRfloat\sub folder.
Open prr [div] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\prr_v1_00_c\devl\projnav and selecting prr.ise

Browse to E:\vab_test_doc\edk_sys\pcores\prr_v1_00_c\hdl\vhdl then select
div_flpt.vhd file . These file will be added to the project.

module


\prr_v1_00_c\devl\projnav to E:\vab_test_doc\PRRfloat\div folder.
Open prr [mul] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\prr_v1_00_d\devl\projnav and selecting prr.ise

Browse to E:\vab_test_doc\edk_sys\pcores\prr_v1_00_d\hdl\vhdl then select
mult_flpt.vhd file . These file will be added to the project.

module


\prr_v1_00_d\devl\projnav to E:\vab_test_doc\PRRfloat\mult folder.
Open fft [fft4] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\fft_v1_00_a\devl\projnav and selecting fft.ise

Select fft module in Sources window, right-click on it, and go to Add Source option.
Browse to E:\vab_test_doc\edk_sys\pcores\fft_v1_00_a\hdl\vhdl then select all files
except user_logic.vhd and fft.vhd file . These file will be added to the project.
Select fft module in Sources window, right-click on Synthesis in Processes window,

module

Using Windows Explorer, copy fft.ngc from E:\vab_test_doc\edk_sys\pcores

\fft_v1_00_a\devl\projnav to E:\vab_test_doc\PRRfft\fft4 folder.
Open fft [fft8] project (ISE) by selecting File Open Project and browsing to
E:\vab_test_doc\edk_sys\pcores\fft_v1_00_b\devl\projnav and selecting fft.ise

Select fft module in Sources window, right-click on it, and go to Add Source option.
Browse to E:\vab_test_doc\edk_sys\pcores\fft_v1_00_b\hdl\vhdl then select all files
except user_logic.vhd and fft.vhd file . These file will be added to the project.
Select fft module in Sources window, right-click on Synthesis in Processes window,

module

Using Windows Explorer, copy fft.ngc from E:\vab_test_doc\edk_sys\pcores
\fft_v1_00_b\devl\projnav to E:\vab_test_doc\PRRfft\fft8 folder.
Step 5
Create Top-Level Design
Select File New Project to create a new ISE project as in figure 138
Figure 138- ISE Design for top module
Figure 139- Create New Project Browse for project directory
Browse to E:\vab_test_doc using Browse button as in figure 139, Click OK.
Figure 140-New Project Wizard Create New Project
Let the name of the project be top in the project namefield (note that the directory
path is also appended with the name) as shown in figure 140.
Click Next.
Figure 141-New Project Wizard Device Properties
Select appropriate device property and click next as in figure 141.
Figure 142- New Project Wizard Add Existing Source
Click Add Source, browse to resource folder given, and select top.vhd, leaving
copy to project box checked as shown in figure 142.
Figure 143- New Project Wizard- Add Existing Source
Click Add Source, browse to E:\vab_test_doc\edk_sys folder and select

system.xmp, uncheck copy to project box, and click Next as in figure 143.
Click finish then Ok to open the project.
Figure 144- Synthesis of top file
Select top.vhd in Sources window and double-click Synthesize to synthesize the

design as shown in figure 144.
Close ISE.
Create a PlanAhead Project
Step 6
This step is performed to create a floor plan of the reconfigurable region and placment of
bus macros, clock and other resources.
Open PlanAhead as shown in figure 145 by selecting Start Programs Xilinx ISE
Design Suit 10.1 Xilinx PlanAhead 10.1. the Planahead will be open as shown in
figure 146.
Figure 145- start of Planahead Project
Figure 146- Planahead Window
Click on Create A New Project. Window like figure 147 will be opened. Click Next.
Figure 147- Create a New Planahead Project window
Figure 148-select project directory path
Browse to E:\vab_test_doc directory, as shown in the figure 148. Notice that the Project
name selected is project_1 (if you already have a project in that directory then the tool
will pick next project number) click Next.
Figure 149- Select Input option
Select Yes, import a synthesized (EDIF or NGC) fileand click Next as shown in the
figure 149.
Figure 150-Selecting top.ngc and other required macros for the project
Click browse button to browse to E:\vab_test_doc\top directory and select top.ngc as a

top-level NGC file.
Click on Add button and select E:\vab_test_doc\prrint\div directory to add NGC file
related to divider for integer type regions select E:\vab_test_doc\PRRfloat\div directory to
add NGC file related to divider for floating point type regions select
E:\vab_test_doc\prrfft\fft8 directory to add NGC file related to fft8 for FFTs regions.
Similarly, click on Add button again and select bus_macros directory (Resource Folder)
to add NMC files related to bus macros. All these steps are shown in figure 150
Figure 151-Chose Devic Family
Select the device family from the Choose Product Family page as in figure 151.
Figure 152- Select Device Part from the list
Click Next to go to the Select device family part as in figure 152 form and select
XC4VFX60FF1152-11 device, and then click OK followed by click on Next to go to
Import Constraints form.
Figure 153- adding constraint file
In Import Constraints form, click on Add button as in figure 153 and browse to
E:\vab_test_doc\edk_system\data directory and select system.ucf file. Click OK to
add it.
Figure 154- Set project as PR project
Select File Set PR Project to set the current project (project_1.ppr) as a PR project as
shown in figure 154.
system level constraints

Delete the respective lines from system.ucf incase any errors are popped, while creating project.
Create Area Groups and Place Components
Step 7
Figure 155- Draw Pblock for 1st region
Select U1 (Math) module in Netlist panel, right-click and select Draw Pblock, and
draw a rectangle covering SLICE_X30Y208:SLICE_X41Y255 as in figure 155. This
will create area group.
Figure 156-set that region as reconfiguration
Select U1 (Math) module, right-click and select Set Reconfigurable option as in

figure 156.
Figure 157-set name of PR instances
Name it as d as the divider netlist was selected when the project was created. Shown in
figure 157
The Previous steps are again executed to create PRR2 and PRR3.
Select U2 (prr) module in Netlist panel, right-click and select Draw Pblock, and draw a
rectangle covering SLICE_X56Y128:SLICE_X71Y255.
This will create area
group.Select U2 (prr) module, right-click and select Set Reconfigurable option.
Name it as d as the divider netlist was selected when the project was created.
Select U3 (fft) module in Netlist panel, right-click and select Draw Pblock, and draw a
rectangle covering SLICE_X54Y0:SLICE_X73Y93. This will create area group.Select
U3 (fft) module, right-click and select Set Reconfigurable option.
Name it as 8 as the fft8 netlist was selected when the project was created.
Select U1(Math) module, right-click and select Add Reconfigurable option.
Figure 158- adding reconfigurable module to U1
For U1, select the option Add Reconfigurable Moduleas shown in figure 158.
Figure 159-Add Module block
Click Next on the Add Reconfigurable Model window as figure 159.
Figure 160- Name the module name
Name the reconfigurable module as a, as adder is going to be added as in figure 160.
Figure 161-giving path to ngc file of add
Click Browse button, browse to E:\vab_test_doc\prrint\adder\, select math.ngc file,

and click Next and then Finish as shown in the figure 161.
The previous steps are repeated for all other modules respective to their regions.
Take screen shots here for all the modules
Figure 162- select Create Site Constraint Mode
Select Create Site Constraint Mode by clicking appropriate tool button (shown in Red
colour) as shown in figure 162 (This will allow us to place components in floorplan
window).
NTopPrmitivesABUS_0_BM _Generate[1].ABUS chk
ABUS_0_BM _Generate[2].
Control_1_0_BM
Control_2_0_BM
DBUS_0_BM _Generate[1].
SDBUS_0_BM_Generate[0]
video for files
Abus_
0_BM
_gen
[0]
to[4]
Place all bus macros on the left edge of the all PR regions example is as given in figure
163. (Two Inner & Two Outer)
Figure 163- Bus Macro Placement
Figure 163- Placement of DCM
Place dcm_0, dcm1, dcm_2 at DCM_ADV_X0Y6, DCM_ADV_X0Y7,

DCM_ADV_X0Y8. Shown in the figure 163. ( Here we have taken only dcm_0 and _1
and third _2 was ignored #DDR2, get clarified )
Figure 164- Run DRC
Select Tools Run DRC. Refer Figure 164
Click OK
Figure 165-ExploreAhead Window
At this stage, the ExploreAhead Runs tab should show static and 10 RM modules entry
as in figure 165
Run PR Flow
Step 7
This is last and final step. In this step, we assemble and merge the PRRs into full design.
Figure 166- Selection of BMM file
Before we run the PR Implementation flow, we need to set path to system_stub.bmm file
in order to generate system_stub_bd.bmm file after the implementation.
For this, select options tab in Run Properties view. Select bm option under ngdbuild
and click anywhere in the field.
Browse to E:\vab_test_doc\edk_sys\implementation, select system_stub.bmm file, and
click Open. As shown in the figure 167
Figure 167- Run Properties Window
Click Apply to have the option in effect as in figure 167.
Figure 168- Static Run
Select static in ExploreAhead Runs tab, right-click, and select Launch Run and
click OK to complete implementation as in figure 168
Figure 169- Run all individual runs
Same as above, select UI_d in ExploreAhead Runs tab, right-click, and select Launch
Runs as shown in the figure 169.
Figure 170- Lunch Run Window
Click OK to complete implementation. As shown in the figure 170
Repeat the same step for all reconfigurable modules
------------- Take screen shots here
Figure 171- Selection to Run PR Assemble
The last step in the PR Implementation flow is to run PR Assemble and PR Verify
design steps, which can be launched simultaneously by right-clicking one of the RM
modules and selecting Run PR Assemble. As shown in the figure 171.
Figure 172- Assembling of PR
Window will be pop-up as shown in the figure 172 to select the initial RM to be included
in static_full bit stream. Select divider as the initial RM module for region 1, select
divider as the initial RM module for region 2, select 8 as the initial RM module for
region 3 and
PR Assemble window will be popped out & process is in execution mode and keep
waiting, till you get OK dialog box as shown in Figure 173.
click OK to start the step.
Figure 173-Window popping Assembling is done
When the step is completed, click OK and Close buttons as shown in the figure 174.
Close PlanAhead, saving the project work.
Create Image and Test
Step 8
Using
Windows
Explorer,
browse
to:\vab_test_doc\project_1
\project_1.runs\floorplan_1\merge directory and copy pblock_u1_blank.bit,
u1_a_partial.
bit,
cu1_m_partial.
bitu1_d_partial.bit,
u1_s_partial.bit,
pblock_u2_blank.bit,
u2_a_partial.bit,
u2_m_part-ial.bit,
u2_d_partial.bit,
u2_s_partial.bit, pblock_u3_blank.bit, u3_8_partial.bit, u3_4_partial.bit and place
them as vaba_b.bit, vaba_a.bit, vaba_m.bit, vaba_d.bit, vaba_s.bit, vabb_b.bit,
vabb_a.bit, vabb_m.bit, vabb_d.bit, vabb_s.bit, vabc_b.bit, vabc_8.bit, vabc_4.bit
respectively in E:\vab_test_doc\bits folder
pblock_u1_blank.bit
vaba_b.bit
u1_a_partial. bit
vaba_a.bit
u1_m_partial. bit
vaba_m.bit
u1_d_partial.bit
vaba_d.bit
u1_s_partial.bit
vaba_s.bit
pblock_u2_blank.bit
vabb_b.bit
u2_a_partial.bit
vabb_a.bit
u2_m_part-ial.bit
vabb_m.bit
u2_d_partial.bit
vabb_d.bit
u2_s_partial.bit
vabb_s.bit
pblock_u3_blank.bit
vabc_b.bit
u3_8_partial.bit
vabc_8.bit
u3_4_partial.bit
vabc_4.bit
Using Windows Explorer, browse to E:\vab_test_doc\project_1\project_1.runs\floorplan_1\merge directory and copy static_full.bit and place it in
E:\vab_test_doc\bits folder
Using Windows Explorer, browse to E:\vab_test_doc\edk_sys\TestApp_Peripheral
directory and copy executable.elf and place it in E:\vab_test_doc\bits folder
Using Windows Explorer, browse to E:\vab_test_doc\edk_sys\implementation
directory and copy system_stub_bd.bmm and place it in E:\vab_test_doc\bits folder
Building VxWorks Image

Step 1
Select Software Software Platform Setting. As shown in figure 1
Figure 1- Selection of Software Platform Setting
Under software platform verify that vxworks6_3 is selected for ppc405_0. As shown in
the figure 2.
Figure 2- Software Platform Setting vxworks selection
Ensure these fields are set as follows as in figure 3

o STDIN RS232_Uart_1
o STDOUT RS232_Uart_1
Figure 3- Setting for RS232_Uart_1
Verify these peripherals are included in the pop-up dialog box as in 4

o RS232_Uart_1
o SysACE_Compactflash
Figure 4 -Add List of Parameters-Values
Select: SoftwareGenerate Libraries and BSPs. As shown in figure 5
Figure 5- Option to generate Libs and BSPs
The generated VxWorks BSP will be: E:\vab_test_doc\edk_sys\ppc405_0\bsp_ppc405_0
Copy E:\vab_test_doc\edk_system\ppc405_0 To C:\vab_test_doc_rtos on Vxworks

installed machine
Update these lines in the C:\vab_test_doc_rtos\bsp_ppc405_0\config.h file:

the green line as shown in figure 6
Set LOCAL_MEM_SIZE to 0x10000000
Set RAM_HIGH_ADRS to 0x10000000
Figure 6- Memory Map in config.h file
Update this line in the C:\vab_test_doc_rtos\bsp_ppc405_0\Makefile file: as in figure 7

Set RAM_HIGH_ADRS to 10000000
Figure 7 -Address specification in makefile
Update the splash message in the C:\vab_test_doc_rtos \bsp_ppc405_0\sysLib.c file:

shown in 8
From:
To:
ppc405_0 VirtexII Pro PPC405

Xilinx Virtex-4 FX PPC405
Figure 8 -Set argument for virtex 4 FX PPC405
10.3 Creating VxWorks System

1. Modify
following
lines
in
$PROJECT_DIR/ppc405_0/bsp_ppc405_0/config.h file:
i. Set LOCAL_MEM_SIZE to 0x10000000
ii. Set RAM_HIGH_ADRS to 0x10000000
2. Replicate
same
settings
in
$PROJECT_DIR/ppc405_0/bsp_ppc405_0/Makefile
3. Set RAM_HIGH_ADRS to 10000000
4. Create
$project_nameVxWorks
Image
Project
in
WindRiverWorkBench 2.5 using following settings:
a. A
board
support
package:
->
Browse
to
$PROJECT_DIR/ppc405_0/bsp_ppc405_0
b. Tool chain ->sfgnu
c. Edit the Kernel Configuration from the Tab under your
$project_name to additionally include
i. C++ components
ii. WDB agent -> WDB task breakpoints
iii. Loader -> Module Manager & Target Unloader
iv. Kernel shell components -> file system shell commands
v. Include RAM disk driver, XBD Block Device, XBD Disk
Partition, Handler, XBD Ram Drive
vi. Enable Cache from HW
vii. Set CONSOLE_Baud_ Rate to 9600
5. Code a new file & include it in project name it test.c. This file is
already given in resource folder
6. Rebuild Project to create VxWorks image (File has no extension).
For a detailed step-by-step execution, follow these snapshots:

Launch Wind River Workbench and select File New Project
Choose VxWorks Image Project. As shown in figure 9.
Set the project name to vabTest_prrr.
Set the location to C:\vab_test_doc_rtos and Click Next. Shown in figure
VXWORKS_SCR 88
Figure 9- select option
Figure 10- Setting for project name and location
Select the BSP by browsing to C:\vab_test_doc_rtosdirectory.
Select sfgnu (software floating point) from the Tool chain drop-down menu.
Click Next. As shown in figure 11
Figure 11 toolchain selection
Click Next twice
Click Next.
Click Finish.
Figure 12 -Finish completing project creation wizard
In the Project Navigator expand new created project vabTest_prr, right-click on

Kernel Configuration, and select Edit Kernel Configuration as shown in figure 13.
Figure 13- Edit Kernel Configuration
Include: C++ Components. Some components are pre-checked, leave them checked.
As shown in figure 13
Figure 13- C/C++ inclusion
Click Next and note the image size; then click Finish.
As shown in figure 14
Figure 14- Finish to complete C/C++ inclusion
Include: development tool components WDB agent components
Check WDB task breakpoints clickNext and then Finish. As shown is Figure 15
Figure 15- Selection for WDB task breakpoints
Include: loader components
Click Next and include module manager and target unloader and then click next and
finish as shown in figure 16
Figure 16- Final for WDB agent
Include: development tool components > kernel shell components
Check file system shell commands as shown in figure 16
Figure 16
Click Finish as shown in figure 17
Figure 17
Include: operating system components IO system components ->dosFs File System

Components
Check all boxes, except:

File System Backup and Archival
DOS File System Old Directory Format Handler
Check the following: as shown in figure 18 and click finish

RAM disk driver
XBD Block Device
XBD Disk Partition Handler
XBD Ram Drive
Figure 18- Selection for IO system components
Exclude: hardware memory enable caches. As in figure 19 and click finish
Figure 19- setting for memory caches
Expand hardware peripherals serial SIO. As shown in figure 20
Set CONSOLE_BAUD_RATE to 9600.
Figure 20- Serial port setting
Right-click on VxWorks image project new file. As in figure 21
This creates a file that associates with this image project.
Figure 21- Creating new file for Image
Give the name of the file as test.c and Finish. As in figure 22. This file is given in
resource folder.
Figure 22- Naming of application file

Following steps are required to run the Partial Reconfiguration program.
Properties Build Properties Link Order
button of xhwicap_zzzz (around 6 files)
Now add the header files using Add
Figure 23- Application for reconfiguration
Right-click VxWorks and select Rebuild Project. As in figure 24
This creates a VxWorks system image.
Note : Errors are expected here.

o All you need to do is to remove the comments mentioned with // comments
@syntax issues with VxWorks which considers /* comments */ as legitimate. Around
30 comments are required to be removed.
o Secondly replace print with printf for two lines, Incase any errors are listed.
A successful compile creates a VxWorks ELF kernel image

\default\vxWork
Figure 25- Building Image file
Using Windows Explorer, browse to E:\vab_test_doc\project_1\project_1.runs\floorplan_1\merge directory and copy static_full.bit and place it in
E:\vab_test_doc\bits folder
Using Windows Explorer, browse to E:\vab_test_doc\edk_sys\bootloopsdirectory and
copy ppc405.elf and place it in E:\vab_test_doc\bits folder
Open cmd shell by selecting Start Run go to the directory E:\vab_test_doc\bits
Execute the following command to generate download.bit file (having software
component included) from static_full.bit (having just hardware component)
data2mem bmsystem_stub_bd -btstatic_full.bit -bd ppc405.elf tag ppc405_0 o b

download.bit
This will generate download.bit in bits directory.
Using Windows Explorer copy all files (13 partial bits) from bits folder into CF card
(Make sure that there are no files in CF card before copying). The Format of CF should
be FAT12.
Place the CF card into board, start HyperTerminal window with 9600 baud rate, and
download download.bit file through impact.
Power Up Xilinx Board
Open XMD from XPS project.
Go to the Vxworks image folder.
Using cd command. Type dowvxworks then run command.
See the hyperterminal

Now run sysSystemAceMount(0,"/vab",1).
Run cd
vab.
Then typevab.
Do as instructed in menu
---------------------
Good Luck
----------------------------

PRR - Vxworks

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A step by step guide to implement of 3 Partial Reconfiguration Regions through ICAP

Installation can be verified by looking at the PR_assemble.pl

Create Processor System

Figure 1-opening XPS from program menu

Figure 2- selecting option to create project

Browse to drive:/vab_test_doc/ edk_system directory and click Save as in figure 3

Figure 3- giving project path to EDK tools

Base system Builder welcome will appear as in figure 4

Figure 4- BSB Wizard

Figure 5- BSB Wizard Select Board Option

Figure 6-BSB Wizard- Select Processor

Select PowerPC and Click Next in the figure 6

Figure 7- BSB Wizard - Configure PowerPC option

Processor CLK Frequency 100 MHz(defaultValue) and

Figure 8- BSB wizard Configure IO Interface

RS232_Uart_1 with 9600 baud rate,

Figure 9- BSB Wizard- Configure IO Interface option

Select SPI_EEPROM with include receive and transmit FIFO and

Figure 10- BSB Wizard- Configure IO option

Select SysAce_CompactFlash with use interrupt from this dialog box;

Figure 11- BSB Wizard- Configure IO option

deselect all of the option as in figure 11 Click Next

Figure 12- BSB Wizard- Configure IO option

Figure 13- BSB Wizard-Add Internal Peripheral option

Figure 14- BSB Wizard- software setup option

Figure 15- BSB Wizard- Summary

Click FINISH to end Base System Builder Wizard as in figure 15.

Figure 16- setting for user repository

Figure 17- Adding IPs to system

In IP Catalog tab as in figure 17, expand Project Local pcores and

Figure 18- selecting bus selection

Expand opb_dcr_socket_0, opb_dcr_socket_1, opb_dcr_socket_2 opb_hwicap_0, and

Figure 19- Address Space

opb_dcr_socket_2 instances, and then

Note : File Open system.mhs (@edksys folder)

Figure 20- Generate net- list

Figure 21- Software platform setting

Figure 22- Software Platform setting

Click OK to accept the settings and close the form.

Figure 23- Generate Libs and BSPs wizard

Figure 24- Build All User Application

Create Peripheral IPs for integer modules

Figure 25-Start to create or Import Peripheral Wizard

In XPS select Hardware Create/Import Peripheral Wizard as in figure 25.

Figure 26-Create or Import Peripheral Wizard-welcome wizard

Click Next twice, as in figure 26

Figure 27- Create or Import Peripheral Wizard-Peripheral Flow

Figure 28- Create or Import Peripheral Wizard-Repository or Project

Select To an XPS project option, click Browse button, browse to

Figure 29-Create or Import Peripheral Wizard-Create Peripheral- Name and Version

Name it as math with version 1.00.a and click Next.

Figure 30- Create or Import Peripheral Wizard Bus Interface

Figure 31- Create Peripheral IPIF Interface

Figure 32- Create Peripheral User S/W Register

Figure 33-Create Peripheral IP Interconnect (IPIC)

Figure 34- Create Peripheral Peripheral Simulation Support

Figure 35-Create Peripheral Peripheral Implementation Support

Figure 36-Create Peripheral Finish Wizard

Click Finish to complete the IP creation as in figure 36.

Open user_logic.vhd file from

Figure 37-Start to create or Import Peripheral Wizard

In XPS select Hardware Create/Import Peripheral Wizard as in figure 37.

Figure 38-Create or Import Peripheral Wizard-welcome wizard