1.

Overview

Name
Technology

TES18V28IO

TES18V28IO
28nm

2. Features
1. LVCMOS Compatible 1.8V input receiver and output driver
2. Build in JTAG MUXes for input receiver and output driver
3. Maximum operating frequency 50MHz

3. Functionality
The design incorporates internal reference bias circuits to allow reliable 3.3V
(+10%/-10%) operation using only the 1.8V devices
Buffer operation at voltages greater than 3.75 V may severely degrade the
lifetime of the device and should be avoided.
The buffer also has a built in boundary Scan logic for ease of testing. When
JTAGAS=JTAGOES=JTAGZS=0 the buffer is in normal mode and when
JTAGAS=JTAGOES=JTAGZS=1 the buffer is in the Boundary Scan mode for testing.

Fig 1

TES18V28IO

4. Pin Order and Supply list

S. No
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.

Pin Name
A
JTAGA
JTAGAS
OE
JTAGOE
JTAGOES
JTAGZI
JTAGZ
JTAGZS
P3U
P3D
JTAGAZ
JTAGOEZ
JTAGZI
ZI
PAD

Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Inout

Description
Input to output driver
Test Mode substitute for A input to output driver
Selects JTAGA rather than A when High
Tristate driver, Active Low
Test Mode Substitution for OE input to output driver
Selects JTAGOE rather than OE when High
Buffered test mode output of the receiver
Test-mode replacement for the output of the receiver
Selects JTAGZI instead of receiver output when HIGH
Enables 100K pull up resistor
Enables 100K pull down resistor
Output of A, JTAG mux
Output of OE,JTAG mux
Buffered test mode output of receiver
Receiver data to I/O cell core
PAD IO node

17. Functionality Truth Tables

JTAG Mux Functional operation:

Inputs
A

X
X
X
X
X
X
X
X

JTAGA

0
1
0
1
0
1
0
1

JTAGAS

1
1
1
1
1
1
1
1

JTAGOES

Outputs

OE

JTAGOE

PAD

X
X
X
X
X
X
X
X

JTAG Mode, JTAG Mux Function

0
1
X
0
1
0
1
X
0
1
1
1
X
0
1
1
1
X
0
1
0
1
X
1
1
0
1
X
1
1
1
1
X
1
1
1
1
X
1
1

Normal Mode Operation:

(JTAGAS=JTAGOES = 0)
Inputs
A

JTAGZ

JTAGZS

0
1

X
X

0
0

OE

JTAGZ

JTAGZS

P3D

JTAGAZ

JTAGOEZ

JTAGZI

ZI

0
1
0
1
0
1
0
1

0
0
1
1
0
0
1
1

0
0
0
0
1
1
1
1

0
0
0
0
1
1
1
1

Outputs
P3U

PAD

JTAGZI

1

X
X
Z
0
1

X
X
Z
1
Normal input mode Output tri-stated with OE =0
0
0

X
X
0
0

ZI

PAD

0
1

0
1

TES18V28IO

X
0
0

X
X
1
1
1
1
Normal input mode Output tri-stated with OE =0,Pullup/Pull-down Function
X
0
0

0
0
Z
U
U
Z
X
0
0

0
1
Z
1
1
H
X
0
0

1
0
Z
0
0
L
X
0
0

1
1
Z
U
U
Z

X
X
X
X

JTAG Mode Operation

Functional JTAG Mode Operation with Output JTAG paths selected
(JTAGAS=JTAGOES=1)

Input

JTAGA

JTAGZ

JTAGZS

JTAGOE

P3D

P3U

PAD

Output
JTAGZI

ZI

PAD

JTAG Output Mode

0
0
1
1
X
X
Z
0
0
0
1
0
1
1
X
X
Z
0
0
1
0
1
1
1
X
X
Z
1
1
0
1
1
1
1
X
X
Z
1
1
1
JTAG Input Mode Output Tri-Stated with OE=0
X
0
1
0
X
X
0
0
0
0
X
0
1
0
X
X
1
0
0
1
X
1
1
0
X
X
0
1
1
0
X
1
1
0
X
X
1
1
1
1
JTAG Input Mode, Output Tri-Stated with OE, and Pull-up /Pull-down Function
X
X
0
1
0
0
Z
0
0
Z
X
X
1
1
0
0
Z
1
1
Z
X
X
0
1
0
1
Z
0
0
H
X
X
1
1
0
1
Z
1
1
H
X
X
0
1
1
0
Z
0
0
L
X
X
1
1
1
0
Z
1
1
L
X
X
0
1
1
1
Z
0
0
Z
X
X
1
1
1
1
Z
1
1
Z